CTNF 18/131,980 CTNF 82440 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-20 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Singhai et al. (US 2016/0162352) . Consider claim 1 , Singhai et al. discloses an apparatus comprising: an interface to a memory pool; and a processor operable to execute one or more instructions to cause the processor to: determine a first memory region of a plurality of memory regions in the memory pool; and modify a metadata of the first memory region from a first configuration to a second configuration, wherein the first configuration is associated with a first number of error correction code (ECC) bits and the second configuration is associated with a second number of ECC bits (abstract, [0013]-[0014], [0021], [0027]-[0030], table 1 and 2, Singhai et al. discloses a blocks a memory being grouped together based on degradation of the blocks. The ECC mechanism is adaptive to those conditions, thus giving different groupings of blocks different ECC schemes that utilize different amounts of ECC code bits.) . Consider claim 2 , Singhai et al. discloses the apparatus of claim 1 , wherein the first number of ECC bits is different than the second number of ECC bits (abstract, [0013]-[0014], [0021], [0027]-[0030], table 1 and 2, Singhai et al. discloses different groupings of blocks having different ECC schemes that utilize different amounts of ECC code bits.) . Consider claim 3 , Singhai et al. discloses the apparatus of claim 1 , wherein the first configuration is associated with a first number of bits for a service, wherein the second configuration is associated with a second number of bits for the service (abstract, [0013]-[0014], [0021], [0027]-[0030], table 1 and 2, Singhai et al. discloses different groupings of blocks having different ECC schemes that utilize different amounts of ECC code bits.) . Consider claim 4 , Singhai et al. discloses the apparatus of claim 3 , wherein the service is to comprise one or more of a security service, an encryption service, an isolation service, or an interconnect protocol service (abstract, [0013]-[0014], [0021], [0027]-[0030], table 1 and 2, Singhai et al. discloses an adaptive ECC system.) . Consider claim 5 , Singhai et al. discloses the apparatus of claim 1 , the processor operable to execute the one or more instructions to cause the processor to, prior to modifying the metadata: receive a request to modify the metadata of the first memory region (abstract, [0013]-[0014], [0021], [0027]-[0030], table 1 and 2, Singhai et al. discloses that blocks are continuously monitored and when the conditions of a block require an improved ECC scheme, a new scheme is employed.) . Consider claim 6 , Singhai et al. discloses the apparatus of claim 1 , the processor operable to execute the one or more instructions to cause the processor to, prior to modifying the metadata: determine an error rate of the first memory region; and determine to modify the metadata of the first memory region based on the error rate (abstract, [0013]-[0014], [0021], [0027]-[0030], table 1 and 2, Singhai et al. discloses that blocks are continuously monitored and when the conditions of a block require an improved ECC scheme, a new scheme is employed.) . Consider claim 7 , Singhai et al. discloses the apparatus of claim 1 , the processor operable to execute the one or more instructions to cause the processor to: determine a Quality of Service (QoS) parameter for the first memory region; and migrate the first memory region to a second memory region of the plurality of memory regions based on the QoS parameter for the first memory region (abstract, [0013]-[0014], [0021], [0024], [0027]-[0030], table 1 and 2, Singhai et al. discloses determining the error count of a block an associating it with the correct group.) . Consider claim 8 , Singhai et al. discloses the apparatus of claim 1 , the processor operable to execute the one or more instructions to cause the processor to: determine a Quality of Service (QoS) parameter for the first memory region; and modify the first memory region to include a second memory region of the plurality of memory regions based on the QoS parameter for the first memory region (abstract, [0013]-[0014], [0021], [0024], [0027]-[0030], table 1 and 2, Singhai et al. discloses determining the error count of a block an associating it with the correct group.) . Consider claim 9 , Singhai et al. discloses the apparatus of claim 1 , wherein the interface to the memory pool is to be based on the Compute Express Link standard ([0017]-[0018], PCI express is disclosed which is a based on CXL to be implemented on.) . Consider claim 10 , Singhai et al. discloses the apparatus of claim 1 , further comprising a memory controller configured to, subsequent to the modification of the metadata: determine, based on the second number of ECC bits, one or more ECC bits in the metadata for a first memory line of the first memory region; compute an ECC value based on the first memory line of the first memory region; and compare the ECC value to the one or more ECC bits in the metadata for the first memory line of the first memory region (abstract, [0013]-[0014], [0021], [0024], [0027]-[0030], table 1 and 2, Singhai et al. discloses determining the error count of a block an associating it with the correct group.) . Consider claim 21 , Singhai et al. discloses a non-transitory computer-readable storage medium storing instructions that when executed by a processor cause the processor to: map a first address space of a plurality of address spaces to a first set of memory features, wherein the first set of memory features includes a first number of error correction code (ECC) bits, wherein the first address space is mapped to a first memory region of a plurality of memory regions of physical memory in a memory pool; and map a second address space of the plurality of address spaces to a second set of memory features, wherein the second set of memory features includes a second number of ECC bits, wherein the second number of ECC bits is different than the first number of ECC bits, wherein the second address space is mapped to a second memory region of the plurality of memory regions of physical memory in the memory pool (abstract, [0013]-[0014], [0021], [0027]-[0030], table 1 and 2, Singhai et al. discloses a blocks a memory being grouped together based on degradation of the blocks. The ECC mechanism is adaptive to those conditions, thus giving different groupings of blocks different ECC schemes that utilize different amounts of ECC code bits.) . Consider claim 22 , Singhai et al. discloses the non-transitory computer-readable storage medium of claim 21 , wherein the first set of memory features is associated with a first number of bits for a service, wherein the second set of memory features is associated with a second number of bits for the service (abstract, [0013]-[0014], [0021], [0027]-[0030], table 1 and 2, Singhai et al. discloses different groupings of blocks having different ECC schemes that utilize different amounts of ECC code bits.) . Consider claim 23 , Singhai et al. discloses the non-transitory computer-readable storage medium of claim 22 , wherein the service is to comprise one or more of a security service, an encryption service, an isolation service, or an interconnect protocol service (abstract, [0013]-[0014], [0021], [0027]-[0030], table 1 and 2, Singhai et al. discloses an adaptive ECC system.) . Claims 11-15 are the method claims to apparatus claims 1, 3, 4, 6 and 9 above and are rejected in the same manner. Claims 16-20 are the medium claims to apparatus claims 1, 3-5 and 9 above and are rejected in the same manner . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G. Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL ALSIP/Primary Examiner, Art Unit 2139 Application/Control Number: 18/131,980 Page 2 Art Unit: 2139 Application/Control Number: 18/131,980 Page 3 Art Unit: 2139 Application/Control Number: 18/131,980 Page 4 Art Unit: 2139 Application/Control Number: 18/131,980 Page 5 Art Unit: 2139
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