DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 8 and 9, reference is made to "the adiabatic clock driver circuitry." However, there is no such circuitry in parent claim 1. It is unclear which element of claim 1 is being referenced by the adiabatic clock driver circuitry.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 and 20-26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Salem (US 2018/0226969).
Regarding claim 1, fig. 2 and 3 of Salem teach a device comprising: a clock driver that provides an adiabatic stepwise clock signal via an output node [between s1 and s4], wherein the clock driver is coupled between a supply voltage [at top of s4] and ground [at bottom of s1]; and selectively switched stages [s2,C1 and s3,C2] with each selectively switched stage having a capacitor [C1,C2] and a transistor [s2,s3] (fig. 3A) coupled in series between the output node and ground, wherein each capacitor refers to an auxiliary tank capacitor that is electrically isolated from each other auxiliary tank capacitor (as shown in fig. 3A when the switched circuit topology is such that the number of steps is 4 where the separate voltage levels are ground, 1/3 VDD, 2/3 VDD, and VDD, meaning not the switched circuit topology where the number of steps is 3 when C1 and C2 are connected together such that the voltage levels are ground, ½ VDD, and VDD) (as further shown in fig. 2B where each auxiliary tank capacitor C1 and C2 is always physically separated and electrically isolated from the other auxiliary tank capacitor during each of the four stages of operation) (par. 19), and wherein the selectively switched stages include a first stage [s3, C2] having a first capacitor [C2] and a second transistor [s3] coupled in series between the output node and ground, wherein a source terminal of the second transistor is connected to the output node and a drain terminal of the second transistor is connected to the first capacitor (when s3 conducts).
Regarding claim 2, fig. 2 and 3 of Salem teach wherein: the clock driver has a first transistor [s1] coupled between the output node and ground, and when selectively activated with a first switch signal, the clock driver provides a first voltage that is approximately similar to ground or a ground voltage.
Regarding claim 3, fig. 2 and 3 of Salem teach wherein: the selectively switched stages include a second stage [s2, C1] having a second capacitor [C1] and a third transistor [s2] coupled in series between the output node and ground, wherein a drain terminal of the third transistor is connected to the output node and a source terminal of the third transistor is connected to the second capacitor, and when selectively activated with a second switch signal, the second stage provides a second voltage that is approximately one-third (1/3) of the supply voltage (see fig. 2A where VC1=VDD/3).
Regarding claim 4, fig. 2 and 3 of Salem teach wherein: when selectively activated with a third switch signal, the first stage provides a third voltage that is approximately two-thirds (2/3) of a supply voltage (see fig. 2A where VC2=2VDD/3).
Regarding claim 5, fig. 2 and 3 of Salem teach wherein: the clock driver has a fourth transistor [s4] coupled between the supply voltage and the output node, and when selectively activated with a fourth switch signal, the clock driver provides a fourth voltage that is approximately similar to the supply voltage.
Regarding claim 6, fig. 2 and 3 of Salem teach an output capacitor [CCLK] coupled between the output node and ground, wherein the output capacitor is charged by the adiabatic stepwise clock signal.
Regarding claim 20, this claim is merely a method to operate the circuit having structure recited in claim 1. Since Salem above teaches the structure, the method to operate such a circuit is similarly disclosed.
Regarding claim 21, fig. 2 and 3 of Salem teach wherein the auxiliary tank capacitor is always electrically isolated from the other auxiliary tank capacitor (as shown in fig. 3A when the switched circuit topology is such that the number of steps is 4 where the separate voltage levels are ground, 1/3 VDD, 2/3 VDD, and VDD, meaning not the switched circuit topology where the number of steps is 3 when C1 and C2 are connected together such that the voltage levels are ground, ½ VDD, and VDD) (par. 19).
Regarding claim 22, fig. 2 and 3 of Salem teach wherein the supply voltage coupled to each auxiliary tank capacitor is at least one of electrically isolated and physically separated from the supply voltage coupled to each other auxiliary tank capacitor.
Regarding claim 23, fig. 2 and 3 of Salem teach wherein each auxiliary tank capacitor is coupled to a non-shared supply voltage node that is distinct from each respective intermediate supply voltage node of each other auxiliary tank capacitor through each functional activation mode of the clock driver (fig. 2B).
Regarding claim 24, fig. 2 and 3 of Salem teach wherein each auxiliary tank capacitor has a positive electrode that is coupled to the supply voltage coupled to each auxiliary tank capacitor, the positive electrode being electrically isolated and physically separated from the positive electrode of each other auxiliary tank capacitor (fig. 2B).
Regarding claim 25, fig. 2 and 3 of Salem teach wherein the auxiliary tank capacitors share a common ground line while each being coupled to a separate supply voltage path that is physically separated and electrically isolated from a supply voltage path of each other auxiliary tank capacitor.
Regarding claim 26, fig. 2 and 3 of Salem teach wherein a combined capacitance of the auxiliary tank capacitors is defined relative to a capacitance of an output capacitor [CCLK] coupled between the output node and ground.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Salem in view of Cho (US 7,750,706).
Regarding claim 7, Salem teaches the device as indicated above except for wherein each auxiliary tank capacitor refers to a MIMCAP (metal-insulator-metal capacitor). However, Cho describes implementing capacitors as MIMCAPs (col. 1, lines 39-41). In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the MIMCAP capacitor design as taught in Cho for the purpose of utilizing a suitable and well-known type of capacitor implementation.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Salem in view of Kang (US 2024/0203792).
Regarding claim 8, Salem teaches the device as indicated above except wherein: the adiabatic clock driver circuitry refers to frontside clock circuitry that is disposed above a substrate, and each auxiliary tank capacitor is disposed above the substrate as part of a frontside power distribution network that is coupled to the frontside clock circuitry. However, Kang describes implementing semiconductor devices on the frontside of the structure (¶20). In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the frontside structure for clock drivers for the purpose of utilizing a suitable and well-known type of structural fabrication.
Regarding claim 9, Salem teaches the device as indicated above except wherein: the adiabatic clock driver circuitry refers to frontside clock circuitry that is disposed above a substrate, and each auxiliary tank capacitor is disposed below the substrate as part of a frontside power distribution network that is coupled to the frontside clock circuitry. However, Kang describes implementing semiconductor devices on the frontside of the structure while keeping other components on the backside of the structure (¶20). In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the frontside structure for clock drivers and the backside structure for devices such as the auxiliary tank capacitors for the purpose of utilizing a suitable and well-known type of structural fabrication.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Salem in view of Yamagishi (US 6,336,190).
Regarding claim 10, Salem teaches the device as indicated above except for further comprising: one or more additional clock drivers; and one or more additional selectively switched stages of capacitors and transistors, wherein combination of each additional clock driver and each additional selectively switched stage is coupled in parallel with combination of each other additional clock driver and each other selectively switched stage. However, Cho describes a plurality of clock generators circuits (such as that of Salem) in parallel (col. 4, lines 23-39). In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the parallel design as taught in Yamagishi for the purpose of utilizing a suitable and well-known type of clock generation design.
Response to Arguments
Applicant's arguments filed 12/26/25 have been fully considered but they are not persuasive.
Regarding claims 1 and 20, applicant contends that Salem does not disclose wherein the selectively switched stages include a first stage having a first capacitor and a second transistor coupled in series between the output node and ground, wherein a source terminal of the second transistor is connected to the output node and a drain terminal of the second transistor is connected to the first capacitor. However, Salem discloses wherein the selectively switched stages include a first stage [s3, C2] having a first capacitor [C2] and a second transistor [s3] coupled in series between the output node and ground, wherein a source terminal of the second transistor is connected to the output node and a drain terminal of the second transistor is connected to the first capacitor (when s3 conducts).
Regarding claim 9, applicant contends that Kang does not disclose the driver circuitry on the frontside of the substrate and tank capacitors on the backside. However, Kang discloses incorporating elements on both the frontside and backside of a device, where they may be connected through the substrate. In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the frontside structure for clock drivers and the backside structure for devices such as the auxiliary tank capacitors for the purpose of utilizing a suitable and well-known type of structural fabrication.
Regarding claim 10, applicant contends that Yamagishi does not disclose a combination of an additional clock driver and an additional selectively switched stage is coupled in parallel with the combination of another additional clock driver and another selectively switched stage. However, as illustrated in Salem, the switchable stages generating to the output are configured in parallel. As more switched stages are added to provide different outputs, these would also be added in parallel.
Conclusion
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/SIBIN CHEN/ Primary Examiner, Art Unit 2836
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