Detailed Action
1. This office action is in response to communication filed December 24, 2025. Claims 1-20 are currently pending and claims 1 and 18 are the independent claims.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
3. This Final Office Action is in response to the applicant’s remarks and arguments filed on December 24, 2025.
Claims 1, 6, 10, and 18 are amended. No claims have been cancelled. No claims are new. Claims 1-20 remain pending in the application. Claims 2-5, 7-9, 11-17, and 19-20 filed on April 7, 2023 are being considered on the merits along with amended claims 1, 6, 10, and 18.
Response to Arguments
4. Applicant’s arguments, see Remarks section 35 U.S.C. 102 REJECTIONS, filed December 24, 2025, with respect to the rejections of claims 1-2, 4-9, 11, 14, 18, and 20 as anticipated by Phatak have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made via Phatak in view of Xia under 35 U.S.C. 103. The following response to the Remarks submitted by the Applicant includes:
The Applicant respectfully submitted on page 5 of the Remarks under section 35 U.S.C. 112 REJECTIONS that claim 6’s 112(b) rejection should be withdrawn.
A. The Examiner has removed the rejection under 35 U.S.C. 112 based on the Applicant’s amendment to claim 6 fixing the indefinite nature of the original claim.
The Applicant respectfully submitted on pages 5-7 of the Remarks under section 35 U.S.C. 101 REJECTIONS that the claims are not directed to an abstract idea and that the claims amount to significantly more.
B. The Examiner disagrees with the Applicant’s assertions made regarding the rejections made under 35 U.S.C. 101. The Examiner does not claim that the simulation of the devices is an abstract idea, rather than the simulation of the devices is an “apply it” step while the determination of the hardware devices and enabling of the user selection of the simulation of these devices are the abstract ideas. Additionally, the selection of the fidelity is done with the support of generic computing components (“one or more computing devices” in claim 1). The Examiner requires further amendment to the claims to overcome the 101 rejections. Clarification of these computing devices and further details regarding the simulation are suggested avenues of amendment to overcome the current 101 rejections.
The Applicant respectfully submitted on pages 7-9 of the Remarks under section 35 U.S.C. 102 REJECTIONS that Phatak fails to fully teach each and every limitation of claim 1 and its correspond dependent claims rejected under 35 U.S.C. 102.
C. As mentioned above, the Examiner fully considered the Applicant’s statements on the 102 rejections and decided the arguments are persuasive. The Examiner has thus withdrawn the rejections under 35 U.S.C. 102 and updated the rejections to be made under 35 U.S.C. 103 via Phatak in view of Xia, seen in section 7 below.
The Applicant respectfully submitted on pages 9-10 of the Remarks under section 35 U.S.C. 103 REJECTIONS that the prior art including Phatak, Hyodo, Xia, and Iuniana Oprescu fails to fully teach claims 3, 10, 12-13, 15-17, and 19.
D. The Examiner respectfully disagrees with the assertions of the Applicant regarding claims 3, 10, 12-13, 15-17, and 19. The combination of Phatak, Xia, and Hyodo teaches the limitation of user selection of fidelity levels for hardware devices and determining this level of fidelity “based on desired processing speed and accuracy of the simulation of each hardware device.” The combination of Phatak and Xia again teaches the limitation of user selection of fidelity levels for specific hardware devices along with configuring the fidelity of simulated elements to optimize the simulation resource usage. The combination of Phatak, Xia, and Iuniana Oprescu again teaches the limitation of user selection of fidelity levels for specific hardware devices along with RPC usage to sent requests between a user and a hypervisor.
E. The Examiner respectfully includes the rejections for claims 1-20 under 35 U.S.C 101 and 35 U.S.C. 103 in this Final Office Action.
Claim Objections
5. Claim 1 is objected to because of the following informalities:
The second claim limitation in claim 1 states “enable a user to select a level of fidelity of the simulation for each of the plurality hardware devices;” which should state “enable a user to select a level of fidelity of the simulation for each of the plurality of hardware devices;”
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
6. Claim 1 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim recites “A system for hardware simulation framework, comprising: one or more computing devices configured to: determine a plurality of hardware devices for testing using simulation; enable a user to select a level of fidelity of the simulation for each of the plurality hardware devices; and simulate, in the one or more computing devices using software binaries, each of the plurality of hardware devices based on the selected level of fidelity.”
Under Step 2A, Prong I, the limitation “determine a plurality of hardware devices for testing using simulation” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. For example, a person may determine a group of hardware devices to simulate for testing on a sheet of paper with pen or mentally by selecting hardware devices from a list of available hardware devices to test. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Step 2A, Prong I, the limitation “enable a user to select a level of fidelity of the simulation for each of the plurality hardware devices” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. For example, a person may determine a level of fidelity of the simulation for each hardware device with pen or mentally by making a judgement for each individual hardware device such that devices can range from low to high fidelity with any selection available in between as well. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular under step 2A Prong II, claim 1 recites the additional elements “A system for hardware simulation framework, comprising: one or more computing devices configured to: … simulate, in the one or more computing devices using software binaries, each of the plurality of hardware devices based on the selected level of fidelity.” The additional element “one or more computing devices” is an example of generic computing components that are used to run hardware simulation. Additionally, the additional element “simulate, in the one or more computing devices using software binaries, each of the plurality of hardware devices based on the selected level of fidelity” represents the “apply it” step which is a mere instruction to apply an exception (2106.05(f)). The additional limitation amounts to mere instructions to apply an exception of simulating the plurality of hardware devices based on the user-selected level of fidelity using software binaries/files. The claim is directed to an abstract idea.
Under Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract ideas into a practical application, the additional elements “one or more computing devices” and “simulate, in the one or more computing devices using software binaries, each of the plurality of hardware devices based on the selected level of fidelity” are recognized by the courts as well-understood, routine, and conventional activities when they are claimed in a merely generic manner (see MPEP 2106.05(d)(II)(iv) Storing and retrieving information in memory, Versata Dev. Group Inc.). The additional elements that are well- understood, routine, conventional activity do not amount to significantly more, and are thus, not an inventive concept. Accordingly, the claim does not appear to be patent eligible under 35 U.S.C. 101.
As per claim 2, it incorporates the deficiencies of independent claim 1 upon which it depends, and further recites “wherein the system further comprises a plurality of virtual machines and a virtual machine orchestrator (analyzed under Prong II Step 2A & 2B as additional elements).” These additional elements do not integrate the abstract idea/mental process into a practical application and are not significantly more than the judicial exception. Therefore, claim 2 fails to correct the deficiencies of claim 1 and is rejected for similar reasoning as claim 1, above.
As per claim 3, it incorporates the deficiencies of independent claim 1 upon which it depends, and further recites “wherein the level of fidelity of the simulation for each of the plurality of hardware devices is determined based on desired processing speed and accuracy of the simulation of each hardware device (analyzed under Prong I Step 2A as directing to an abstract idea under the mental process).” If a claim limitation, under its broadest
reasonable interpretation, covers performance of the limitation in the mind, then it falls within
the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract
idea. Therefore, claim 3 fails to correct the deficiencies of claim 1 and is rejected for similar
reasoning as claim 1, above.
As per claim 4, it incorporates the deficiencies of independent claim 1 upon which it depends, and further recites “wherein the fidelity levels are changed using a graphical user interface or text files (analyzed under Prong II Step 2A & 2B as additional element).” This additional element does not integrate the abstract idea/mental process into a practical application and is not significantly more than the judicial exception. Therefore, claim 4 fails to correct the deficiencies of claim 1 and is rejected for similar reasoning as claim 1, above.
As per claim 5, it incorporates the deficiencies of independent claim 1 upon which it depends, and further recites “further comprising an entity-relationship model, wherein the entity-relationship model describes configurations of the plurality of hardware devices (analyzed under Prong II Step 2A & 2B as additional elements).” These additional elements do not integrate the abstract idea/mental process into a practical application and are not significantly more than the judicial exception. Therefore, claim 5 fails to correct the deficiencies of claim 1 and is rejected for similar reasoning as claim 1, above.
As per claim 6, it incorporates the deficiencies of dependent claim 5 upon which it depends, and further recites “further comprising a simulation builder, wherein the simulation builder automatically simulates each of the plurality of hardware devices based on the entity-relationship model (analyzed under Prong II Step 2A & 2B as additional elements).” These additional elements do not integrate the abstract idea/mental process into a practical application and are not significantly more than the judicial exception. Therefore, claim 6 fails to correct the deficiencies of claim 5 and is rejected for similar reasoning as claim 5, above.
As per claim 7, it incorporates the deficiencies of dependent claim 5 upon which it depends, and further recites “wherein the simulated each of the plurality of hardware devices are integrated into a distributed production software stack and network (analyzed under Prong II Step 2A & 2B as additional elements).” These additional elements do not integrate the abstract idea/mental process into a practical application and are not significantly more than the judicial exception. Therefore, claim 7 fails to correct the deficiencies of claim 5 and is rejected for similar reasoning as claim 5, above.
As per claim 8, it incorporates the deficiencies of independent claim 1 upon which it depends, and further recites “wherein each of the simulated hardware devices mimic functions of each of the hardware devices (analyzed under Prong II Step 2A & 2B as additional element).” This additional element does not integrate the abstract idea/mental process into a practical application and is not significantly more than the judicial exception. Therefore, claim 8 fails to correct the deficiencies of claim 1 and is rejected for similar reasoning as claim 1, above.
As per claim 9, it incorporates the deficiencies of independent claim 1 upon which it depends, and further recites “wherein each of the simulated hardware devices are either partially simulated or fully simulated (analyzed under Prong II Step 2A & 2B as additional element).” This additional element does not integrate the abstract idea/mental process into a practical application and is not significantly more than the judicial exception. Therefore, claim 9 fails to correct the deficiencies of claim 1 and is rejected for similar reasoning as claim 1, above.
As per claim 10, it incorporates the deficiencies of independent claim 1 upon which it depends, and further recites “wherein the simulated hardware devices are connected to a hypervisor via an application programming interface (API) layer (analyzed under Prong II Step 2A & 2B as additional element).” This additional element does not integrate the abstract idea/mental process into a practical application and is not significantly more than the judicial exception. Therefore, claim 10 fails to correct the deficiencies of claim 1 and is rejected for similar reasoning as claim 1, above.
As per claim 11, it incorporates the deficiencies of dependent claim 2 upon which it depends, and further recites “wherein each of the virtual machines is either a persistent virtual machine or a transitory virtual machine (analyzed under Prong II Step 2A & 2B as additional element).” This additional element does not integrate the abstract idea/mental process into a practical application and is not significantly more than the judicial exception. Therefore, claim 11 fails to correct the deficiencies of claim 2 and is rejected for similar reasoning as claim 2, above.
As per claim 12, it incorporates the deficiencies of dependent claim 2 upon which it depends, and further recites “wherein the virtual machine orchestrator utilizes a remote procedure call (RPC) to enable interaction between the plurality of virtual machines using different languages in different manners (analyzed under Prong II Step 2A & 2B as additional element).” This additional element does not integrate the abstract idea/mental process into a practical application and is not significantly more than the judicial exception. Therefore, claim 12 fails to correct the deficiencies of claim 2 and is rejected for similar reasoning as claim 2, above.
As per claim 13, it incorporates the deficiencies of dependent claim 2 upon which it depends, and further recites “wherein the virtual machine orchestrator communicates with one or more simulated hardware devices using smart network interface cards in the network, wherein the smart network interface cards can be simulated based on a user selection (analyzed under Prong II Step 2A & 2B as additional elements).” These additional elements do not integrate the abstract idea/mental process into a practical application and are not significantly more than the judicial exception. Therefore, claim 13 fails to correct the deficiencies of claim 2 and is rejected for similar reasoning as claim 2, above.
As per claim 14, it incorporates the deficiencies of dependent claim 2 upon which it depends, and further recites “wherein the virtual machine orchestrator provides a configurable level of abstraction, for the simulation (analyzed under Prong II Step 2A & 2B as additional elements).” These additional elements do not integrate the abstract idea/mental process into a practical application and are not significantly more than the judicial exception. Therefore, claim 14 fails to correct the deficiencies of claim 2 and is rejected for similar reasoning as claim 2, above.
As per claim 15, it incorporates the deficiencies of dependent claim 2 upon which it depends, and further recites “wherein the virtual machine orchestrator is further configured to inject deterministic errors of the hardware devices into the simulated hardware devices for testing errors (analyzed under Prong II Step 2A & 2B as additional elements).” These additional elements do not integrate the abstract idea/mental process into a practical application and are not significantly more than the judicial exception. Therefore, claim 15 fails to correct the deficiencies of claim 2 and is rejected for similar reasoning as claim 2, above.
As per claim 16, it incorporates the deficiencies of dependent claim 2 upon which it depends, and further recites “wherein the virtual machine orchestrator is further configured to simulate a baseboard management controller to manage a physical state of the hardware devices (analyzed under Prong II Step 2A & 2B as additional element).” This additional element does not integrate the abstract idea/mental process into a practical application and is not significantly more than the judicial exception. Therefore, claim 16 fails to correct the deficiencies of claim 2 and is rejected for similar reasoning as claim 2, above.
As per claim 17, it incorporates the deficiencies of dependent claim 16 upon which it depends, and further recites “wherein the physical state of the hardware devices comprises temperature, humidity, power supply voltage, fan speeds, remote access, and operating system functions of the underlying hardware (analyzed under Prong II Step 2A & 2B as additional elements).” These additional elements do not integrate the abstract idea/mental process into a practical application and are not significantly more than the judicial exception. Therefore, claim 17 fails to correct the deficiencies of claim 16 and is rejected for similar reasoning as claim 16, above.
Claim 18 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim recites the same claimed language as claim 1 above other than being a method claim rather than a system claim. Claim 18 is rejected under 35 U.S.C. 101 for the same reasons as claim 1 above.
Claim 19 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim recites the same claimed language as claim 3 above other than being a method claim rather than a system claim. Claim 19 is rejected under 35 U.S.C. 101 for the same reasons as claim 3 above.
Claim 20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim recites the same claimed language as claim 4 above other than being a method claim rather than a system claim. Claim 20 is rejected under 35 U.S.C. 101 for the same reasons as claim 4 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1-2, 4-11, 13-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Phatak et al. (U.S. Patent No. 11,314,907) – hereinafter “Phatak” in view of Xia et al. (U.S. Patent No. 10,796,035) – hereinafter “Xia”.
Regarding independent claim 1, Phatak discloses:
A system for hardware simulation framework, comprising:
one or more computing devices configured to: (Fig. 1, Sim 148(1) – 148(M) and Fig. 2, Simulation Computing Device 252(1) with Sim Controller 248(1) and Simulator(s) 254(1)) and Abstract “… one or more computing devices on a network …”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the computing devices are configured to be execute simulations.
determine a plurality of hardware devices for testing using simulation; (Col. 4, Lines 47-53 “The simulation platform allows design optimization of vehicle systems by allowing virtual experimentation, testing, and comparison of different E/E architectures with respect to multiple virtual ECUs (vECUs) and other simulated components or systems. The simulation platform herein further enables testing and comparing the performance of microcontrollers and hardware components.” and Col. 8, Lines 24-31 “In some examples, the user 136 may use the GUI presented by the browser 138 to configure a desired simulation, which may include a plurality of simulators 148 such as processors simulators (vECUs), plant simulators, and/or other types of simulators. Each simulator may be configured to emulate a real-world component, such as for generating or receiving one or more signals that would be generated or received, respectively, by the real-world component.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the user can select the simulation of a plurality of simulators such that they simulate real-world components.
simulate each of the plurality of hardware devices based on the selected level of fidelity. (Fig. 11, GUI 1100 and Execute Simulation 1108 and Col. 16, Line 63 – Col. 17, Line 4 “For example, the user may confirm that the configured simulation is a mechanical system simulation of mixed fidelity, as indicated at 1102, that there are two simulators configured, as indicated at 1104, and that simulation is set for a specified end time and step size, as indicated at 1106. When the user has confirmed that the simulation is properly configured, the user may select an “execute simulation” virtual control 1108.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the user can confirm simulation of the simulator components with the GUI with selection of the level of fidelity.
Phatak does not explicitly disclose:
enable a user to select a level of fidelity of the simulation for each of the plurality of hardware devices;
However, Xia discloses:
enable a user to select a level of fidelity of the simulation for each of the plurality of hardware devices; (Col. 3, Lines 38-60 “The simulation and test environment 10 further comprises a simulated infrastructure development, deployment, and testing system 130. The system 130 comprises application programming interfaces that are configured to enable a user to design, deploy, and test the simulated computing system 100. In one embodiment, the application programming interfaces comprises web-based interfaces. For example, as shown in FIG. 1, the system 130 comprises a node simulation API 132, and a test control API 134. The node simulation API 132 implements user interfaces and methods that are configured to (i) define/build simulated hardware elements including, but not limited to, servers, storage elements, network devices, and power control elements, (ii) utilize the simulated hardware elements to build different types of customized simulated nodes (e.g., virtual compute nodes 122, virtual storage nodes 124, virtual switch nodes 126, virtual power nodes 128), (iii) utilize the simulated nodes to build simulated scalable, heterogeneous hardware infrastructures and associated simulated network topologies; and (iv) enable on-demand deployment of a simulated hardware infrastructure on top of one or more actual servers (e.g., processing platform 110) to implement a simulated computing system.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the user can select a level of fidelity for the simulation of their component based upon the building of simulated hardware elements such that the user specifically defines the level of fidelity with the building of the component in comparison to real-world components.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add enable a user to select a level of fidelity of the simulation for each of the plurality of hardware devices as seen in Xia's invention into Phatak's invention because these modifications allow the use of a known technique to improve similar devices in the same way such that the simulated hardware devices based upon real-world devices can be scaled in terms of fidelity to test different devices.
Regarding claim 2, Phatak discloses the system of claim 1, wherein the system further comprises a plurality of virtual machines and a virtual machine orchestrator. (Fig. 1, Virtual Machine 110(1) to 110(N) and Simulation Manager (126) and Management Computing Device (132) and Col. 7, Lines 43-54 “Further, a simulation manager 126 may manage the execution of simulations on the simulation platform. For example, the simulation manager 126 may ensure that the user has sufficient licenses for executing a specific simulation. Further, the simulation manager 126 may control timing of the execution of simulations. As one example, if a user is executing a first simulation and also submits for execution a second simulation, the simulation manager 126 may check whether the user has sufficient licenses available, and if not, may delay execution of the second simulation until a sufficient number of licenses are freed up following completion of execution of the first simulation.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the system is comprised of virtual machines and the combination of the simulation manager and management computing device help to manage simulation.
Regarding claim 4, Phatak discloses the system of claim 1, wherein the fidelity levels are changed using a graphical user interface or text files. (Col. 14, Lines 16-22 “In addition, each simulation type 502 may indicate an associated fidelity of the simulation type. For example, the fidelity of a simulation may indicate the degree to which a model or simulation reproduces the state and behavior of a real world component, system, or process. Accordingly, fidelity may be considered an indication of the realism of a particular model or simulation.” and Col. 15, Lines 24-28 “In addition, the GUI 600 may include a summary area 620 showing all the simulators that have been selected for a particular simulation, and may further include a back button 622 in case the user desires to go back to a previous interface, such as for changing a prior selection.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the fidelity level for a simulation can be adjusted using the GUI for simulator selection.
Regarding claim 5, Phatak discloses the system of claim 1, further comprising an entity-relationship model, wherein the entity-relationship model describes configurations of the plurality of hardware devices. (Col. 10, Lines 32-41 “FIG. 2 illustrates a block diagram 200 showing components and operations for performing a simulation according to some implementations. FIG. 2 includes a description of thirteen example operations 201-213 that may be included for executing a simulation job and providing results to the user 136. For example, the simulation job may be executed using the simulation platform 108 in the system 100 discussed above with respect to FIG. 1. Further, some or all of the operations may be implemented in hardware, software or a combination thereof.” and Col. 28, Lines 30-35 “In addition, the client computing devices 122, the management computing devices 132, and/or the computing devices 1702 and 1704 may include hardware configurations similar to those described above, but may include different functional components, software, and so forth.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the group of components includes hardware configurations to perform simulations.
Regarding claim 6, Phatak discloses the system of claim 5, further comprising a simulation builder, wherein the simulation builder automatically simulates each of the plurality of hardware devices based on the entity-relationship model. (Col. 31, Lines 2-12 “In addition, the simulation controller 248 may obtain one or more model files from a storage location for execution by each respective simulator 254 controlled by that simulation controller 248. For example, the simulation controller 248(1)-248(K) may request the model files identified in the simulation job information from a specified storage location. Through the worker processes 2202, the simulation controller 248 may launch, monitor, terminate, and clean up the workspaces of all simulators 254 executing on the respective simulation computing device 252 during a co-simulation.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the simulation controller obtains model files for execution of each simulator and automatically handles the simulation through launching, monitoring, terminating, and cleaning up simulation workspaces.
Regarding claim 7, Phatak discloses the system of claim 5, wherein the simulated each of the plurality of hardware devices are integrated into a distributed production software stack and network. (Fig. 1, Network Computing Resources 102 and Client Computing Device(s) 122 and Management Computing Device(s) 132 and Col. 25, Lines 20-28 “The first computing device 1702 and the second computing device 1704 may be configured to communicate through a connection 1706, which may be a direct connection, a LAN, or any of the one or more networks 124 described above. As one example, the connection 1706 may be an Ethernet connection, and the co-simulation bus 1418 may communicate over the connection 1706 with the virtual CAN bus 1412 and the co-simulation buses 1416 and 1420.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the plurality of hardware devices are distributed across multiple physical machines and a network.
Regarding claim 8, Phatak discloses the system of claim 1, wherein each of the simulated hardware devices mimic functions of each of the hardware devices. (Col. 4, Lines 47-53 “The simulation platform allows design optimization of vehicle systems by allowing virtual experimentation, testing, and comparison of different E/E architectures with respect to multiple virtual ECUs (vECUs) and other simulated components or systems. The simulation platform herein further enables testing and comparing the performance of microcontrollers and hardware components.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the vECUs/simulated components mimic functions of real ECUs/real components.
Regarding claim 9, Phatak discloses the system of claim 1, wherein each of the simulated hardware devices are either partially simulated or fully simulated. (Col. 4, Lines 47-53 “The simulation platform allows design optimization of vehicle systems by allowing virtual experimentation, testing, and comparison of different E/E architectures with respect to multiple virtual ECUs (vECUs) and other simulated components or systems. The simulation platform herein further enables testing and comparing the performance of microcontrollers and hardware components.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the vECUs/simulated components mimic functions of real ECUs/real components to simulate hardware devices.
Regarding claim 10, Phatak discloses the system of claim 1, but does not explicitly disclose:
wherein the simulated hardware devices are connected to a hypervisor via an application programming interface (API) layer.
However, Xia discloses:
wherein the simulated hardware devices are connected to a hypervisor via an application programming interface (API) layer. (Col. 7, Lines 36-39 “In one embodiment of the invention, the virtual host 310 is implemented using a hosted virtual machine monitor system, such as the open source hosted hypervisor system QEMU (Quick Emulator).” and Col. 8, Lines 61-67 “The virtual BMC server 320 receives and processes various types of commands and data from the test control API 134 for purposes of, e.g., controlling/testing/validating the operation of virtual compute node 300 and for introducing simulated errors into the simulated computing system in which the virtual compute node 300 resides.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the virtual host implemented using a hypervisor system communicates with the virtual BMC server and simulated hardware elements via test control API.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add wherein the simulated hardware devices are connected to a hypervisor via an application programming interface (API) layer as seen in Xia’s invention into Phatak's invention because these modifications allow combining prior art elements according to known methods to yield predictable results such that the hypervisor communicates and monitors execution status of simulated hardware devices.
Regarding claim 11, Phatak discloses the system of claim 2, wherein each of the virtual machines is either a persistent virtual machine or a transitory virtual machine. (Col. 9, Lines 65-67 “Based on the desired simulation additional virtual machines 110 may be allocated to the simulation platform 108 or deallocated back to the resource pool 112.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the deallocation of virtual machines resulting in their resources being given back to the resource pool for allocation to a different purpose means the virtual resources are transitory in nature.
Regarding claim 13, Phatak discloses the system of claim 2, but does not explicitly disclose:
wherein the virtual machine orchestrator communicates with one or more simulated hardware devices using smart network interface cards in the network, wherein the smart network interface cards can be simulated based on a user selection.
However, Xia discloses:
wherein the virtual machine orchestrator communicates with one or more simulated hardware devices using smart network interface cards in the network, wherein the smart network interface cards can be simulated based on a user selection. (Col. 7, Lines 18-35 “FIG. 3 schematically illustrates a virtual compute node 300 according to an embodiment of the invention. The virtual compute node 300 comprises a virtual host 310, product code 312, a product operating system 314, simulated hardware elements 316, a virtual BMC (baseboard management controller) server 320, a control port 330-1 and a data port 330-2. The virtual compute node 300 is configured to simulate a physical compute node (e.g., server node), which typically includes a BMC server, one or more processors (e.g., CPUs), system memory (e.g., DRAM), storage devices (e.g., HDD), and network adaptors (e.g., NIC, HBA). The control port 330-1 comprises a simulated network interface element that is configured to connect the virtual compute node 300 to a simulated out-of-band control network, for example. The data port 330-2 comprises a simulated network interface element that is configured to connect the virtual compute node 300 to a simulated in-band data network, for example.” and Col. 7, Lines 59-67 “The virtual host 310 provides the operating system 314 with a simulated hardware operating platform comprising the simulated hardware elements 316, and manages the execution of the operating system 314 via the simulated hardware elements 316. The simulated hardware elements 316 include, for example, simulated processors (e.g., CPUs), simulated data memory elements (e.g., DRAM, DIMM), simulated storage elements (e.g., flash NAND storage, SSD, HDD, etc.), and simulated network interfaces (e.g., NIC, HBA).”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the virtual host contains simulated hardware elements and can communicate via NIC to other compute nodes also containing simulated hardware elements.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add wherein the virtual machine orchestrator communicates with one or more simulated hardware devices using smart network interface cards in the network, wherein the smart network interface cards can be simulated based on a user selection as seen in Xia’s invention into Phatak's invention because these modifications allow the simple substitution of one known element for another to obtain predictable results such that another component like a smart NIC can be simulated to monitor network statistics.
Regarding claim 14, Phatak discloses the system of claim 2, wherein the virtual machine orchestrator provides a configurable level of abstraction, for the simulation. (Fig. 1, Virtual Machine 110(1) to 110(N) and Simulation Manager (126) and Management Computing Device (132) and Col. 7, Lines 43-54 “Further, a simulation manager 126 may manage the execution of simulations on the simulation platform. For example, the simulation manager 126 may ensure that the user has sufficient licenses for executing a specific simulation. Further, the simulation manager 126 may control timing of the execution of simulations. As one example, if a user is executing a first simulation and also submits for execution a second simulation, the simulation manager 126 may check whether the user has sufficient licenses available, and if not, may delay execution of the second simulation until a sufficient number of licenses are freed up following completion of execution of the first simulation.” and Col. 14, Lines 16-20 “In addition, each simulation type 502 may indicate an associated fidelity of the simulation type. For example, the fidelity of a simulation may indicate the degree to which a model or simulation reproduces the state and behavior of a real world component, system, or process.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the simulation manager and management computing device ensure that each simulation type indicates a fidelity level such that the simulation’s level of abstraction is configurable.
Regarding claim 15, Phatak discloses the system of claim 2, but does not explicitly disclose:
wherein the virtual machine orchestrator is further configured to inject deterministic errors of the hardware devices into the simulated hardware devices for testing errors.
However, Xia discloses:
wherein the virtual machine orchestrator is further configured to inject deterministic errors of the hardware devices into the simulated hardware devices for testing errors. (Col. 4, Lines 47-63 “In this regard, in one embodiment of the invention, a management and orchestration platform can be deployed to execute on top of the simulated computing system, wherein the test control API 134 allows a user to test a functionality of the management and orchestration platform by, e.g., injecting error into the simulated computing system, and determining how the management and orchestration platform reacts in response to the injected error. For example, the test control API 134 can be utilized to manipulate/change a behavior of one or more of the simulated elements, or simulate a failure of one or more of the simulated elements of the simulated computing system. In particular, the test control API 134 can be utilized to modify system behavior by manipulating FW (firmware) behavior of one or more simulated hardware elements or simulated nodes, or simulating a hardware failure of one or more simulated hardware elements.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the orchestration platform allows a user to inject errors into the simulated computing system to simulate hardware failures for the simulated hardware elements.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add wherein the virtual machine orchestrator is further configured to inject deterministic errors of the hardware devices into the simulated hardware devices for testing errors as seen in Xia’s invention into Phatak's invention because these modifications allow applying a known technique to a known device ready for improvement to yield predictable results such that a user can quickly and/or continuously test error handling scenarios in an easier way than replicating these errors on real hardware devices.
Regarding claim 16, Phatak discloses the system of claim 2, but does not explicitly disclose:
wherein the virtual machine orchestrator is further configured to simulate a baseboard management controller to manage a physical state of the hardware devices.
However, Xia discloses:
wherein the virtual machine orchestrator is further configured to simulate a baseboard management controller to manage a physical state of the hardware devices. (Col. 8, Lines 32-41 “The virtual BMC server 320 is configured to emulate the functionalities of an actual BMC server. In one embodiment, the virtual BMC server 320 is configured to work in conjunction with the test control API 134 to introduce errors into a simulated computing system for purposes resiliency testing, failure recovery, and/or validation of a given simulated system design or management and orchestration software. A BMC comprises a service processor that is configured to monitor the physical state of a computer, or hardware devices, using a plurality of sensors.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the virtual BMC server emulates the functions of an actual BMC server such that it monitors the physical state of hardware devices using sensors.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add wherein the virtual machine orchestrator is further configured to simulate a baseboard management controller to manage a physical state of the hardware devices as seen in Xia’s invention into Phatak's invention because these modifications allow applying a known technique to a known device ready for improvement to yield predictable results such that monitoring of the physical state of hardware devices is used for testing hardware device scenarios rather than having to continuously replicate these scenarios with real hardware devices.
Regarding claim 17, Phatak discloses the system of claim 16, but does not explicitly disclose:
wherein the physical state of the hardware devices comprises temperature, humidity, power supply voltage, fan speeds, remote access, and operating system functions of the underlying hardware.
However, Xia discloses:
wherein the physical state of the hardware devices comprises temperature, humidity, power supply voltage, fan speeds, remote access, and operating system functions of the underlying hardware. (Col. 8, Lines 32-46 “The virtual BMC server 320 is configured to emulate the functionalities of an actual BMC server. In one embodiment, the virtual BMC server 320 is configured to work in conjunction with the test control API 134 to introduce errors into a simulated computing system for purposes resiliency testing, failure recovery, and/or validation of a given simulated system design or management and orchestration software. A BMC comprises a service processor that is configured to monitor the physical state of a computer, or hardware devices, using a plurality of sensors. The sensors monitor and measure various variables/parameters/statistics such as physical variables (e.g., temperature, power-supply voltage, cooling fan speeds), processor status, power supply status, network communications parameters, and operating system functions.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the virtual BMC server monitors the temperature, power-supply voltage, fan speeds, network communications parameters, and operating system functions.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add wherein the physical state of the hardware devices comprises temperature, humidity, power supply voltage, fan speeds, remote access, and operating system functions of the underlying hardware as seen in Xia’s invention into Phatak's invention because these modifications allow combining prior art elements according to known methods to yield predictable results such that monitoring of hardware devices through physical state is done to see if a level of fidelity simulates hardware devices properly for the user.
Regarding claim 18, it is a method claim having the same limitations as cited in system claim 1. Thus, claim 18 is also rejected under the same rationale as addressed in the rejection of claim 1 above.
Regarding claim 20, it is a method claim having the same limitations as cited in system claim 4. Thus, claim 20 is also rejected under the same rationale as addressed in the rejection of claim 4 above.
8. Claims 3 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Phatak et al. (U.S. Patent No. 11,314,907) – hereinafter “Phatak”, in view of Xia et al. (U.S. Patent No. 10,796,035) – hereinafter “Xia”, further in view of Hyodo (U.S. Patent No. 5,787,269).
Regarding claim 3, Phatak discloses the system of claim 1, wherein the level of fidelity of the simulation for each of the plurality of hardware devices is determined based on [user selection] of the simulation of each hardware device. (Col. 14, Lines 16-27 “In addition, each simulation type 502 may indicate an associated fidelity of the simulation type. For example, the fidelity of a simulation may indicate the degree to which a model or simulation reproduces the state and behavior of a real world component, system, or process. Accordingly, fidelity may be considered an indication of the realism of a particular model or simulation. For instance, suppose that the user clicks on or otherwise selects mechanical system simulation 510. As indicated at 516, the GUI 500 may present information about the fidelity of the selected mechanical system simulation 510, which shows that the fidelity is mixed in this example.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the level of fidelity of the simulation is determined based on a user selection in a GUI.
Phatak does not explicitly disclose:
wherein the level of fidelity of the simulation for each of the plurality of hardware devices is determined based on desired processing speed and accuracy of the simulation of each hardware device.
However, Hyodo discloses:
wherein the level of fidelity of the simulation … is determined based on desired processing speed and accuracy of the simulation … (Col. 2, Lines 44-54 “The model selecting means may comprise: first selecting means for selecting a first simulation model for each process from among the various simulation models, the first simulation model being a most accurate simulation model; second means for selecting a second simulation model from among the various simulation models, a processing time of the second simulation model being shorter than a processing time of the first simulation model;” and Col. 6, Lines 55-59 “The second selecting means 32 of the model selecting means 3 determines, in S22, whether or not there is a simulation model having a shorter processing time than that of the most accurate simulation from among simulation models registered in the condition information A.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the level of fidelity of the simulation is determined based on a desired processing time/speed of the simulation model and an accuracy level of the simulation.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add wherein the level of fidelity of the simulation … is determined based on desired processing speed and accuracy of the simulation as seen in Hyodo's invention into Phatak's invention because these modifications allow the use of a known technique to improve similar devices in the same way such that the level of simulation is selected based on speed and accuracy so that if a user wants to simulate background tasks it is not required to select a high processing speed if it is unrealistic to the real-world scenario.
Regarding claim 19, it is a method claim having the same limitations as cited in system claim 3. Thus, claim 19 is also rejected under the same rationale as addressed in the rejection of claim 3 above.
9. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Phatak et al. (U.S. Patent No. 11,314,907) – hereinafter “Phatak”, in view of Xia et al. (U.S. Patent No. 10,796,035) – hereinafter “Xia”, further in view of Iuniana Oprescu et al. (NPL “dVirt: A virtualized infrastructure for experimenting BGP routing”) – hereinafter “Iuniana Oprescu”.
Regarding claim 12, Phatak discloses the system of claim 2, but does not explicitly disclose:
wherein the virtual machine orchestrator utilizes a remote procedure call (RPC) to enable interaction between the plurality of virtual machines using different languages in different manners.
However, Iuniana Oprescu discloses:
wherein the virtual machine orchestrator utilizes a remote procedure call (RPC) to enable interaction between the plurality of virtual machines using different languages in different manners. (Page 152, Fig. 1 “An overview of the dVirt components: the user interacts through the RPC with the remote hypervisors and the corresponding virtual machines.” and Fig. 2 “The user launches a request that can be executed either by the hypervisor or the virtual machines. Note that for the calls on VMs, an embedded request is forwarded by the hypervisor to the corresponding VM.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the user interacts through the RPC with hypervisors/VM orchestrators and VMs such that communication across VMs is forwarded by the hypervisor.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add wherein the virtual machine orchestrator utilizes a remote procedure call (RPC) to enable interaction between the plurality of virtual machines using different languages in different manners as seen in Iuniana Oprescu’s invention into Phatak's invention because these modifications allow the simple substitution of one known element for another to obtain predictable results that ensure communication between VMs without unexpected errors.
Conclusion
10. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Prior art including Luecke et al. (U.S. Pub. No. 2021/0182180), Ramalingam et al. (U.S. Pub. No. 2021/0144232), and Maity et al. (U.S. Pub. No. 2018/0046486) contain information regarding simulation of hardware components. These simulations are done in different ways but all comprise the idea of simulating hardware components with the use of virtualization.
Examiner has cited particular columns/paragraphs/sections and line numbers in the references applied and not relied upon to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
When responding to the Office action, applicant is advised to clearly point out the patentable novelty the claims present in view of the state of the art disclosed by the reference(s) cited or the objections made. A showing of how the amendments avoid such references or objections must also be present. See 37 C.F.R. 1.111(c).
When responding to this Office action, applicant is advised to provide the line and page numbers in the application and/or reference(s) cited to assist in locating the appropriate paragraphs.
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/D.T./Examiner, Art Unit 2198
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2198
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