DETAILED ACTION
This office action is responsive to amendment filed on January 28, 2026 in this application Sangeneni, U.S. Patent Application No. 18/132,327 (Filed April 7, 2023). Claims 1 – 20 were pending. Claims 1, 3, 5, 7, 9, 10, and 13 – 20 are amended. Claim 2 is cancelled. Claims 1 and 3 – 20 are pending.
Applicants' arguments have been carefully and respectfully considered and found not persuasive. Accordingly, this action has been made FINAL.
Response to Arguments
1. With respect to Applicant’s argument on pgs. 8 – 9 of the Applicant’s Remarks (“Remarks”) stating that the claim amendments overcome the 101 rejections by including steps “inherently tied to computer operation,” such as compilation, which cannot practically be done in the human mind, examiner respectfully agrees and the rejections made under 35 USC §101 are withdrawn.
2. With respect to Applicant’s argument on pg. 9 of the Remarks stating that “network interface” in claim 18 is “a well understood term in the art” and is not a generic placeholder, examiner respectfully neither agrees nor disagrees. See infra § 35 USC 112(f).
No argument has been provided as to how “network interface” being allegedly “well understood” would lead to a determination that it recites sufficient structure to perform the claimed function and is not a generic placeholder for structure. The specification fails to provide an explicit description of the claimed “network interface” but paragraph 0042 and fig. 3 appears to provide disclosure of structure in the form of both a network on a chip 330 which is part of a system-on-chip 302 as well as “ethernet and PCIe” network connections which supplies definite hardware support for the claimed “network interface” placeholder. To the extent applicant wishes to overcome the interpretation made under 35 USC 112(f) they may amend the claim to recite sufficient structure to perform the claimed function as supported in the specification.
Therefore claim 18 remains interpreted under 35 USC 112(f).
3. With respect to Applicant’s argument on pgs. 10 - 13 of the Remarks stating that the current prior art fails to teach the newly added limitations of “accessing a listing of the hardware processors in the chipset” and “mapping[] each functional module to a corresponding hardware processor for execution”, examiner respectfully disagrees as to the first limitation but agrees in part to the second. See infra § Claim Rejections - 35 USC §103 § Claim 1.
However, in the interests of compact prosecution newly added prior art reference Ciolfi is used which teach the newly added limitations by disclosing the user to graphically building a program by connecting and assigning functional blocks to specific different hardware processors of a deployment system to specify the deployment of the program. Ciolfi at Abstract; id. at ¶¶ 0036, 0093, 0040 (target system environment contains a chipset consisting of a plurality of different hardware processors to which functions may be mapped); id. at ¶¶ 0050 & 0052 – 0054 (assign blocks to specific different hardware processors of the target system); id. at fig. 3B; id. at ¶¶ 0067 & 0069 (deployment of program to real-time system as executable code); id. at ¶¶ 0043 & 0084 (operating system scheduling execution on system running the executable code).
Therefore, the prior art teaches a management end server that provides the claimed instructions.
Information Disclosure Statement
The information disclosure statement (IDS) filed on January 28, 2026 is in compliance with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609. The references listed therein have been considered, and placed in the application file.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
1. Claims 1 and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 7 - 9 of co-assigned U.S. Patent No. 12,399,688. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the Patents anticipate the claims of the instant Application.
Dependent claims 3 – 16 and 18 - 20 are rejected on the ground of obviousness-type double patenting as being unpatentable over claims 1 and 7 - 9 of U.S. Patent No. 12,399,688. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are obvious in view of the Patent and the art used in the dependent claims and associated motivation (see infra).
2. Claims 1 and 17 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 5 of co-assigned U.S. Patent Application No. 19,287,286. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the Patents anticipate the claims of the instant Application.
Dependent claims 3 – 16 and 18 - 20 are provisionally rejected on the ground of obviousness-type double patenting as being unpatentable over claims 1 and 5 of U.S. Patent Application No. 19,287,286. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are obvious in view of the Patent and the art used in the dependent claims and associated motivation (see infra).
This is a provisional obviousness double patenting rejection because the conflicting claims have not in fact been patented.
35 USC § 112(f)
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “interface configured to”, in claims 18.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections 35 U.S.C. §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nandakumar et al., United States Patent Application Publication No. 2022/0138004 (Published May 5, 2022, filed July 27, 2021) (“Nandakumar”) in view of Seif et al., United States Patent Application Publication No. 2019/0384577 (Published December 19, 2019, filed June 15, 2018) (“Seif”), and Yang et al., United States Patent Application Publication No. 2019/0324759 (Published October 24, 2019, filed April 7, 2017) (“Yang”), and Ciolfi, United States Patent Application Publication No. 2007/0294074 (Published December 20, 2007, filed August 20, 2007) (“Ciolfi”).
Claim 1
With respect to claim 1, Nandakumar teaches the invention as claimed including a method implemented by a computer system for generating graphics representing a pipeline of a machine learning pipeline to be executed on a [chipset] comprising a plurality of [hardware processors], the method comprising:
displaying a graphical user interface (GUI) comprising a canvas area; receiving user indications for graphically specifying a processing pipeline of functional modules in the canvas area; … displaying graphics representing the pipeline of functional modules in the canvas area, {Using a graphical IDE to graphically select function modules from a library, drag-and-drop the function module blocks on a canvas, and interconnect the blocks to specify the processing pipeline of an application including using the graphical user interface to specify computing infrastructure and computing resources for each block by “selecting an infrastructure template from a Provision UI…for provisioning the infrastructure.” Nandakumar at ¶¶ 0021, 0022, 0063, 0069, 0100, 0120 id. at fig. 2; id. at ¶ 0098 (blocks may be selected from a library of available blocks); id. at ¶¶ 0016 & 0101 (resource provisioning).}
However, Nandakumar doesn’t explicitly teach the limitation:
[hardware] processors…accessing a listing of the [hardware] processor in the [chipset] …retrieving a plurality of software blocks from a library of software blocks, the software blocks implementing the functional modules of the pipeline on the corresponding [hardware] processors; {Seif does teach this limitation. Seif teaches that the method for using a graphical IDE to specify processing resources for various blocks comprising an application, as taught in Nandakumar, may include using a graph editor GUI for visual programming of a machine learning application composed by the user selecting, from a provided list, module nodes of a node library of available nodes, graphically connecting the input and output ports of the nodes to specify processing flow, and including the user specifying respective different processors to perform processing of module nodes, such as processors, digital signal processors, and image processors. Seif at Abstract, ¶¶ 0030, 0031, 0035, 0045, 0052, 0053; id. at fig. 2.
Nandakumar and Seif are analogous art because they are from the “same field of endeavor” and are both from the same “problem-solving area.” Specifically, they are both from the field of software development, and both are trying to solve the problem of how to select components of an application under development.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine specifying processing resources for various blocks comprising an application, as taught in Nandakumar, with specifying the processors to use, as taught in Seif. Seif teaches there may be various types of processors available. Seif at ¶ 0052. Therefore, one having ordinary skill in the art would have been motivated to combine specifying processing resources for various blocks comprising an application, as taught in Nandakumar, with specifying the processors to use, as taught in Seif, for the purpose of using a known method to specify processing resource types in a GUI with a method that requires the specification of processing resources in a GUI.}
However, Nandakumar and Seif doesn’t explicitly teach the limitation:
chipset … in the chipset {Yang does teach this limitation. Yang teaches that the method for using a graphical IDE to specify types of processors for various blocks comprising an application, as taught in Nandakumar and Seif, may include specifying particular chipset cores to use for particular machine learning blocks selected from a library and assembled to define a machine learning application. Yang at Abstract, ¶¶ 0004, 0143, 0144, 0204 - 0206.
Nandakumar, Seif, and Yang are analogous art because they are from the “same field of endeavor” and are both from the same “problem-solving area.” Specifically, they are both from the field of software development, and both are trying to solve the problem of how to select components of an application under development.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine specifying processor for application blocks, as taught in Nandakumar and Seif, with specifying processor cores to use, as taught in Yang. Seif teaches there may be various types of processors available and Yang teaches that using multiple cores makes a neural network workload process faster. Seif at ¶ 0052; Yang at ¶ 0006. Therefore, one having ordinary skill in the art would have been motivated to combine specifying processor for application blocks, as taught in Nandakumar and Seif, with specifying processor cores to use, as taught in Yang, for the purpose of using a known graphical method to specify processors with a method that allows specify processor cores when a multi-core processor is available.}
However, Nandakumar, Seif, and Yang doesn’t explicitly teach the limitation:
the graphics showing a mapping of each functional module to a corresponding hardware processor in the [chipset] for execution;…generating a plurality of executable components of the software blocks for execution on the hardware processors to which the functional modules are mapped, the executable components including at least one software block compiled for execution on the corresponding hardware processor; generating a descriptive file describing the executable components to be executed by the corresponding hardware processors and connections between the executable components to form the processing pipeline, wherein the descriptive file is executable by a scheduler installed on a device containing the chipset; and generating an implementation package containing the plurality of executable components and the descriptive file. {Ciolfi does teach this limitation. Ciolfi teaches that the method for using a graphical IDE to specify types of processors for various blocks comprising an application, as taught in Nandakumar, Seif, and Yang, includes where the GUI canvas presented to the user allows the user to graphically build a program by connecting and assigning functional blocks to specific different processors of a deployment system to specify the deployment of the program. Ciolfi at Abstract; id. at ¶¶ 0036, 0093, 0040 (target system environment contains a chipset consisting of a plurality of different hardware processors to which functions may be mapped); id. at ¶¶ 0050 & 0052 – 0054 (assign blocks to specific different processors of the target system); id. at fig. 3B; id. at ¶¶ 0067 & 0069 (deployment of program to real-time system as executable code); id. at ¶¶ 0043 & 0084 (operating system scheduling execution on system running the executable code).
Nandakumar, Seif, Yang, and Ciolfi are analogous art because they are from the “same field of endeavor” and are both from the same “problem-solving area.” Specifically, they are both from the field of software development, and both are trying to solve the problem of how to select components of an application under development.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine specifying processors for application blocks, as taught in Nandakumar, Seif, and Yang, with specifying particular hardware processors for particular application blocks for deployment, as taught in Ciolfi. Seif teaches there may be various types of processors available and Yang teaches that using multiple cores makes a neural network workload process faster. Seif at ¶ 0052; Yang at ¶ 0006. Therefore, one having ordinary skill in the art would have been motivated to combine specifying processors for application blocks, as taught in Nandakumar, Seif, and Yang, with specifying particular hardware processors for particular application blocks for deployment, as taught in Ciolfi, for the purpose of using a known graphical method to specify node execution on processors with a method that requires using a graphical method to specify which nodes should be executed on which processors.}
Claim 3
With respect to claim 3, Nandakumar, Seif, Yang, and Ciolfi, teach the invention as claimed including:
connecting via a network to the device containing the chipset; deploying the implementation package onto the device, causing the device to execute the executable components; responsive to executing the executable components by the device, {Users may specify particular chipset cores to use for particular machine learning blocks selected from a library, assemble them to define a machine learning application, and the application may be deployed, scheduled for, and executed according to the specification. Yang at Abstract, ¶¶ 0004, 0143, 0144, 0204 – 0206; id. at ¶¶ 0053, 0054, 0067 (scheduling).}
receiving from the device an output via the network; and displaying the output on the GUI. {Output of the application execution may be viewed in the GUI. Seif at ¶ 0032.}
Claim 4
With respect to claim 4, Nandakumar, Seif, Yang, and Ciolfi, teach the invention as claimed including:
simulating the device containing the [chipset]; deploying the implementation package onto the simulated device, causing the simulated device to execute the executable components; responsive to executing the executable components by the simulated device, receiving from the simulated device an output via the network; {Using a graphical IDE to graphically select function modules from a library, drag-and-drop the function module blocks on a canvas, and interconnect the blocks to specify the processing pipeline of an application including using the graphical user interface to specify computing infrastructure and computing resources for each block by “selecting an infrastructure template from a Provision UI…for provisioning the infrastructure,” the specified pipeline may be scheduled, deployed, and executed. Nandakumar at ¶¶ 0021, 0022, 0063, 0069, 0120 id. at fig. 2; id. at ¶ 0098 (blocks may be selected from a library of available blocks); id. at ¶¶ 0016 & 0101 (resource provisioning); id. at ¶¶ 0063, 0100, 0101, 0110, 0112 (scheduling and execution); id. at ¶ 0121 (virtual machine may be used as a simulator).}
chipset {Users may specify particular chipset cores to use for particular machine learning blocks selected from a library, assemble them to define a machine learning application, and the application may be deployed, scheduled for, and executed according to the specification. Yang at Abstract, ¶¶ 0004, 0143, 0144, 0204 – 0206; id. at ¶¶ 0053, 0054, 0067 (scheduling).}
and displaying the output on the GUI. {Output of the application execution may be viewed in the GUI. Seif at ¶ 0032.}
Claim 5
With respect to claim 5, Nandakumar, Seif, Yang, and Ciolfi, teach the invention as claimed including:
wherein receiving user indications for graphically specifying the pipeline of functional modules comprises: displaying a catalog of functional modules in the GUI, each functional module corresponding to a graphic; receiving first user indications dragging functional modules in the catalog into the canvas area; responsive to receiving first user indications, displaying graphics corresponding to the dragged functional modules in the canvas area; receiving second user indications linking the graphics representing the functional modules in the canvas area; and responsive to receiving second user indications, linking the graphics in the canvas area with arrows. {Using a graphical IDE to graphically select function modules from a library, drag-and-drop the function module blocks on a canvas, and interconnect the blocks with arrows to specify the processing pipeline of an application including using the graphical user interface to specify computing infrastructure and computing resources for each block by “selecting an infrastructure template from a Provision UI…for provisioning the infrastructure,” the specified pipeline may be scheduled, deployed, and executed. Nandakumar at ¶¶ 0021, 0022, 0063, 0069, 0120 id. at fig. 2 (arrows); id. at ¶ 0098 (blocks may be selected from a library of available blocks); id. at ¶¶ 0016 & 0101 (resource provisioning); id. at ¶¶ 0063, 0100, 0101, 0110, 0112 (scheduling and execution); id. at ¶ 0121 (virtual machine may be used as a simulator).}
Claim 6
With respect to claim 6, Nandakumar, Seif, Yang, and Ciolfi, teach the invention as claimed including:
wherein the catalog of functional modules includes a machine learning model, a sensor plugin, and an ethernet device plugin. {Selected functional modules include various types including machine learning models, image processors, and communications. Nandakumar at ¶¶ 0013, 0016 & 0101 (resource provisioning); Seif at ¶¶ 0035 & 0052.}
Claim 7
With respect to claim 7, Nandakumar, Seif, Yang, and Ciolfi, teach the invention as claimed including:
wherein at least one function module comprises a plurality of functional stages, each of which is mapped to an interconnected software block, and the graphic corresponding to the functional module comprises a plurality of subgraphics, each of which corresponds to a functional stage. {Functional stages are displayed including parameters that may be configured within the GUI of the function module. Seif at ¶¶ 0035 - 0037.}
Claim 8
With respect to claim 8, Nandakumar, Seif, Yang, and Ciolfi, teach the invention as claimed including:
displaying a metric for utilization of the chipset by the functional stages. {Functional stages are displayed including parameters that may be configured within the GUI of the function module. Seif at ¶¶ 0035 - 0037.}
Claim 9
With respect to claim 9, Nandakumar, Seif, Yang, and Ciolfi, teach the invention as claimed including:
wherein the metric comprises at least one of (1) frames per second of a hardware processor, (2) a power utilization of a hardware processor, (3) memory utilization of a memory device, and (4) utilization of a hardware processor. {Output may include displaying for each functional block “their respective CPU, GPU, and Memory usage.” as well as “power, processor speed, memory capacity.” Nandakumar at ¶ 0102.}
Claim 10
With respect to claim 10, Nandakumar, Seif, Yang, and Ciolfi, teach the invention as claimed including:
wherein the at least one functional module comprising a plurality of functional stages is a machine learning model. {Functional stages for machine learning models are displayed including parameters that may be configured within the GUI of the function module. Seif at ¶¶ 0035 - 0037.}
Claim 11
With respect to claim 11, Nandakumar, Seif, Yang, and Ciolfi, teach the invention as claimed including:
wherein the plurality of interconnected software blocks of the machine learning model includes a tensor multiplication block that executes tensor multiplication on a machine learning accelerator (MLA) of the chipset. {Machine Learning accelerator such as a graphics multiprocessor can be used to perform tensor convolutions. Yang at ¶¶ 0143 – 0148; see Nandakumar at ¶ 0064.}
Claim 12
With respect to claim 12, Nandakumar, Seif, Yang, and Ciolfi, teach the invention as claimed including:
wherein the GUI further comprises a model training interface configured to receive a user input of (1) a location of training dataset, and (2) a type of model, the method further comprising: training a custom machine learning model based on the user input, and adding the custom machine learning model to the catalog of functional modules. {Custom models may be trained and added. Nandakumar at ¶¶ 0013, 0014, 0021, 0026, 0027, 0076.}
Claim 13
With respect to claim 12, Nandakumar, Seif, Yang, and Ciolfi, teach the invention as claimed including:
wherein generating a plurality of executable components of the software blocks comprises: assigning the executable components to execute on different [hardware] processors in the [chipset,] based on specializations of the [hardware] processors. {A graph editor GUI may be used for visual programming of a machine learning application composed by the user selecting module nodes from a library of available nodes, graphically connecting the input and output ports of the nodes to specify processing flow, and including the user specifying respective different processors to perform processing of module nodes, such as processors, digital signal processors, and image processors. Seif at Abstract, ¶¶ 0030, 0031, 0035, 0045, 0052; id. at fig. 2.
hardware processors {Ciolfi at Abstract; id. at ¶¶ 0036, 0093, 0040 (target system environment contains a chipset consisting of a plurality of different hardware processors to which functions may be mapped); id. at ¶¶ 0050 & 0052 – 0054 (assign blocks to specific different processors of the target system); id. at fig. 3B; id. at ¶¶ 0067 & 0069 (deployment of program to real-time system as executable code).}
chipset {Users may specify particular chipset cores to use for particular machine learning blocks selected from a library, assemble them to define a machine learning application, and the application may be deployed and scheduled for execution according to the specification. Yang at Abstract, ¶¶ 0004, 0143, 0144, 0204 – 0206; id. at ¶¶ 0053, 0054, 0067 (scheduling).}
Claim 14
With respect to claim 14, Nandakumar, Seif, Yang, and Ciolfi, teach the invention as claimed including:
wherein generating a plurality of executable components of the software blocks comprises: setting configuration parameters of the [hardware] processors. {Machine learning models are displayed including parameters that may be configured within the GUI of the function module. Seif at ¶¶ 0035 - 0037.}
hardware processors {Ciolfi at Abstract; id. at ¶¶ 0036, 0093, 0040 (target system environment contains a chipset consisting of a plurality of different hardware processors to which functions may be mapped); id. at ¶¶ 0050 & 0052 – 0054 (assign blocks to specific different processors of the target system); id. at fig. 3B; id. at ¶¶ 0067 & 0069 (deployment of program to real-time system as executable code).}
Claim 15
With respect to claim 15, Nandakumar, Seif, Yang, and Ciolfi, teach the invention as claimed including:
wherein the [hardware] processors in the [chipset ] include an application processing unit (APU), and synthesizing the pipeline of functional modules into interconnected executable components comprises: configuring the APU to control execution of the executable components on the [hardware] processors. {Applications may be processed by an operator node representing a “processor operators for executing any program.” Seif at ¶ 0035.}
in the chipset {Users may specify particular chipset cores to use for particular machine learning blocks selected from a library, assemble them to define a machine learning application, and the application may be deployed and scheduled for execution according to the specification. Yang at Abstract, ¶¶ 0004, 0143, 0144, 0204 – 0206; id. at ¶¶ 0053, 0054, 0067 (scheduling).}
hardware processors {Ciolfi at Abstract; id. at ¶¶ 0036, 0093, 0040 (target system environment contains a chipset consisting of a plurality of different hardware processors to which functions may be mapped); id. at ¶¶ 0050 & 0052 – 0054 (assign blocks to specific different processors of the target system); id. at fig. 3B; id. at ¶¶ 0067 & 0069 (deployment of program to real-time system as executable code).}
Claim 16
With respect to claim 16, Nandakumar, Seif, Yang, and Ciolfi, teach the invention as claimed including:
wherein generating a plurality of executable components of the software blocks comprises: retrieving, from a software library, source code files for software blocks that implement the functional modules; and compiling the source code files to generate the executable components. {Using a graphical IDE to graphically select function modules from a library, drag-and-drop the function module blocks on a canvas, and interconnect the blocks with arrows to specify the processing pipeline of an application including using the graphical user interface to specify computing infrastructure and computing resources for each block by “selecting an infrastructure template from a Provision UI…for provisioning the infrastructure,” the specified pipeline may be scheduled, deployed, and executed. Nandakumar at ¶¶ 0021, 0022, 0063, 0069, 0120 id. at fig. 2 (arrows); id. at ¶ 0098 (blocks may be selected from a library of available blocks); id. at ¶¶ 0016 & 0101 (resource provisioning); id. at ¶¶ 0063, 0100, 0101, 0110, 0112 (scheduling and execution); id. at ¶ 0121 (virtual machine may be used as a simulator); id. at ¶¶ 0096 & 0098 (executable blocks are formed from source code); see Yang at ¶¶ 0054 & 0078 (compiler).}
Claim 17
With respect to claim 17, Nandakumar teaches the invention as claimed including a device having a [chipset comprising a plurality of hardware processors], and a non-transitory computer-readable storage medium, having instructions encoded thereon that, when executed [by the plurality of hardware processors,] cause at least one [hardware processor] to:
receive an implementation package comprising (a) a plurality of executable components …, and (b) a descriptive file…wherein the executable components implement at least one of (1) a machine learning model, or (2) an image processing operation; and schedule and control execution of the executable components on the [hardware processors] according to the descriptive file. {Using an graphical IDE to graphically select function modules from a library, drag-and-drop the function module blocks on a canvas, interconnect the blocks to specify the processing pipeline of an application including using the graphical user interface to specify computing infrastructure and computing resources for each block by “selecting an infrastructure template from a Provision UI…for provisioning the infrastructure,” and outputting the constructed machine learning application for execution Nandakumar at ¶¶ 0021, 0022, 0063; 0069; 0100, 0120 id. at fig. 2; id. at ¶ 0098 (blocks may be selected from a library of available blocks); id. at ¶¶ 0016 & 0101 (resource provisioning).}
However, Nandakumar doesn’t explicitly teach the limitation:
plurality of [hardware] processors {Seif does teach this limitation. Seif teaches that the method for using a graphical IDE to specify processing resources for various blocks comprising an application, as taught in Nandakumar, may include using a graph editor GUI for visual programming of a machine learning application composed by the user selecting module nodes from a library of available nodes, graphically connecting the input and output ports of the nodes to specify processing flow, and including the user specifying respective different processors to perform processing of module nodes, such as processors, digital signal processors, and image processors. Seif at Abstract, ¶¶ 0030, 0031, 0035, 0045, 0052; id. at fig. 2.
Nandakumar and Seif are analogous art because they are from the “same field of endeavor” and are both from the same “problem-solving area.” Specifically, they are both from the field of software development, and both are trying to solve the problem of how to select components of an application under development.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine specifying processing resources for various blocks comprising an application, as taught in Nandakumar, with specifying the processors to use, as taught in Seif. Seif teaches there may be various types of processors available. Seif at ¶ 0052. Therefore, one having ordinary skill in the art would have been motivated to combine specifying processing resources for various blocks comprising an application, as taught in Nandakumar, with specifying the processors to use, as taught in Seif, for the purpose of using a known method to specify processing resource types in a GUI with a method that requires the specification of processing resources in a GUI.}
However, Nandakumar and Seif doesn’t explicitly teach the limitation:
chipset {Yang does teach this limitation. Yang teaches that the method for using a graphical IDE to specify types of processors for various blocks comprising an application, as taught in Nandakumar and Seif, may include specifying particular chipset cores to use for particular machine learning blocks selected from a library and assemble to define a machine learning application. Yang at Abstract, ¶¶ 0004, 0143, 0144, 0204 - 0206.
Nandakumar, Seif, and Yang are analogous art because they are from the “same field of endeavor” and are both from the same “problem-solving area.” Specifically, they are both from the field of software development, and both are trying to solve the problem of how to select components of an application under development.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine specifying processor for application blocks, as taught in Nandakumar and Seif, with specifying processor cores to use, as taught in Yang. Seif teaches there may be various types of processors available and Yang teaches that using multiple cores makes a neural network workload process faster. Seif at ¶ 0052, Yang at ¶ 0006. Therefore, one having ordinary skill in the art would have been motivated to combine specifying processor for application blocks, as taught in Nandakumar and Seif, with specifying processor cores to use, as taught in Yang, for the purpose of using a known graphical method to specify processors with a method that allows specify processor cores when a multi-core processor is available.}
However, Nandakumar, Seif, and Yang doesn’t explicitly teach the limitation:
that are executable on the hardware processors, including at least one software block compiled for execution on one of the hardware processors…describing a mapping of each executable component to the corresponding hardware processor for execution and connections between the executable components to form a processing pipeline, {Ciolfi does teach this limitation. Ciolfi teaches that the method for using a graphical IDE to specify types of processors for various blocks comprising an application, as taught in Nandakumar, Seif, and Yang, includes where the GUI canvas presented to the user allows the user to graphically build a program by connecting and assigning functional blocks to specific different processors of a deployment system to specify the deployment of the program. Ciolfi at Abstract; id. at ¶¶ 0036, 0093, 0040 (target system environment contains a chipset consisting of a plurality of different hardware processors to which functions may be mapped); id. at ¶¶ 0050 & 0052 – 0054 (assign blocks to specific different processors of the target system); id. at fig. 3B; id. at ¶¶ 0067 & 0069 (deployment of program to real-time system as executable code).
Nandakumar, Seif, Yang, and Ciolfi are analogous art because they are from the “same field of endeavor” and are both from the same “problem-solving area.” Specifically, they are both from the field of software development, and both are trying to solve the problem of how to select components of an application under development.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine specifying processors for application blocks, as taught in Nandakumar, Seif, and Yang, with specifying particular hardware processors for particular application blocks for deployment, as taught in Ciolfi. Seif teaches there may be various types of processors available and Yang teaches that using multiple cores makes a neural network workload process faster. Seif at ¶ 0052; Yang at ¶ 0006. Therefore, one having ordinary skill in the art would have been motivated to combine specifying processors for application blocks, as taught in Nandakumar, Seif, and Yang, with specifying particular hardware processors for particular application blocks for deployment, as taught in Ciolfi, for the purpose of using a known graphical method to specify node execution on processors with a method that requires using a graphical method to specify which nodes should be executed on which processors.}
Claim 18
With respect to claim 18, Nandakumar, Seif, Yang, and Ciolfi, teach the invention as claimed including:
a network interface configured to connect to a server, and to send to the server …executing the executable components. {Users may specify particular chipset cores to use for particular machine learning blocks selected from a library, assemble them to define a machine learning application, and the application may be deployed, scheduled for, and executed according to the specification. Yang at Abstract, ¶¶ 0004, 0143, 0144, 0204 – 0206; id. at ¶¶ 0053, 0054, 0067 (scheduling).}
performance data for the hardware processors {Output of the application execution may be viewed in the GUI. Seif at ¶ 0032.}
Claim 19
With respect to claim 19, Nandakumar, Seif, Yang, and Ciolfi, teach the invention as claimed including:
receive a modified implementation package; and update the schedule and control of execution of the executable components on the [hardware processors] according to the modified implementation package. {Using a graphical IDE to graphically select function modules from a library, drag-and-drop the function module blocks on a canvas, and interconnect the blocks with arrows to specify the processing pipeline of an application including using the graphical user interface to specify computing infrastructure and computing resources for each block by “selecting an infrastructure template from a Provision UI…for provisioning the infrastructure,” the specified pipeline may be scheduled, deployed, executed, and modified. Nandakumar at ¶¶ 0021, 0022, 0063, 0069, 0120 id. at fig. 2 (arrows); id. at ¶ 0098 (blocks may be selected from a library of available blocks); id. at ¶¶ 0016 & 0101 (resource provisioning); id. at ¶¶ 0063, 0100, 0101, 0110, 0112 (scheduling and execution); id. at ¶ 0121 (virtual machine may be used as a simulator); id. at ¶¶ 0096 & 0098 (executable blocks are formed from source code); see Yang at ¶¶ 0054 & 0078 (compiler); id. at ¶ 0111 (pipeline modification).}
hardware processors {Ciolfi at Abstract; id. at ¶¶ 0036, 0093, 0040 (target system environment contains a chipset consisting of a plurality of different hardware processors to which functions may be mapped); id. at ¶¶ 0050 & 0052 – 0054 (assign blocks to specific different processors of the target system); id. at fig. 3B; id. at ¶¶ 0067 & 0069 (deployment of program to real-time system as executable code).}
Claim 20
With respect to claim 20, Nandakumar, Seif, Yang, and Ciolfi, teach the invention as claimed including:
wherein the plurality of [hardware] processors includes an application processing unit (APU), {Applications may be processed by an operator node representing a “processor operators for executing any program.” Seif at ¶ 0035.}
and a machine learning accelerator (MLA). {Machine Learning accelerator such as a graphics multiprocessor can be used to perform tensor convolutions. Yang at ¶¶ 0143 – 0148; see Nandakumar at ¶ 0064.}
hardware processors {Ciolfi at Abstract; id. at ¶¶ 0036, 0093, 0040 (target system environment contains a chipset consisting of a plurality of different hardware processors to which functions may be mapped); id. at ¶¶ 0050 & 0052 – 0054 (assign blocks to specific different processors of the target system); id. at fig. 3B; id. at ¶¶ 0067 & 0069 (deployment of program to real-time system as executable code).}
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THEODORE E HEBERT whose telephone number is (571)270-1409. The examiner can normally be reached on Monday to Friday 9:00 a.m. to 6:00 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lewis Bullock can be reached on 571-272-3759. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
//T.H./ June 12, 2026
Examiner, Art Unit 2199
/LEWIS A BULLOCK JR/Supervisory Patent Examiner, Art Unit 2199
Prosecution Insights