THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY APPARATUS COMPRISING THE SAME

DETAILED ACTION This correspondence is in response to the communications received June 16, 2026. Claims 1-8 and 12-22 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Election/Restrictions Applicant’s election without traverse of Group I and Species I-A (e.g. wherein the second active layer is separate from the first connection electrode), claims 1-8 and 12-22 in the reply filed on June 16, 2026 is acknowledged. Specification The abstract of the disclosure is objected to because it exceeds 150 words. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b). Claim Objections Claim 21 is objected to because of the following informalities: The phrase, “wherein the first connection electrode is extends”, appears to have a grammatical error. Appropriate correction is required. Relevant Prior Art Cho et al. (US 2023/0074433) Fig. 7, shown below. PNG media_image1.png 392 542 media_image1.png Greyscale Lee et al. (US 2018/0012947) Fig. 9, shown below. PNG media_image2.png 598 496 media_image2.png Greyscale Seo et al. (US 2020/0286972) Fig. 10, shown below. PNG media_image3.png 476 658 media_image3.png Greyscale Lee (US 2020/0135772) Fig. 9, shown below. PNG media_image4.png 524 646 media_image4.png Greyscale Samsung Jeon et al. (US 11,495,650) Fig. 4, shown below. The two TFTs are at the same distance from the substrate. PNG media_image5.png 522 876 media_image5.png Greyscale Kang et al. (US 2023/0337482) Fig. 4A, shown below. The gate of GT connects to active region of upper TFT active region, but only schematically. PNG media_image6.png 486 752 media_image6.png Greyscale Kim et al. (US 2019/0214447) Figs. 4 and 6A, shown below. The gate of GT connects to active region of upper TFT active region, but only schematically. PNG media_image7.png 466 352 media_image7.png Greyscale PNG media_image8.png 328 488 media_image8.png Greyscale Park et al. (US 2022/0037456) Fig. 9, shown below. The two TFTs are at the same distance from the substrate. PNG media_image9.png 404 430 media_image9.png Greyscale Applicant’s Claim to Figure Comparison It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant. PNG media_image10.png 688 532 media_image10.png Greyscale Regarding claim 1, the Applicant discloses in Fig. 3, a thin film transistor substrate comprising: a first thin film transistor (T1, ¶ 0048) disposed on a substrate (100), the first thin film transistor (T1) including a first active layer (A1) and a first gate electrode (G1); a second thin film (T2) transistor disposed on the substrate (on 100), the second thin film transistor (T2) including a second active layer (A2) and a second gate electrode (G2), each of the second active layer (A2) and the second gate electrode (G2) being located farther away from the substrate (farther from 100) than the first active layer and the first gate electrode (A1 and G1 closer to 100, than A2 and G2); a first insulating layer (130, 140, 150) disposed between the first gate electrode and the second active layer (between G1 and A2); and a first connection electrode (D2) connecting the first gate electrode (G1) with the second active layer (A2), wherein the first connection electrode (D2) extends through a first contact hole in the first insulating layer (discontinuity in 130, 140, 150) and contacts both of the first gate electrode and the second active layer (D2 connects G1 with A2). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3, 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (CN 115662996 A) in view of Kim et al. (US 2021/0288123). PNG media_image11.png 454 844 media_image11.png Greyscale Regarding claim 1, the prior art of Huang discloses in Fig. 1, a thin film transistor substrate (plural TFTs shown on “substrate 100” on page 5, second to last ¶. Huang does not use the terminology of “thin film transistor substrate”, which will be addressed below in the combination rejection below.) comprising: a first thin film transistor (“thin film transistor may include an active layer 21, source electrode 22, The drain electrode 23 and the gate electrode 24”, page 5, last ¶, hereinafter referred to as ‘TFT1’) disposed on a substrate (“substrate 100” on page 5, second to last para), the first thin film transistor (TFT1) including a first active layer (“active layer 21”, page 5, last ¶) and a first gate electrode (“gate electrode 24”, page 5, last ¶); a second thin film transistor (“thin film transistor may have an active layer 11, a source electrode 12, a drain electrode 13 and a gate electrode 14”, page 5, last ¶, hereinafter referred to as ‘TFT2’) disposed on the substrate (TFT2 on 100), the second thin film transistor (TFT2) including a second active layer (“active layer 11”, page 5, last para) and a second gate electrode (“gate electrode 14”, page 5, last ¶), each of the second active layer (11) and the second gate electrode (14) being located farther away from the substrate (11/14 farther from 100) than the first active layer (21) and the first gate electrode (24, so 11/14 farther from 100 than 21/24); a first insulating layer (“interlayer dielectric layer 260 … interlayer buffer layer 250”, page 6, last ¶) disposed between the first gate electrode (24) and the second active layer (11); and a first connection electrode (“metal wiring 40”, second line page 6, with sub-portion 13, “drain electrode 13”, pg. 5, second to last line) connecting the first gate electrode (24) with the second active layer (40/13 connects 24 with 11, “gate electrode 24 of the second thin film transistor and the drain electrode 13 of the first thin film transistor are connected by a metal wiring 40”, page 6, first ¶), wherein the first connection electrode (40/13) extends through a first contact hole in the first insulating layer (40/13 passes through discontinuity in 260/250) and contacts both of the first gate electrode and the second active layer (“gate electrode 24 of the second thin film transistor and the drain electrode 13 of the first thin film transistor are connected by a metal wiring 40”, page 6, first ¶). Huang does not use the terminology of “thin film transistor substrate”, however it is clear that the substrate of Huang does support thin film transistor circuitry. Kim discloses an OLED display with TFT circuitry, where the substrate is referred to as “According to one or more embodiments, a thin-film transistor substrate includes a semiconductor layer disposed on a substrate”, ¶ 0007. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the feature of, “thin film transistor substrate”, as disclosed by Kim in the system of Huang, for the purpose of using a substrate which supports the manufacturing steps during formation and use of thin film transistors in service of a display device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. Regarding claim 3, the prior art of Huang discloses the thin film transistor substrate according to claim 1, and Huang discloses in Fig. 1, wherein one end of the second active layer is in contact with one side of the first connection electrode (lower end of 40 contacts 11, “metal wiring 40”, second line page 6, “active layer 11”, page 5, last para). Regarding claim 8, the prior art of Huang discloses the thin film transistor substrate according to claim 1, and Huang discloses in Fig. 1, wherein the first connection electrode (13) is a second drain electrode of the second thin film transistor (13 is described as “a drain electrode 13”, pg. 5, second to last line. The electrode 13 then is understood to be a drain support electrode, so the portion of second TFT being contacted is the drain region of 11/TFT2, where “thin film transistor may have an active layer 11, a source electrode 12, a drain electrode 13 and a gate electrode 14”, page 5, last ¶, hereinafter referred to as ‘TFT2’). Regarding claim 17, the prior art of Huang discloses the thin film transistor substrate according to claim 1, and Huang discloses in Fig. 1, further comprising: a third thin film transistor (“the active layer 31 of the third thin film transistor … the source/drain electrodes (32 and 33) of the third thin film transistor”, pg. 6, second to last ¶. These features make up the “third thin film transistor”, hereinafter referred to as ‘TFT3’) disposed on the substrate (disposed on “substrate 100” on page 5, second to last para), the third thin film transistor (TFT3) including a third active layer (“active layer 31”, pg. 6, second to last para) and a third gate electrode (“the gate electrode 34 of the third thin film transistor”, pg. 6, second to last para), wherein the third active layer (31) is disposed on a same layer as the first active layer (31 and 11 both on “layer 280”, pg. 7, second line), and wherein the third gate electrode (34) is disposed on a same layer as the first gate electrode (34 and 24 both on “layer 270”, pg. 7, line 1). Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (CN 115662996 A) in view of Kim et al. (US 2021/0288123) in view of Yamazaki et al. (US 9,472,682). Regarding claim 6, the prior art of Huang discloses the thin film transistor substrate according to claim 1, and Huang discloses, further comprising: a second insulating layer (“first insulating layer 270”, pg. 7, first line) disposed between the first active layer (“active layer 21”, page 5, last ¶) and the first gate electrode (“gate electrode 24”, page 5, last ¶). Huang does not disclose, “wherein the second insulating layer has a same pattern or a same width as the first gate electrode.” PNG media_image12.png 448 642 media_image12.png Greyscale Yamazaki discloses in Fig. 1B, wherein the second insulating layer (“gate insulating film 402”, col. 6, line 12) has a same pattern or a same width (shown in Fig. 1B) as the first gate electrode (“gate electrode layer 401”, col. 6, line 12-13). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the feature of, “wherein the second insulating layer has a same pattern or a same width as the first gate electrode”, as disclosed by Yamazaki in the system of Huang, for the purpose of using a purpose specific insulation layer that can keep the gate electrical field isolated to the channel area and not interact with the source and drain contact electrodes, which aids in the reducing unwanted charge build up between electrodes. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. Regarding claim 7, the prior art of Huang discloses the thin film transistor substrate according to claim 1, while Huang shows in the drawing the delineated regions of the channel and the source drain regions, however Huang is silent on the detail of, “wherein the second active layer includes a channel part and a connection part connected to one side of the channel part having better electrical conductivity than the channel part, and wherein the first connection electrode is in contact with the connection part.” Yamazaki discloses in Fig. 1B, wherein the second active layer includes a channel part (“channel formation region 403”, col. 6, line 13) and a connection part connected (“low-resistance region 404a, and a low-resistance region 404b”, col. 6, lines 11-12) to one side of the channel part (404a and 404b are connected to sides of 403) having better electrical conductivity than the channel part (e.g. the “low-resistance” meaning “better conductivity”), and wherein the first connection electrode is in contact with the connection part (the analogous “connection electrode” being the 405a or 405b of, “source electrode layer 405a and a drain electrode layer 405b which are electrically connected to the low-resistance region 404a and the low-resistance region 404b”, col. 6, lines 17-20). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the feature of, “wherein the second active layer includes a channel part and a connection part connected to one side of the channel part having better electrical conductivity than the channel part, and wherein the first connection electrode is in contact with the connection part.”, as disclosed by Yamazaki in the system of Huang, for the purpose of providing the basic functional components of a field effect transistor so that it can operate as intended, where a channel can be formed between two higher conductivity regions. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (CN 115662996 A) in view of Kim et al. (US 2021/0288123) in view of Zhou et al. (US 2019/0172954). Regarding claim 18, the prior art of Huang discloses the thin film transistor substrate according to claim 1, however Huang does not disclose, “further comprising: a light shielding layer overlapping with the first active layer and electrically connected to the first active layer, wherein the light shielding layer is disposed between the substrate and the first active layer.” PNG media_image13.png 494 650 media_image13.png Greyscale Zhou discloses in Fig. 13, further comprising: a light shielding layer (“light-shielding layer 20”, ¶ 0059) overlapping with the first active layer (“active layer 40 is a metal oxide semiconductor material.”, ¶ 0059) and electrically connected (by electrode composed of 71, 73 and 81, “the source contact hole 71 and the drain contact hole 72, while the source 81 is electrically connected to the light-shielding layer 20 through the signal via hole 73.”, ¶ 0081) to the first active layer (connected to 40), wherein the light shielding layer is disposed between the substrate and the first active layer (20 between “substrate 10”, ¶ 0059 and 20). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the feature of, “further comprising: a light shielding layer overlapping with the first active layer and electrically connected to the first active layer, wherein the light shielding layer is disposed between the substrate and the first active layer.”, as disclosed by Zhou in the system of Huang, for the purpose protecting the TFT from light that could interfere with it’s ideal function. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. Claims 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2020/0411559). PNG media_image14.png 362 712 media_image14.png Greyscale PNG media_image15.png 396 516 media_image15.png Greyscale PNG media_image16.png 370 728 media_image16.png Greyscale PNG media_image17.png 442 710 media_image17.png Greyscale Regarding claim 21, the prior art of Wu discloses in Figs. 5 (shown merely for the identification of the insulator layers), 8, 9 and 13, a display apparatus (see title, “Display Panel and Display Device”) comprising: a light emitting element (“light-emitting element 30”, ¶ 0057) disposed on a substrate (“substrate 10”, ¶ 0055); a first thin film transistor (“thin film transistor 22”, ¶ 0031) disposed on the substrate (on 10) and electrically connected to the light emitting element (22 connects to 30 by way of at least “electrode 222”, ¶ 0032), the first thin film transistor (22) including a first active layer (“active layer 211”, ¶ 0032) and a first gate electrode (“gate 224”, ¶ 0046); a second thin film transistor (“thin film transistor 21”, ¶ 0045) disposed on the substrate (on 10), the second thin film transistor (21) including a second active layer (“active layer 211”, ¶ 0045) and a second gate electrode (“gate 214”, ¶ 0050), each of the second active layer (211) and the second gate electrode (214) being located farther away from the substrate (10) than the first active layer (221) and the first gate electrode (224); a first insulating layer (“insulating layer 27”, ¶ 0054) disposed between the first gate electrode (224) and the second active layer (211); and a first connection electrode (see Figs. 8 and 9, “electrode 213”, ¶ 0034) connecting the first gate electrode (224 which includes extension that extends in downward direction in Fig. 8, which is then immediately below 213) with the second active layer (213 connects 224’s noted extension to 211, see Figs. 8 and 9), wherein the first connection electrode (213) is extends through a first contact hole in the first insulating layer (213 extends through a discontinuity in 27) and contacts both of the first gate electrode and the second active layer (213 contacts both the extension of 224 in Figs. 8 and 9, to 211). Figs. 8 and 9 of Wu do not disclose the light emitting device 30 as Fig. 13 does. So Fig. 8 and 9 of Wu do not disclose, “a light emitting element disposed on a substrate; … the first thin film transistor being electrically connected to the light emitting element;”. As stated above and repeated here, Fig. 13 shows these features, a light emitting element (“light-emitting element 30”, ¶ 0057) disposed on a substrate (“substrate 10”, ¶ 0055); … the first thin film transistor (22) being electrically connected to the light emitting element (22 connects to 30 by at least “electrode 222”, ¶ 0032);”. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the feature of, “a light emitting element disposed on a substrate; … the first thin film transistor being electrically connected to the light emitting element;”, as disclosed by Fig. 13 of Wu in the system of Figs. 8 and 9 of Wu, for the purpose providing a light emitting device and the electrical connections to the thin film transistor circuitry to allow for light emitting functionality to attain a fully functional display device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. PNG media_image18.png 350 726 media_image18.png Greyscale PNG media_image19.png 444 706 media_image19.png Greyscale Regarding claim 22, the prior art of Wu discloses in Fig. 5 and 13, a display apparatus (see title, “Display Panel and Display Device”) comprising: a light emitting element (“light-emitting element 30”, ¶ 0057) disposed on a substrate (“substrate 10”, ¶ 0055); a first thin film transistor (“thin film transistor 22”, ¶ 0031) disposed on the substrate (on 10) and including a first active layer (“active layer 221”, ¶ 0032), the first thin film transistor (22) being electrically connected to the light emitting element (22 connects to 30 by at least “electrode 222”, ¶ 0032); a second thin film transistor (“thin film transistor 21”, ¶ 0032) disposed on the substrate (on 10) and including a second active layer (“active layer 211”, ¶ 0032); and a first connection electrode (“electrode 222”, ¶ 0032) directly connected between the first active layer (221) and the second active layer (211), wherein the second active layer (211) is located farther away from the substrate (10) than the first active layer (211 farther from 10 than 221), and wherein a portion of the second active layer (left most portion of 211) directly contacts both of an upper surface of the first connection electrode (left most portion of 211 covers and directly contacts a right most portion of top surface of 222) and a side surface of the first connection electrode (left most portion of 211 covers a right most side surface of 222). Fig. 5 of Wu does not disclose the light emitting device 30 as Fig. 13 does. So Fig. 5 of Wu does not disclose, “a light emitting element disposed on a substrate; … the first thin film transistor being electrically connected to the light emitting element;”. As stated above and repeated here, Fig. 13 shows these features, a light emitting element (“light-emitting element 30”, ¶ 0057) disposed on a substrate (“substrate 10”, ¶ 0055); … the first thin film transistor (22) being electrically connected to the light emitting element (22 connects to 30 by at least “electrode 222”, ¶ 0032);”. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the feature of, “a light emitting element disposed on a substrate; … the first thin film transistor being electrically connected to the light emitting element;”, as disclosed by Fig. 13 of Wu in the system of Fig. 5 of Wu, for the purpose providing a light emitting device and the electrical connections to the thin film transistor circuitry to allow for light emitting functionality to attain a fully functional display device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. Allowable Subject Matter Claims 2, 4, 12-16, 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 2, the prior art of Huang et al. (CN 115662996 A) Fig. 1, shows the configuration of claim 1, but does not show the physical relationship between the “second active layer” and the “first connection electrode”, as detailed in claim 2, where the lower surface of the “second active layer” is in contact with “both of one side surface of the first connection electrode and a portion of an upper surface of the first connection electrode”. It is further unclear how to modify Fig. 1 of Huang, nor is there a clear motivation to modify Fig. 1 of Huang with the prior art of Wu (US 2020/0411559). “2. The thin film transistor substrate according to claim 1, wherein one side of a lower surface of the second active layer is in contact with both of one side surface of the first connection electrode and a portion of an upper surface of the first connection electrode.” Regarding claim 4, the prior art of Huang et al. (CN 115662996 A) Fig. 1, shows the configuration of claim 1, but does not show the physical relationship between the “second active layer” and the “first connection electrode”, as detailed in claim 4, where the “second active region” only has the lower portion of the “first connection electrode” connected thereto in Huang and not the italicized relationship detailed below. See Applicant’s Figs. 9 and 10. It is further unclear how to modify Fig. 1 of Huang, nor is there a clear motivation to modify Fig. 1 of Huang with the prior art of Wu (US 2020/0411559). “4. The thin film transistor substrate according to claim 1, wherein the second active layer is in contact with one side of the first connection electrode, an upper surface of the first connection electrode and another side of the first connection electrode opposite to the one side.” Regarding claim 5, the prior art of Huang et al. (CN 115662996 A) Fig. 1, shows the configuration of claim 1, but does not show the physical relationship between the “second active layer” and the “first connection electrode”, as detailed in claim 5, where the “second active region” only has the lower portion of the “first connection electrode” connected thereto in Huang and not the italicized relationship detailed below. See Applicant’s Fig. 3. It is further unclear how to modify Fig. 1 of Huang, nor is there a clear motivation to modify Fig. 1 of Huang with the prior art of Wu (US 2020/0411559). “5. The thin film transistor substrate according to claim 1, wherein the second thin film transistor further includes a second source electrode in contact with the second active layer, wherein one side of the second active layer is in contact with the first connection electrode, and another side of the second active layer is in contact with the second source electrode, and wherein an overlapping structure between the one side of the second active layer and the first connection electrode differs from an overlapping structure between the another side of the second active layer and the second source electrode.” Regarding claim 12, the prior art of Huang et al. (CN 115662996 A) Fig. 1, shows the configuration of claim 1, but does not show the physical relationship and connection electrode relationship between the position of the “first active layer” and the “third active layer” in comparison to the “substrate”. See italicized portion below highlighting the difference between, Applicant’s Fig. 3 compared to Huang’s Fig. 1. “12. The thin film transistor substrate according to claim 1, further comprising: a third thin film transistor disposed on the substrate, the third thin film transistor including a third active layer and a third gate electrode, each of the third active layer and the third gate electrode being located farther away from the substrate than the first active layer and the first gate electrode; a second insulating layer disposed between the first active layer and the first gate electrode; and a second connection electrode connecting the first active layer with the second active layer, wherein the second connection electrode extends through a second contact hole in the first insulating layer and the second insulating layer, and the second connection electrode contacts both of the first active layer and the second active layer.” Claims 13-16 are objected to, due to their dependence upon claim 12. Regarding claim 19, the prior art of Huang et al. (CN 115662996 A) Fig. 1, shows the configuration of claim 1, but does show a capacitor, but does not show the claimed position and shared electrical layers and connections as detailed in claim 19. “19. The thin film transistor substrate according to claim 1, further comprising: a first capacitor electrode electrically connected to the first gate electrode, the first capacitor electrode being disposed on a same layer as the first gate electrode; and a second capacitor electrode electrically connected to the light shielding layer, the second capacitor electrode being disposed on a same layer as the light shielding layer.” Regarding claim 20, the prior art of Huang et al. (CN 115662996 A) Fig. 1, shows the configuration of claim 18, but does show a capacitor, but does not show the claimed position and shared electrical layers and connections as detailed in claim 20. “20. The thin film transistor substrate according to claim 18, further comprising: a first capacitor electrode disposed on a same layer as the second gate electrode, and electrically connected to the first gate electrode through a second bridge electrode; and a second capacitor electrode disposed on a same layer as the first connection electrode, and electrically connected to the light shielding layer.” Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EDUARDO A RODELA/Primary Examiner, Art Unit 2893