DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-9 and 21-30 in the reply filed on 10/13/2025 is acknowledged.
Claim Objections
Claim 21 is objected to because of the following informalities: the “a transmitted configured to…” appear to be “a transmitter configured to…”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 21-22, 24, 25, 27, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US 2017/0,180,181; hereinafter Chen) in view of Yang (CN 101,340,738).
Regarding claims 1, 21, and 27, Chen disclose an apparatus (100, 200; Figs. 1, 2), system, and method for compensating impairments in an RF output, comprising:
a first/cancellation circuit (2081, 2082, 2083) configured to: receive a first input data (receive input data from 212) and a second input data (receive input data from 218), generate a first distortion term based on the first input data (the second computing circuit 2082 generate a first distortion term based on first input data from training device 218 and computing circuit 2081; paras. [0015], [0025], [0032]-[0033]), generate a second distortion term based on the second input data (the third computing circuit 2083 generate a second distortion term based on second input data from training device 218 and computing circuit 2081; paras. [0015], [0025], [0032]-[0033]); change a polarity of the first distortion term and the second distortion term (the first pre-distort signal and the second pre-distort signal should be phase shifted by an appropriate phase ϕ by the second computing circuit 1082 and the third computing circuit 1083 wherein polarity change (i.e. positive phase or negative phase) is inherent by the compensation phase shifting; paras. [0026], [0013]);
one or more subtraction circuits comprising a first subtraction circuit (2084) configured to subtract the first distortion term from the first input data to generate first difference data
(¶ [0032]); a second subtraction circuit (2085) configured to subtract the second distortion term from the second input data to generate second difference data (¶ [0032]); and a second circuit or transmitter (202, 204, 210, 206) configured to generate a radio frequency (RF) output using the first difference data and the second difference data (¶ [0032]), wherein the first difference data and the second difference data are configured to compensate, based on polarity changes of the first distortion term and the second distortion term, one or more impairments of the RF output (the processing device 208 may directly load the target compensation coefficient α and the target compensation phase ϕ to pre-distort the real data such that the power of the CIM3 signal in the transmitting signal is lower than the predetermined power level; paras. [0025]-[0026], [0031]-[0033], [0044]). Although Chen do not explicitly disclose a polarity change of the first and second distortion term and a subtraction circuit. However, the examiner takes official notice that it is notoriously old in the art using the absolute value of the difference data by using a combining or subtraction circuit and that the compensation phase shifting of Chen can include change in phase polarity, e.g. Yang disclose polarity as the positive phase or negative phase in a predistortion compensation processor (¶ [0079]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a distortion compensation value that has an opposite characteristic, e.g. phase polarity, to the distortion component in order to cancel out the distortion component.
Regarding claim 2 and 22, Chen and Yang disclose the apparatus and system of claim 1 and 21 respectively, wherein they do not explicitly the first distortion term and the second distortion term are configured to be equal in magnitudes to compensate the one or more impairments of the RF output. However, the examiner takes official notice that the first distortion term and the second distortion term are configured by the first training device 212, the detecting device 214, the determining device 216, and the second training device 218 which determine the compensation coefficient α and the compensation phase φ so that the first distortion term and the second distortion term are configured to be equal in magnitudes due to the equal amplitudes of the in-phase and quadrature components of the first pre-distort (CIM3) signal and second pre-distort (CIM3) signal which differ, i.e. phase shifted, by an appropriate phase ϕ (Chen, paras. [0025]-[0026], [0031], [0032]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to do so in order provide distortion compensation values that are equal in amplitude but opposite in phase so that the pre-distortion and the CIM3 distortion cancel each other out at the transmitter output.
Regarding claim 5, 24, and 28, Chen and Yang disclose the apparatus, system, and method of claim 1, 21, and 27 respectively wherein the first distortion term and the second distortion terms are generated further based on one or more of a plurality of coefficients, and wherein the plurality of coefficients comprise cancellation coefficients (the computing circuit 2082 generate the first distortion term based on cancellation coefficient α inputted from second training device 218 and computing circuit 2081, and the computing circuit 2083 generate the second distortion term based on compensation coefficient α inputted from training device 218 and computing circuit 2081, wherein the determining 216 is arranged to determine a specific coefficient from a predetermined coefficient range including an initial compensation coefficient and a target compensation coefficient; Chen, paras. [0032]-[0035]).
Regarding claim 25, Chen and Yang disclose the system of claim 21, where values of the one or more cancellation coefficients are determined based on a monitored power of a third counter intermodulation (CIM3) component in the radio frequency output (Chen; the first pre-distortion signal I′ and the second pre-distortion signal Q′ are arranged to pre-distort or calibrate the in-phase digital signal I and the quadrature digital signal Q respectively such that the power of CIM3 signal in the amplified signal can be reduced or diminished to an acceptable level; para. [0018]).
Claims 3 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US 2017/0,180,181; hereinafter Chen) in view of Yang (CN 101,340,738) further in view of Cho et al (US 2004/0,125,888; hereinafter Cho).
Regarding claim 3 and 23, Chen and Yang disclose the apparatus and system of claim 1 and 21 respectively, wherein the second circuit comprises a digital transmit data path configured to further process the first difference data and the second difference data using a first clock signal and a second clock signal respectively (further processing of the difference data from first circuit 2084 using an inherent first clock signal from first DAC 2022 and processing of the difference data from second circuit 2085 using an inherent second clock signal from a second DAC 2042; Chen, Fig. 2). Chen and Yang do not explicitly disclose a first clock signal and a second clock signal. In the same field of endeavor, Cho disclose processing a first digital signal via a first channel DAC using a first clock signal and processing a second digital signal via a second channel DAC using a second clock signal (para. [0015]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to do so in order to convert the first digital difference signal and the second digital difference signal into analog signals.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US 2017/0,180,181) in view of Yang (CN 101,340,738) in view of Cho et al (US 2004/0,125,888) further in view of Weber et al (US 2020/0,186,103; hereinafter Weber).
Regarding claim 4, Chen, Yang, and Cho disclose the apparatus of claim 3, wherein they do not disclose the second circuit is configured to: filter the first difference data and the second difference data, and subsequent to filtering, provide a first modified input data and a second modified input data. In the same field of endeavor, Weber disclose a second circuit (631, 632, 633, 634) is configured to: filter the first difference data and the second difference data, and subsequent to filtering, provide a first modified input data and a second modified input data (¶ [0057]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to do so in order to remove any undesired frequency components from the predistortion difference data.
Allowable Subject Matter
7. Claims 6-9, 26, 29-30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 6, Chen and Yang disclose the apparatus of claim 5, wherein the cited prior art fails to further disclose or fairly suggest further comprising a third circuit configured to: apply a single-sideband tone to input ports of the first circuit, and determine values of the cancellation coefficients based on the single-sideband tone.
Regarding claim 7, the cited prior art fails to further disclose or fairly suggest the apparatus of claim 6, wherein the impairments of the RF output comprise a CIM3 component, and wherein the third circuit is configured to monitor a power of the CIM3 component in the RF output while the values of the cancellation coefficients are adjusted, and wherein the RF output includes a first output signal and a second output signal.
Regarding claim 8, the cited prior art fails to further disclose or fairly suggest the apparatus of claim 7, wherein the cancellation coefficients are adjusted based on a value of the monitored power of the CIM3 component.
Regarding claim 9, the cited prior art fails to further disclose or fairly suggest the apparatus of claim 8, wherein the value corresponds to a minimum determined value of the monitored power.
Regarding claim 26, Chen and Yang disclose the system of claim 25, wherein the cited prior art fails to further disclose or fairly suggest the system further comprising a calibration circuit configured to apply a single sideband tone to input data of the cancellation circuit.
Regarding claim 29, Chen and Yang disclose the method of claim 27, wherein the cited prior art fails to further disclose or fairly suggest the method further comprising applying a single-sideband tone to input ports used for the first input data and the second input data, and adjusting one or more parameters used to generate the distortion terms based on a monitored characteristic of the radio frequency output.
Regarding claim 30, the cited prior art fails to further disclose or fairly suggest the method of claim 29, wherein the monitored characteristic comprises a power of a third counter intermodulation (CIM3) component in the radio frequency output.
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LANA N LE whose telephone number is (571) 272-7891. The examiner can normally be reached M-F 8:30am-4:30pm.
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/LANA N LE/Primary Examiner, Art Unit 2648