otice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Applicant’s election without traverse of Group I and species C in response/amendment is acknowledged. The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
The applicant is kindly asked to submitted any prior art documents in the information Disclosure Statement(s), if any, to be considered and made of record.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim(s) 1-16 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lang et al., US 20240149632 A1.
With regard to claim 1, Lang teaches an integrated circuit package (see figs. 1-6 and summary), comprising:
a substrate (i.e., 2001A) comprising an integrated circuit device mounting surface (clearly shown in at least figs. 2-3, para. 0042); and an optical fiber 4040 mount in the substrate (clearly shown in at least figs. 2-3, para. 0042, 0048), wherein the optical fiber mount comprises a support (Si layer as shown) comprising an optical fiber mounting channel 450 (clearly shown in at least figs.3), and the optical fiber mounting channel is configured to mount at least one clad optical fiber 4040 within a length of the optical fiber mounting channel 450’ (clearly shown in at least figs.3).
Lang Further teaches:
2. (Currently Amended) The integrated circuit package of claim 1, wherein the substrate comprises a cavity, and the optical fiber mount is within the cavity (clearly shown in at least figs.3).
3. (Currently Amended) The integrated circuit package of claim 2, further comprising a dielectric layer between the optical fiber mount and the integrated circuit device mounting surface, wherein the dielectric layer overlies at least a portion of the optical fiber mount (see at least figs. 2-3, wherein the layers include glass or silicon as shown in the figures with various separation layers including the layers supporting integrated circuits therebetween (at least parag. 0058 0012, 0011, 0040, 0050, 0044, 0030) .
4. (Currently Amended) The integrated circuit package of claim 1, wherein the optical fiber mounting channel is configured to mount a single optical fiber (see fig. 3).
5. (Currently Amended) The integrated circuit package of claim 1, wherein the optical fiber mounting channel has a semicircular cross-sectional shape; such limitation is extremely conventional, taking official notice, i.e., see cited prior art including US 11852876 B2, col. 2, 2nd parag., providing easy insertion of fibers into grooves.
6. (Currently Amended) The integrated circuit package of claim 1, wherein the optical fiber mount comprises a dielectric material chosen from silicon, organics, glass, ceramics, and combinations thereof (at least parag. 0058 0012, 0011, 0040, 0050, 0044, 0030)
.
With regard to claim 7, Lang teaches an integrated circuit package (see figs. 1-6 and summary), comprising:
a substrate (i.e., 2001A) comprising an integrated circuit device mounting surface (clearly shown in at least figs. 2, para. 0042); and an optical fiber 4040 mount in the substrate (clearly shown in at least figs. 2-3, para. 0042, 0048), wherein the optical fiber mount comprises a support layer (Si layer as shown) comprising a substantially planar optical fiber mounting surface (clearly shown in at least figs. 2-3);
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and an optical fiber mounting layer on the substantially planar optical fiber mounting surface (clearly shown in at least figs. 2-3), wherein the optical fiber mounting layer comprises an optical fiber mounting channel 450 with a length extending to an edge of the optical fiber mounting layer (clearly shown in at least figs. 2-3), and the optical fiber mounting channel has a depth that extends to the substantially planar optical fiber mounting surface (clearly shown in at least figs. 2-3), and a clad optical fiber 4040 in the optical fiber mounting channel 450’, wherein the clad optical fiber is optically coupled to an optical element (i.e., 200) proximal the edge of the optical fiber mounting layer (clearly shown in at least fig. 2).
8. (Currently Amended) The integrated circuit package of claim 7, wherein the substrate comprises a cavity, and the optical fiber mount is within the cavity (see fig. 3).
9. (Currently Amended) The integrated circuit package of claim 8, further comprising a dielectric layer between the optical fiber mount and the integrated circuit device mounting surface of the substrate, wherein the dielectric layer overlies at least a portion of the optical fiber mount (see at least figs. 2-3, wherein the layers include glass or silicon as shown in the figures with various separation layers including the layers supporting integrated circuits therebetween (at least parag. 0058 0012, 0011, 0040, 0050, 0044, 0030).
10. (Currently Amended) The integrated circuit package of claim 7, wherein the optical fiber mounting channel is configured to mount a single optical fiber (see fig. 3)..
11. (Currently Amended) The integrated circuit package of claim 7, wherein the optical fiber mounting channel has a semicircular cross-sectional shape, such limitation is extremely conventional, taking official notice, i.e., see cited prior art including US 11852876 B2, col. 2, 2nd parag., providing easy insertion of fibers into grooves.
12. (Currently Amended) The integrated circuit package of claim 7, wherein the support layer comprises a dielectric material, and the optical fiber mounting layer comprises a conductive material (at least parag. 0058 0012, 0011, 0040, 0050, 0044, 0030)
. 13. (Currently Amended) The integrated circuit package of claim 7, wherein the support layer comprises a dielectric material chosen from silicon, glass, ceramics, and combinations thereof, and the optical fiber mounting layer comprises an organic/glass material (at least parag. 0058 0012, 0011, 0040, 0050, 0044, 0030)
.
14. (Currently Amended) The integrated circuit package of claim 7, wherein the clad optical fiber is on the substantially planar optical fiber mounting surface (see fig. 3) . 15. (Currently Amended) The integrated circuit package of claim 7, further comprising an adhesive between the clad optical fiber and the substantially planar optical fiber mounting surface; such limitation is extremely conventional, taking official notice, as it provides fixing of fibers to grooves.
16. (Currently Amended) The integrated circuit package of claim 7, further comprising an adhesive between the clad optical fiber and a wall of the optical fiber mounting channel, such limitation is extremely conventional, taking official notice, i.e., see cited prior art including US 11852876 B2, col. 2, 2nd parag., providing easy insertion of fibers into grooves .
Citation of Relevant Prior Art
Prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. In accordance with MPEP 707.05 the following references are pertinent in rejection of this application since they provide substantially the same information disclosure as this patent does. These references are:
US 20180003899 A1
US 20240149632 A1
US 20220264759 A1
US 20210385000 A1
US 10365436 B2
US 11852876 B2
US 11109515 B1
US 20200132930 A1
US 20260082503 A1
US 11774689 B2
US 11178473 B1
US 11165509 B1
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAVEH C KIANNI whose telephone number is (571)272-2417. The examiner can normally be reached on 9-19.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hollweg can be reached on571-270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAVEH C KIANNI/Primary Examiner, Art Unit 2874
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