DETAILED ACTION
This Office Action is in response to the Response to Restriction/Election filed 09 February 2026. Claims 1-20 are pending but Claims 19-20 are withdrawn from consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 in the reply filed on 09 February 2026 is acknowledged. In accordance with Applicant’s election, Claims 19-20 are withdrawn from consideration as being directed to unelected embodiment Species 2.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 10 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 2, Applicant claims, in Lines 3-4, “a width of the first source/drain layer in the second direction increases along the third direction.” This limitation is unclear, because it does not state the direction of the third direction which sees the increase (does the width increase upward or downward)
Applicant’s specification clarifies that the width increases in the downward direction ([0039] In some exemplary embodiments, as shown in FIG. 4, the first source/drain layer 140a may have a sidewall profile having an inclination that allows a width to be gradually increased downward when viewed in a sectional view in the second direction.) For purposes of examination, the claim will be treated as stating “a width of the first source/drain layer in the second direction increases along the downward third direction.”
Similarly, Claim 10 claims in Lines 3-4, “a width of the first source/drain layer in the second direction increases along the third direction.” This is unclear for the same reasons and Claim 10 is rejected for the same reasons as Claim 2. For purposes of examination, the claim will be treated as stating “a width of the first source/drain layer in the second direction increases along the downward third direction.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 8 is/are rejected under 35 U.S.C. 102(a)(1) (or alternatively under 102(a(2)) as being anticipated by Ye et. al (US 2022/0310787 A1).
Regarding Claim 1, Ye discloses (as shown in Fig. 1, 10A-22B) A semiconductor device ([0026] FIG. 1 illustrates an example of nano-FETs (e.g., nanosheet FETs, nanosheet FETs, or the like)) comprising:
a substrate ([0026] a substrate 100 (e.g., a semiconductor substrate)) extending in a first direction (See An. Fig. 1, D1) and a second direction (See An. Fig. 1, D2) perpendicular to the first direction (D1); ((See An. Fig. 1, showing the first direction D1 is perpendicular to the second direction D2))
a first active pattern ([0026] fins 102) protruding from a top surface of the substrate (100) and extending in the first direction; ([0026] over fins 102 on a substrate 100 (e.g., a semiconductor substrate), wherein the nanostructures 104 act as channel regions for the GAA-FETs.) (See An. Fig. 1, showing the fins 102 extending in the first direction D1)
an isolation pattern ([0026] Isolation regions 106) covering a sidewall of the first active pattern (102) on the substrate (100); ([0026] Isolation regions 106 are disposed between adjacent fins 102)
first silicon patterns ([0026] The nano-FETs comprise nanostructures 104) ([0052] In some embodiments, the second semiconductor layers 304A-304C (collectively referred to as second semiconductor layers 304) are formed of a second semiconductor material. In some embodiments, the second semiconductor material is silicon) spaced apart from each other in a third direction (See An. Fig. 1, D3) on the first active pattern (102), (See An. Fig. 1)
the third direction (D3) perpendicular to the first direction (D1) and the second direction (D2); (See An. Fig. 1)
a first source/drain layer ([0026] Epitaxial source/drain regions 108) extending in the third direction (D3) from a top surface of the first active pattern (102) on the first active pattern (102), ([0026] Epitaxial source/drain regions 108 are disposed on the fins 102 on opposing sides of the gate dielectric layers 110 and the gate electrodes 112.)
and in contact with sidewalls of the first silicon patterns (304), (See Fig. 1, showing the epitaxial source/drain layer 108 in contact with the nanostructures 104)
wherein a sidewall of the first source/drain layer (104) in the second direction (D2) has a constant inclination with respect to the top surface of the substrate (100); (See Fig. 1, showing the sidewalls of the epitaxial source/drain layer 108 are vertical)
and a gate structure ([0026] Gate electrodes 112 are over the gate dielectrics 110) extending in the second direction (D2) while filling a gap between the first silicon patterns (304, 104) on the substrate (100). (See Fig. 1)
Regarding Claim 2, Ye further discloses (as shown in Fig. 1) wherein the sidewall of the first source/drain layer (108) in the second direction (D2) has a vertical profile or has an inclination such that a width of the first source/drain layer in the second direction increases along the third direction. (See Fig. 1, showing the sidewalls of epitaxial source/drain layer 108 are vertical)
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Regarding Claim 5, Ye further discloses (as shown in Fig. 1) wherein a top surface of the first source/drain layer (108) and a top surface of the first silicon pattern (104) located at an uppermost portion are located on a same plane. (See Fig. 1, showing the source/drain regions 108 end at the top surface of the top nanostructure 104)
Regarding Claim 8, Ye further discloses (as shown in Fig. 1, 22A) wherein a sidewall of the gate structure (110, 112; [0081] replacement gate structure 326 is formed in the gate trench GT between the gate spacers 314) contacts the first source/drain layer (108, 322). (See Fig. 22A, showing the epitaxial source/drain structures contact the gate spacer 314)
Claim(s) 1, 6-7, 9-10, 13-14, 16-17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Fung (US 2023/0253405 A1)
Alternatively, Claim 1 can be rejected under 102(a)(2) by Fung (US 2023/0253405 A1)
Regarding Claim 1, Fung discloses (as shown in Figs. 3B, 6D17A-B) A semiconductor device ([0009] FIGS. 1-17B show exemplary sequential processes for manufacturing the GAA FET device) comprising:
a substrate ([0011] As shown in FIG. 1, a p-well 11 for n-channel FETs (n-channel region) and an n-well 12 for p-channel FETs (p-channel region) are formed in a substrate 10) extending in a first direction (Y-direction) and a second direction (X-Direction) perpendicular to the first direction (Y-direction); (See Fig. 6D, showing the substrate 10, 11, 12 extending in the perpendicular X and Y directions)
a first active pattern ([0018] fin structures 33 extending in the Y direction ) ([0030] the fin structures formed over the p-well 11 (i.e., n-channel FET region)) protruding from a top surface of the substrate (10) and extending in the first direction (Y-direction); ([0018] fin structures 33 extending in the Y direction )
an isolation pattern ([0021] isolation layer 20) covering a sidewall of the first active pattern (33, 11) on the substrate (10); (See Fig. 17B, showing isolation layers 20 on the sidewalls of the fins of p-well 11)
first silicon patterns ([0014] In some embodiments, the first semiconductor layers 30 … are made of Si, a Si compound, SiGe, Ge or a Ge compound.) spaced apart from each other in a third direction (vertical or Z-direction) (Se Fig. 17A, showing the first semiconductor layers 30 stacked ion the Z-direction) on the first active pattern (33), ([0018] Next, as shown in FIGS. 3A and 3B, the stacked layers of the first and second semiconductor layers 30, 35 are patterned using patterning operations including photo-lithography and etching, thereby the stacked layers are formed into fin structures 33)
the third direction (Z-direction) perpendicular to the first direction (Y-direction) and the second direction (X-direction); (See Fig. 17A-B)
a first source/drain layer ([0040] Then, second S/D layers 215) extending in the third direction (Z-Direction) from a top surface of the first active pattern (33) on the first active pattern (33), (See Fig. 17B, showing the second S/D layer 215 extending vertically from the fin in the first region 11)
and in contact with sidewalls of the first silicon patterns (110), (See Fig. 17A, showing the second S/D layers 215 are in contact with the first semiconductor layers 110)
wherein a sidewall of the first source/drain layer (215) in the second has a constant inclination with respect to the top surface of the substrate (10); (See fig. 17B, showing the second S/D layer 215 having vertical sidewalls)
a first gate structure ([0054] The gate electrode layer 130 is formed on the gate dielectric layer 120 to surround each channel region 110.) extending in the second direction (X-Direction) while filling a gap between the first silicon patterns (110) on the substrate (10, 11, 12); ([0054] The gate electrode layer 130 is formed on the gate dielectric layer 120 to surround each channel region 110.)
Regarding Claim 6, Fung further discloses (as shown in Figs. 17A-B) wherein a first spacer ([0027] Further, side wall spacer layers 140) is provided on a sidewall of the gate structure (130, 120), ([0027] Further, side wall spacer layers 140 are formed on opposite sidewalls of the sacrificial gate structure)
and a second spacer ([0039] sidewall spacer layers 140) completely covering the sidewall of the first source/drain layer (215) is provided. (See Fig. 17B, showing sidewall spacers 140 covering the sidewalls of the second S/D layers 215)
Regarding Claim 7, Fung further discloses (as shown in Figs. 17A-B) wherein a bottom surface of the first spacer (140) formed on the sidewall of the gate structure (130, 120) located on the first silicon pattern (33, 11) located at an uppermost portion contacts a top surface of the first source/drain layer (215). (See Fig. 17A, showing the sidewall spacer layers 140 extend partially onto the second S/D layers 215)
Regarding Claim 9, Fung discloses (as shown in Figs. 3B, 6D17A-B) A semiconductor device ([0009] FIGS. 1-17B show exemplary sequential processes for manufacturing the GAA FET device) comprising:
a substrate ([0011] As shown in FIG. 1, a p-well 11 for n-channel FETs (n-channel region) and an n-well 12 for p-channel FETs (p-channel region) are formed in a substrate 10) extending in a first direction (Y-direction) and a second direction (X-Direction) perpendicular to the first direction (Y-direction); (See Fig. 6D, showing the substrate 10, 11, 12 extending in the perpendicular X and Y directions)
a first active pattern ([0018] fin structures 33 extending in the Y direction ) ([0030] the fin structures formed over the p-well 11 (i.e., n-channel FET region)) protruding from a top surface of the substrate (10) in a first region ([0030] p-well 11) and extending in the first direction (Y-direction); ([0018] fin structures 33 extending in the Y direction )
first silicon patterns ([0014] In some embodiments, the first semiconductor layers 30 … are made of Si, a Si compound, SiGe, Ge or a Ge compound.) spaced apart from each other in a third direction (vertical or Z-direction) (Se Fig. 17A, showing the first semiconductor layers 30 stacked ion the Z-direction) on the first active pattern (33), ([0018] Next, as shown in FIGS. 3A and 3B, the stacked layers of the first and second semiconductor layers 30, 35 are patterned using patterning operations including photo-lithography and etching, thereby the stacked layers are formed into fin structures 33)
the third direction (Z-direction) perpendicular to the first direction (Y-direction) and the second direction (X-direction); (See Fig. 17A-B)
a first source/drain layer ([0040] Then, second S/D layers 215) extending in the third direction (Z-Direction) from a top surface of the first active pattern (33) on the first active pattern (33), (See Fig. 17B, showing the second S/D layer 215 extending vertically from the fin in the first region 11)
and in contact with sidewalls of the first silicon patterns (110), (See Fig. 17A, showing the second S/D layers 215 are in contact with the first semiconductor layers 110)
wherein a sidewall of the first source/drain layer (215) in the second has a constant inclination with respect to the top surface of the substrate (10); (See fig. 17B, showing the second S/D layer 215 having vertical sidewalls)
a second active pattern ([0018] fin structures 33 extending in the Y direction ) ([0031] fin structures over the n-well 12 (i.e., p-channel FET region).) protruding from a top surface of the substrate (10) in a first region ([0031] n-well 12) and extending in the second direction (Y-direction); ([0018] fin structures 33 extending in the Y direction )
second silicon patterns ([0014] In some embodiments, the first semiconductor layers 30 … are made of Si, a Si compound, SiGe, Ge or a Ge compound.) spaced apart from each other in a third direction (vertical or Z-direction) (Se Fig. 17A, showing the first semiconductor layers 30 stacked ion the Z-direction) on the first active pattern (33), ([0018] Next, as shown in FIGS. 3A and 3B, the stacked layers of the first and second semiconductor layers 30, 35 are patterned using patterning operations including photo-lithography and etching, thereby the stacked layers are formed into fin structures 33)
a second source/drain layer ([0037] Then, first source/drain (S/D) layers 210 for p-channel FETs) extending in the third direction (Z-Direction) from a top surface of the second active pattern (33) on the second active pattern (33), (See Fig. 17B, showing the first S/D layer 210 extending vertically from the fin in the first region 12)
and in contact with sidewalls of the second silicon patterns (110), (See Fig. 17A, showing the second S/D layers 210 are in contact with the first semiconductor layers 110)
wherein a sidewall of the second source/drain layer (210) in the second direction has a profile in which a portion protrudes; (See Fig. 17B, which shows the first S/D layer 210 having an octagonal shape)
a first gate structure ([0054] The gate electrode layer 130 is formed on the gate dielectric layer 120 to surround each channel region 110.) extending in the second direction (X-Direction) while filling a gap between the first silicon patterns (110) on the substrate (10, 11, 12); ([0054] The gate electrode layer 130 is formed on the gate dielectric layer 120 to surround each channel region 110.)
and a second gate structure ([0054] The gate electrode layer 130 is formed on the gate dielectric layer 120 to surround each channel region 110.) extending in the second direction (X-Direction) while filling a gap between the second silicon patterns (110) on the substrate (10, 11, 12). ([0054] The gate electrode layer 130 is formed on the gate dielectric layer 120 to surround each channel region 110.)
Regarding Claim 10, Fung further discloses (as shown in Fig. 17B) wherein the sidewall of the first source/drain layer (215) in the second direction (X-Direction) has a vertical profile or has an inclination such that a width of the first source/drain layer in the second direction increases along the third direction (Z-direction). (See Fig. 17B, showing the second S/D layer 215 having vertical sidewalls)
Regarding Claim 13, Fung further discloses (as shown in Fig. 17A) wherein a top surface of the first source/drain layer (215) and a top surface of the first silicon pattern (130) located at an uppermost portion are located on a same plane. (See Fig. 17A)
Regarding Claim 14, Fung further discloses (as shown in Fig. 17A) wherein a sidewall of the first gate structure (130, 120) contacts the first source/drain layer (215). (See Fig. 17A, showing the second S/D layers 215 contact the sidewalls of the gate dielectric 120)
Regarding Claim 16, Fung further discloses (as shown in Fig. 17B) wherein the second source/drain layer (210) has a polygonal shape in which a center portion protrudes when viewed in a sectional view in the second direction. (See fig. 17B, showing the first S/D layer 210 having an octagonal shape with the center portion wider than the top or bottom portions)
Regarding Claim 17, Fung further discloses (as shown in Fig. 6D) wherein ends of the first gate structure (130, 120) and the second gate structure (130, 120) are connected to each other so that the first gate structure (130, 120) and the second gate structure (130, 120) are provided as one common gate structure. (See Fig. 6D, showing the sacrificial gate 40 extends across both the first 11 and second 12 regions)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ye as applied to claim 1 above.
Regarding Claim 3, Ye further discloses (as shown in Fig.1, Figs. 10A-22B) wherein the first source/drain layer (108, [0069] In FIGS. 18A-18B, epitaxial source/drain structures 322) includes silicon germanium doped with P-type impurities. ([0070] For example, if the nanostructure layers 304 are silicon, the epitaxial source/drain structures 322 may comprise materials exerting a compressive strain on the nanostructure layers 304, such as silicon germanium, boron doped silicon germanium…)
However, Ye fails to disclose that the source/drain layer (108. 322) is single crystal.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to make the epitaxial source/drain structures 322 in Ye be single crystal. Epitaxially grown single crystal silicon germanium is a well-known source/drain material. Therefore, it would have been obvious for the epitaxial silicon germanium to be single crystal.
Regarding Claim 4, Ye further discloses (as shown in Fig.1, Figs. 10A-22B) wherein the P-type impurities have a concentration of 1E19 /cm3 to 1E22 /cm3. ([0071] The source/drain regions may have an impurity concentration of between about 1×1017 atoms/cm3 and about 1×1022 atoms/cm.3 )
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ye as applied to claim 1 above, and further in view of Tsai et. al (US 2017/0250281 A1).
Regarding Claim 6, Ye further discloses (as shown in Fig. 1, 22A) wherein a first spacer [0081] the gate spacers 314) is provided on a sidewall of the gate structure ([0081] replacement gate structure 326) [0081] replacement gate structure 326 is formed in the gate trench GT between the gate spacers 314)
However, Ye fails to disclose a second spacer completely covering the sidewall of the first source/drain layer (108, 322) is provided.
Tsai discloses (as shown in Fig. 1) a second spacer ([0009] second spacers 130) completely covering the sidewall of the first source/drain layer ([0009] source and drain regions 135) is provided. ([0009] second spacers 130 formed on opposite sidewalls of the source and drain regions 135)
Tsai teaches that the second spacers 130 keep the sources/drains of adjacent fins from merging together, leading to unform growth of the epitaxy material. (]0018] Due to the existence of the second spacers 130, as shown in FIG. 2I, the epitaxy material is slightly over-grown but the protruded portions 135A of the epitaxy material filled in the adjacent recesses 132 will not merge or contact each other, which leads to controlled and uniform growth of the epitaxy material.) It would have been obvious to a person having ordinary sill in the art before the effective filing date of the application to have second spacers covering the sidewalls of the source/drain layer in Ye in order to prevent the source/drain regions from merging.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fung as applied to claim 9 above, and further in view of Yeong et. al (US 2022/0262911 A1).
Fung fails to disclose wherein an inner spacer is further formed between a sidewall of the second gate structure (130, 120) and the second source/drain layer (210).
Yeong discloses (as shown in Fig. 25A) wherein an inner spacer ([0044] inner spacers 86) is further formed between a sidewall of the second gate structure ([0015] The gate structures 100 include gate dielectrics 102 and gate electrodes 104) and the second source/drain layer (210). ([0044] The inner spacers 86 act as isolation features between the subsequently formed source/drain regions and the subsequently formed gate structures)
Yeong teaches that the inner spacers 86, act as isolation features between the source/drain regions and the gate. ([0044] The inner spacers 86 act as isolation features between the subsequently formed source/drain regions and the subsequently formed gate structures) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have an inner spacer is further formed between a sidewall of the second gate structure and the second source/drain layer in order to isolate the second source/drain region from the second gate.
Allowable Subject Matter
Claim 11-12, 15 objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 11, Fung further discloses (as shown in Fig.17B) wherein the first source/drain layer (215) includes silicon germanium ([0040] In this embodiment, the second S/D layers 215 include Si.sub.1-xGe.sub.x, where x is equal to or greater than about 0.4, and in some embodiments, x is greater than about 0.7 to about 1.0.)
However, Fung fails to disclose wherein the first source/drain layer includes single crystal silicon germanium doped with P-type impurities.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to make the epitaxial source/drain structures 322 in Ye be single crystal. Epitaxially grown single crystal silicon germanium is a well-known source/drain material. Therefore, it would have been obvious for the epitaxial silicon germanium to be single crystal.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to dope the source drain of the p-type GAAFET with a p-type impurity. Doping of the source/drain of a p-type transistor with a Group III element is a well-known technique to reduce contact resistance. (For example, please note Cheng which discloses doping a p-type transistor with p-type dopants ([0057] After further processing, the epitaxial source/drain regions 140 become the source/drain regions for transistor devices, such as, for example, NFETs or PFETs, and can comprise … in-situ boron doped (ISBD) SiGe for p-type devices, at concentrations of about 1×1019 /cm3 to about 3×1021/cm3)
However, the first source/drain layer in Fung is not a p-type GAAFET, it is a n-type GAAFET. N-type GAAFETs are typically doped with n-type impurities.
Because the source/drain regions have different shapes (n-type S/D layers having vertical sidewalls and spacers, p-type S/D regions having octagonal shape with no spacers), it would not be obvious to switch the p-type and n-type transistors.
Because Fung discloses a different configuration than claimed, and it would not be obvious to switch the configuration, Claim 11 contains allowable subject matter.
Regarding Claim 12, Fung fails to disclose wherein the P-type impurities have a concentration of 1E19 /cm3 to 1E22 /cm3.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application would know how to optimize the doping concentration to minimize contact resistance. Furthermore, the claimed range is a typical doping range for source/drain regions of p-type transistors, as evidenced by Cheng. ([0057] After further processing, the epitaxial source/drain regions 140 become the source/drain regions for transistor devices, such as, for example, NFETs or PFETs, and can comprise … in-situ boron doped (ISBD) SiGe for p-type devices, at concentrations of about 1×1019 /cm3 to about 3×1021/cm3)
However, Claim 12 depends from Claim 11, and therefore contains allowable subject matter for the same reasons.
Regarding Claim 15, Fung further discloses (as shown in Fig.17B) wherein the second source/drain layer (215) includes silicon germanium ([0040] The materials for the first S/D layers 210 may be one or more of Si, Ge, SiGe…)
However, Fung fails to disclose wherein the first source/drain layer includes single crystal silicon germanium doped with N-type impurities.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to make the epitaxial source/drain structures 322 in Ye be single crystal. Epitaxially grown single crystal silicon germanium is a well-known source/drain material. Therefore, it would have been obvious for the epitaxial silicon germanium to be single crystal.
However, Fung discloses that the second source/drain layer is either undoped or doped with a p-type dopant ([0066] the first S/D layer 210 includes Si or Si.sub.1-xGe.sub.x with or without an additional dopant such as boron (B))
Because the source/drain regions have different shapes (n-type S/D layers having vertical sidewalls and spacers, p-type S/D regions having octagonal shape with no spacers), it would not be obvious to switch the p-type and n-type transistors.
Because Fung discloses a different configuration than claimed, and it would not be obvious to switch the configuration, Claim 15 contains allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
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/JASON JAMES GREAVING/ Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893