DETAILED ACTION
This Office Action is in response to the Amendments filed 16 July 2026. Claims 1-18 are pending in this application. Claims 19-20 are withdrawn.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim 11 allowable. The restriction requirement between Species 1 and 2, as set forth in the Office action mailed on 10 December 2025 , has been reconsidered in view of the allowability of claims to the elected invention pursuant to MPEP § 821.04(a). The restriction requirement is maintained because the nonelected claims do not require all the limitations of an allowable claim.
Claim Rejections - 35 USC § 112
Applicant’s amendments have addressed the previous 112b issues. The 112b rejections are therefore withdrawn.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 6-8 is/are rejected under 35 U.S.C. 102a(2) as being anticipated by (US 2023/0253405 A1) (of record).
Regarding Claim 1, Fung discloses (as shown in Figs. 3B, 6D17A-B) A semiconductor device ([0009] FIGS. 1-17B show exemplary sequential processes for manufacturing the GAA FET device) comprising:
a substrate ([0011] As shown in FIG. 1, a p-well 11 for n-channel FETs (n-channel region) and an n-well 12 for p-channel FETs (p-channel region) are formed in a substrate 10) extending in a first direction (Y-direction) and a second direction (X-Direction) perpendicular to the first direction (Y-direction); (See Fig. 6D, showing the substrate 10, 11, 12 extending in the perpendicular X and Y directions)
a first active pattern ([0018] fin structures 33 extending in the Y direction ) ([0030] the fin structures formed over the p-well 11 (i.e., n-channel FET region)) protruding from a top surface of the substrate (10) and extending in the first direction (Y-direction); ([0018] fin structures 33 extending in the Y direction )
an isolation pattern ([0021] isolation layer 20) covering a sidewall of the first active pattern (33, 11) on the substrate (10); (See Fig. 17B, showing isolation layers 20 on the sidewalls of the fins of p-well 11)
first silicon patterns ([0014] In some embodiments, the first semiconductor layers 30 … are made of Si, a Si compound, SiGe, Ge or a Ge compound.) spaced apart from each other in a third direction (vertical or Z-direction) (Se Fig. 17A, showing the first semiconductor layers 30 stacked ion the Z-direction) on the first active pattern (33), ([0018] Next, as shown in FIGS. 3A and 3B, the stacked layers of the first and second semiconductor layers 30, 35 are patterned using patterning operations including photo-lithography and etching, thereby the stacked layers are formed into fin structures 33)
the third direction (Z-direction) perpendicular to the first direction (Y-direction) and the second direction (X-direction); (See Fig. 17A-B)
a first source/drain layer ([0040] Then, second S/D layers 215) extending in the third direction (Z-Direction) from a top surface of the first active pattern (33) on the first active pattern (33), (See Fig. 17B, showing the second S/D layer 215 extending vertically from the fin in the first region 11)
and in contact with sidewalls of the first silicon patterns (110), (See Fig. 17A, showing the second S/D layers 215 are in contact with the first semiconductor layers 110)
wherein a sidewall of the first source/drain layer (215) in the second has a constant inclination with respect to the top surface of the substrate (10); (See fig. 17B, showing the second S/D layer 215 having vertical sidewalls)
a second active pattern ([0018] fin structures 33 extending in the Y direction ) ([0031] fin structures over the n-well 12 (i.e., p-channel FET region).) protruding from a top surface of the substrate (10) in a first region ([0031] n-well 12) and extending in the second direction (Y-direction); ([0018] fin structures 33 extending in the Y direction )
second silicon patterns ([0014] In some embodiments, the first semiconductor layers 30 … are made of Si, a Si compound, SiGe, Ge or a Ge compound.) spaced apart from each other in a third direction (vertical or Z-direction) (Se Fig. 17A, showing the first semiconductor layers 30 stacked ion the Z-direction) on the first active pattern (33), ([0018] Next, as shown in FIGS. 3A and 3B, the stacked layers of the first and second semiconductor layers 30, 35 are patterned using patterning operations including photo-lithography and etching, thereby the stacked layers are formed into fin structures 33)
a second source/drain layer ([0037] Then, first source/drain (S/D) layers 210 for p-channel FETs) extending in the third direction (Z-Direction) from a top surface of the second active pattern (33) on the second active pattern (33), (See Fig. 17B, showing the first S/D layer 210 extending vertically from the fin in the first region 12)
and in contact with sidewalls of the second silicon patterns (110), (See Fig. 17A, showing the second S/D layers 210 are in contact with the first semiconductor layers 110)
wherein a sidewall of the second source/drain layer (210) in the second direction has a profile in which a portion protrudes; (See Fig. 17B, which shows the first S/D layer 210 having an octagonal shape)
a first gate structure ([0054] The gate electrode layer 130 is formed on the gate dielectric layer 120 to surround each channel region 110.) extending in the second direction (X-Direction) while filling a gap between the first silicon patterns (110) on the substrate (10, 11, 12); ([0054] The gate electrode layer 130 is formed on the gate dielectric layer 120 to surround each channel region 110.)
and a second gate structure ([0054] The gate electrode layer 130 is formed on the gate dielectric layer 120 to surround each channel region 110.) extending in the second direction (X-Direction) while filling a gap between the second silicon patterns (110) on the substrate (10, 11, 12). ([0054] The gate electrode layer 130 is formed on the gate dielectric layer 120 to surround each channel region 110.)
wherein the first source/drain layer (215) includes impurities of a first conductivity type ([0050] second S/D layer 215 in the n-channel region) and the second source/drain layer (210) includes impurities of a second conductivity type ([0050] first S/D layers 210 in the p-channel region) opposite the first conductivity type.
Regarding Claim 2, Fung further discloses (as shown in Fig. 17B) wherein the sidewall of the first source/drain (215) layer in the second direction has a vertical profile (See Fig. 17B, showing the second S/D layer 215 has vertical sidewalls)
or has an inclination such that a width of the first source/drain layer in the second direction increases along the third direction toward the substrate.
Regarding Claim 6, Fung further discloses (as shown in Figs. 17A-B) wherein a first spacer ([0027] Further, side wall spacer layers 140) is provided on a sidewall of the gate structure (130, 120), ([0027] Further, side wall spacer layers 140 are formed on opposite sidewalls of the sacrificial gate structure)
and a second spacer ([0039] sidewall spacer layers 140) completely covering the sidewall of the first source/drain layer (215) is provided. (See Fig. 17B, showing sidewall spacers 140 covering the sidewalls of the second S/D layers 215)
Regarding Claim 7, Fung further discloses (as shown in Figs. 17A-B) wherein a bottom surface of the first spacer (140) formed on the sidewall of the gate structure (130, 120) located on the first silicon pattern (33, 11) located at an uppermost portion contacts a top surface of the first source/drain layer (215). (See Fig. 17A, showing the sidewall spacer layers 140 extend partially onto the second S/D layers 215)
Regarding Claim 8, Fung further discloses (as shown in Figs. 17A-B) wherein a sidewall ([0027] side wall spacer layers 14) of the first gate structure ([0027] Further, side wall spacer layers 140 are formed on opposite sidewalls of the sacrificial gate structure) contacts the first source/drain layer (215). ([0039] Thus, spaces 145 defined by the sidewall spacer layers 140 are formed. [0040] Then, second S/D layers 215 are formed in the spaces 145)
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fung as applied to claim 1 above, and further in view of Frougier et. al (US 2020/0312980 A1) (newly cited).
Regarding Claim 5, Fung fails to disclose wherein a top surface of the first source/drain layer (215) and a top surface of the first silicon pattern (30) located at an uppermost portion are located on a same plane.
Instead, Fung shows that the top surface of the first source/drain layer (215) extends beyond a top surface of the first silicon pattern (30).
Frougier discloses wherein a top surface of the first source/drain layer and a top surface of the first silicon pattern located at an uppermost portion are located on a same plane. ([0069] In other words, portions of the source/drain regions 602 (i.e., the overburden) can be removed such that a top surface of the source/drain regions 602 is coplanar to a top surface of the nanosheet stacks 104)
Frougier teaches that larger source drain regions lead to increased parasitic capacitance. ([0040] While larger contact sizes ensure a larger contact area, larger contacts also result in a higher parasitic capacitance to the gate and increases the risk of contact tip to tip shorts.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to trim the S/D contacts in Fung to have a top surface of the source/drain regions be coplanar with a top surface of the nanosheet stacks in order to reduce the size of the source/drain region, thereby reducing parasitic capacitance.
Allowable Subject Matter
Claim 3-5 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 3, Fung fails to disclose wherein the first source/drain layer (215) includes single crystal silicon germanium doped with P-type impurities.
However, Fung fails to disclose wherein the first source/drain layer includes single crystal silicon germanium doped with P-type impurities.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to make the epitaxial source/drain structures 322 in Ye be single crystal. Epitaxially grown single crystal silicon germanium is a well-known source/drain material. Therefore, it would have been obvious for the epitaxial silicon germanium to be single crystal.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to dope the source drain of the p-type GAAFET with a p-type impurity. Doping of the source/drain of a p-type transistor with a Group III element is a well-known technique to reduce contact resistance. (For example, please note Cheng which discloses doping a p-type transistor with p-type dopants ([0057] After further processing, the epitaxial source/drain regions 140 become the source/drain regions for transistor devices, such as, for example, NFETs or PFETs, and can comprise … in-situ boron doped (ISBD) SiGe for p-type devices, at concentrations of about 1×1019 /cm3 to about 3×1021/cm3)
However, the first source/drain layer in Fung is not a p-type GAAFET, it is a n-type GAAFET. N-type GAAFETs are typically doped with n-type impurities.
Because the source/drain regions have different shapes (n-type S/D layers having vertical sidewalls and spacers, p-type S/D regions having octagonal shape with no spacers), it would not be obvious to switch the p-type and n-type transistors.
Because Fung discloses a different configuration than claimed, and it would not be obvious to switch the configuration, Claim 3 contains allowable subject matter.
Regarding Claim 4, Claim 4 depends from Claim 3 and contains allowable subject matter for the same reasons.
Claim 9-18 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 9, the closest prior art is Fung (US 2023/0253405 A1) (of record). Fung discloses (as shown in Figs. 3B, 6D17A-B) A semiconductor device ([0009] FIGS. 1-17B show exemplary sequential processes for manufacturing the GAA FET device) comprising:
a substrate ([0011] As shown in FIG. 1, a p-well 11 for n-channel FETs (n-channel region) and an n-well 12 for p-channel FETs (p-channel region) are formed in a substrate 10) extending in a first direction (Y-direction) and a second direction (X-Direction) perpendicular to the first direction (Y-direction); (See Fig. 6D, showing the substrate 10, 11, 12 extending in the perpendicular X and Y directions)
a first active pattern ([0018] fin structures 33 extending in the Y direction ) ([0030] the fin structures formed over the p-well 11 (i.e., n-channel FET region)) protruding from a top surface of the substrate (10) in a first region ([0030] p-well 11) and extending in the first direction (Y-direction); ([0018] fin structures 33 extending in the Y direction )
first silicon patterns ([0014] In some embodiments, the first semiconductor layers 30 … are made of Si, a Si compound, SiGe, Ge or a Ge compound.) spaced apart from each other in a third direction (vertical or Z-direction) (Se Fig. 17A, showing the first semiconductor layers 30 stacked ion the Z-direction) on the first active pattern (33), ([0018] Next, as shown in FIGS. 3A and 3B, the stacked layers of the first and second semiconductor layers 30, 35 are patterned using patterning operations including photo-lithography and etching, thereby the stacked layers are formed into fin structures 33)
the third direction (Z-direction) perpendicular to the first direction (Y-direction) and the second direction (X-direction); (See Fig. 17A-B)
a first source/drain layer ([0040] Then, second S/D layers 215) extending in the third direction (Z-Direction) from a top surface of the first active pattern (33) on the first active pattern (33), (See Fig. 17B, showing the second S/D layer 215 extending vertically from the fin in the first region 11)
and in contact with sidewalls of the first silicon patterns (110), (See Fig. 17A, showing the second S/D layers 215 are in contact with the first semiconductor layers 110)
wherein a sidewall of the first source/drain layer (215) in the second has a constant inclination with respect to the top surface of the substrate (10); (See fig. 17B, showing the second S/D layer 215 having vertical sidewalls)
a second active pattern ([0018] fin structures 33 extending in the Y direction ) ([0031] fin structures over the n-well 12 (i.e., p-channel FET region).) protruding from a top surface of the substrate (10) in a first region ([0031] n-well 12) and extending in the second direction (Y-direction); ([0018] fin structures 33 extending in the Y direction )
second silicon patterns ([0014] In some embodiments, the first semiconductor layers 30 … are made of Si, a Si compound, SiGe, Ge or a Ge compound.) spaced apart from each other in a third direction (vertical or Z-direction) (Se Fig. 17A, showing the first semiconductor layers 30 stacked ion the Z-direction) on the first active pattern (33), ([0018] Next, as shown in FIGS. 3A and 3B, the stacked layers of the first and second semiconductor layers 30, 35 are patterned using patterning operations including photo-lithography and etching, thereby the stacked layers are formed into fin structures 33)
a second source/drain layer ([0037] Then, first source/drain (S/D) layers 210 for p-channel FETs) extending in the third direction (Z-Direction) from a top surface of the second active pattern (33) on the second active pattern (33), (See Fig. 17B, showing the first S/D layer 210 extending vertically from the fin in the first region 12)
and in contact with sidewalls of the second silicon patterns (110), (See Fig. 17A, showing the second S/D layers 210 are in contact with the first semiconductor layers 110)
wherein a sidewall of the second source/drain layer (210) in the second direction has a profile in which a portion protrudes; (See Fig. 17B, which shows the first S/D layer 210 having an octagonal shape)
a first gate structure ([0054] The gate electrode layer 130 is formed on the gate dielectric layer 120 to surround each channel region 110.) extending in the second direction (X-Direction) while filling a gap between the first silicon patterns (110) on the substrate (10, 11, 12); ([0054] The gate electrode layer 130 is formed on the gate dielectric layer 120 to surround each channel region 110.)
and a second gate structure ([0054] The gate electrode layer 130 is formed on the gate dielectric layer 120 to surround each channel region 110.) extending in the second direction (X-Direction) while filling a gap between the second silicon patterns (110) on the substrate (10, 11, 12). ([0054] The gate electrode layer 130 is formed on the gate dielectric layer 120 to surround each channel region 110.)
However, Fung fails to disclose wherein the first source/drain layer includes P-type impurities.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to dope the source drain of the p-type GAAFET with a p-type impurity. Doping of the source/drain of a p-type transistor with a Group III element is a well-known technique to reduce contact resistance. (For example, please note Cheng which discloses doping a p-type transistor with p-type dopants ([0057] After further processing, the epitaxial source/drain regions 140 become the source/drain regions for transistor devices, such as, for example, NFETs or PFETs, and can comprise … in-situ boron doped (ISBD) SiGe for p-type devices, at concentrations of about 1×1019 /cm3 to about 3×1021/cm3)
However, the first source/drain layer in Fung is not a p-type GAAFET, it is a n-type GAAFET. N-type GAAFETs are typically doped with n-type impurities.
Because the source/drain regions have different shapes (n-type S/D layers having vertical sidewalls and spacers, p-type S/D regions having octagonal shape with no spacers), it would not be obvious to switch the p-type and n-type transistors.
Because Fung discloses a different configuration than claimed, and it would not be obvious to switch the configuration, Claim 11 contains allowable subject matter.
Regarding Claims 10-18, Claims 10-18 depend from Claim 9 and are allowed for the same reasons.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON JAMES GREAVING/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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