Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-Final Office Action
DETAILED ACTION
Examiner’s Notes
(a) Claim date: 06/06/2023
(b) Priority date: 08/29/2022
(c) Invention: 3D semiconductor device simulation system to help optimize connectivity.
Claim Rejections - 35 USC 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:A person shall be entitled to a patent unless:(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.Claims 1, 4, 6, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by the prior art of record “Pu” <US 20210110096 A1>.(As to claim 1, 6, Pu discloses):1. A 3D semiconductor device simulation system [0085: “3D simulation performed by the off-chip tool”] comprising;
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a device structure file input module configured to receive a plurality of device structure files for a plurality of sub-devices obtained by dividing a semiconductor device to be simulated [0068: “schematic circuit diagram (e.g., a sub-circuit in a Simulation Program with Integrated Circuit Emphasis (SPICE) type and/or format)”] [Fig.1: receive files (S100), divide design (S200), perform simulation (S300, S400, S500)];
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a connection relationship extraction module configured to extract connection relationships between the device structure files for the sub-devices [Fig. 6 and 8, explaining connection wiring relationship (Fig. 6) and extraction files (Fig. 8, S-parameters)];
an interface condition application module configured to apply interface conditions to interface points of the device structure files according to the extracted connection relationships [Fig. 6 (interfacing), and 8 (extraction)];
and a simulation module configured to simulate an operation of the semiconductor device using the device structure files for the sub-devices and the interface conditions at interface points of adjacent sub-devices [0070: “the resistance obtained by step S330 may be converted using the additional tool (e.g., a circuit simulation tool) different from the on-chip tool to obtain the first S-parameter.”],
wherein the 3D semiconductor device simulation system [0085: “3D simulation performed by the off-chip tool”] is configured to simulate the semiconductor device using a plurality of device structure files for the sub-devices [Fig. 6].
(As to claim 4, Pu discloses):4. The 3D semiconductor device simulation system of claim 1, wherein the connection relationships between the plurality of device structure files include information about the interface surfaces of the adjacent sub-devices [Fig. 6], and are extracted by using the coordinate value information of the device structure files [Fig. 8].
Allowable Subject Matter
The following claims would be allowable if all rejections/objections cited in this office action (if any) are overcome and rewritten to include all of the limitations of the base claim and any intervening claims.The reason for this allowance is: the claimed subject matter could not have been anticipated or obviated using any prior arts.Allowable claims are: 2-3, 5, 7-11.
Conclusion
The prior art made of record in the form PTO-892 are not relied upon is considered pertinent to applicant's disclosure.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.Contact information:Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED ALAM whose telephone number is (571) 270-1507, email address: [mohammed.alam@uspto.gov] and fax number (571) 270-2507. The examiner can normally be reached on 10AM to 4PM (EST), Monday to Friday. If attempts to reach the examiner by telephone are unsuccessful, the Examiner's Supervisor, JACK CHIANG can be reached on (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300./Mohammed Alam/Primary Examiner, Art Unit 2851