DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/13/23 and 3/20/25 is being considered by the examiner.
Claim Status
Claims 1-18 are pending and are examined. Claims 19 and 20 are cancelled.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 3-18 of U.S. Patent No. 11,656,197. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are broader than the issued claims. The instant claims encompass the entirety of the issued claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2-5, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Boyanov et al. (US Pub 2016/0017416; previously cited).
With regard to claim 1, Boyanov et al. teaches a solid state detection device comprising:
An array of conducting electrode pairs, each pair of electrodes comprising a source and a drain electrode arrangement separated by a nanogap, the electrode array deposited and patterned on a dielectric substrate (figure 1)[0030][0090];
At least one transition metal dichalcogenide (TMD) layer disposed on each pair of electrodes ([0096] teaches that their MoS2(a TMD) can be used in the sensor, wherein the TMD layer is capable of connecting each source and drain electrode within each pair (Figure 1), and bridges each nanogap of each pair of electrodes.
A dielectric masking layer disposed on the TMD layer and comprising opening that defines an exposed TMD region (Figure 1 and 8), wherein the opening is sized to receive a portion of a biomolecule therethrough ([0020][0091][0100][0101] Examiner notes the sizing is directed to intended use, and is relative in relation to the biomolecule which is not positively claimed as part of the device structure. For example, biomolecules may be different sizes and the opening would then have a variable size depending on the biomolecule). Boyanov et al. teach only one biomolecule (polymerase) attached to the exposed TMD region [0101](Figures 8 and 9) (attached directly via 3 (Figure1) and is capable of allowing only one enzyme to be present and be attached within the one opening.
With regard to claim 2, Boyanov teaches the detection device of claim 1, further comprising at least one biomolecule attached to the exposed TMD region (FIG. 1, polymerase 1 is immobilized on the gate 5 of a silicon nanowire field-effect transistor (FET) 2 with a tether 3.).
With regard to claim 3, Boyanov et al. teaches the detection device of claim 2, wherein the at least one biomolecule comprises a polymerase enzyme ([0013] Fig. 1 shows a polymerase attached to a charge sensor via a tether.).
With regard to claim 4, Boyanov teaches the detection device of claim 2, further comprising a microfluidic system in fluid combination with the sequencing device to provide the at least one biomolecule ([0027] The present disclosure provides a unique detection modality that can be used for nucleic acid sequencing and for detection of nucleic acids and other analytes in general. An exemplary embodiment is shown in FIG. 1.).
With regard to claim 5, Boyanov et al. teaches the detection device of claim 1, wherein at least one TMD layer comprises MoS2 (it is a TMD)[0096].
With regard to claim 13, Boyanov et al. teach the device of claim 1, wherein the nanogap is about 2nm to about 20 nm in length [0099] teaches a charge sensor having a 20nm diameter with a 10nm pinched area can be particularly useful.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Boyanov et al. in view of Khondaker et al. (2015/0294875; previously cited).
With regard to claim 6, Boyanov et al. discloses the device of claim 5, comprising altering a region so as to provide vacancy defects, interstitial defects, and aggregated defects so as to increase surface energy and enhance adhesion of the biomolecule (Para. [0090), useful charge devices include analytical devices that can incorporate a reaction component in direct spatial contact with a transduction element in a way to allow the rapid and convenient conversion of reaction events to detectable signals. Devices based on field-effect transistors (FETs) can directly translate interactions between reaction components (e.g., polymerases) and the transistor surface into readable electrical signals; (0094), In some embodiments a single reaction component can be attached to a charge sensor by creating one single covalent defect on the charge sensor. For example a SWNT can be produced having a single defect such that a variety of attachment chemistries can be used to link a single reaction component to the reactive defect site selectively).
Boyonov et al. fails to explicitly disclose wherein the sulfur stoichiometry is altered so as to provide vacancy defects, interstitial defects, and aggregated defects so as to increase surface energy of the exposed TMD region.
Khondaker et al. teaches a sulfur stoichiometry of an exposed TMD region is altered so as to provide vacancy defects, interstitial defects, and aggregated defects so as to increase the surface energy (Para. (0008), a MoS2 flake material is changed by plasma processing from a semiconductor to insulator (dielectric). Although the TMDC material is described herein as being MoS2 , the TMDC material can be other materials provided they are semiconductors and can be oxidized by disclosed plasma processing including oxygen to raise the resistivity of the material to that of an insulator. For example, the TMDC can also generally comprise MoSe2, WS2, WSe2, ln2Se3, or Ga Te; [0023), In one specific embodiment, MoS2 deposited unto a substrate is then exposed to an oxygen plasma treatment for different time duration ... while exposed to oxygen plasma, energetic oxygen molecules interact with MoS2 to create MoO3 rich defect regions which are insulating (dielectric). The area coverage of the defect region increases with increasing exposure time. This effect can be exploited in fabricating lateral TMDC-based FETs without the need to pattern the TMDC layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Boyonov et al. with the teaching of Khondaker et al. for the purpose of selectively modifying the electrical properties of a TMD surface as taught by Khondaker et al (Para. [0008), wherein a MoS2 flake material is changed by plasma processing from a semiconductor to insulator (dielectric); (0023], while exposed to oxygen plasma, energetic oxygen molecules interact with MoS2 to create MoO3 rich defect regions which are insulating (dielectric). The area coverage of the defect region increases with increasing exposure time. This effect can be exploited in fabricating lateral TMDC-based FETs without the need to pattern the TMDC layer).
With regard to Claim 14, Boyonov et al. discloses the device of claim 1.
Boyonov et al. fails to explicitly disclose wherein the TMD layer comprises a defective TMD layer.
Khondaker et al. teaches introducing oxygen atoms into a TMD layer to produce foreign atom implanted defects, thereby increasing the electrical resistance of the TMD layer (Para. [0008), a MoS2 flake material is changed by plasma processing from a semiconductor to insulator (dielectric). Although the TMDC material is described herein as being MoS2, the TMDC material can be other materials provided they are semiconductors and can be oxidized by disclosed plasma processing including oxygen to raise the resistivity of the material to that of an insulator. For example, the TMDC can also generally comprise MoSe2, WS2, WSe2, ln2Se3, or Ga Te; [0023), In one specific embodiment, MoS2 deposited unto a substrate is then exposed to an oxygen plasma treatment for different time duration ... while exposed to oxygen plasma, energetic oxygen molecules interact with MoS2 to create MoO3 rich defect regions which are insulating (dielectric). The area coverage of the defect region increases with increasing exposure time. This effect can be exploited in fabricating lateral TMDC-based FETs without the need to pattern the TMDC layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Boyonov et al. with the teaching of Khondaker et al for the purpose of selectively modifying the electrical properties of a TMD surface as taught by Khondaker (Para. [0008), a MoS2 flake material is changed by plasma processing from a semiconductor to insulator (dielectric); [0023), while exposed to oxygen plasma, energetic oxygen molecules interact with MoS2 to create MoO3 rich defect regions which are insulating (dielectric). The area coverage of the defect region increases with increasing exposure time. This effect can be exploited in fabricating lateral TMDC-based FETs without the need to pattern the TMDC layer).
Regarding Claim 15, modified Boyonov et al. discloses the device of claim 14. Boyonov et al. fail to explicitly disclose wherein the defective TMD layer comprises a linear nano-ribbon parallel array, a patterned shape nano-ribbon array, strained lattice defects, vacancies, interstitial defects, dislocation defects, foreign atom implanted defects, or nanoporous defects.
Khondaker et al teaches introducing oxygen atoms into a TMD layer to produce foreign atom implanted defects, thereby increasing the electrical resistance of the TMD layer (Para. [0008). a MoS2 flake material is changed by plasma processing from a semiconductor to insulator (dielectric). Although the TMDC material is described herein as being MoS2 , the TMDC material can be other materials provided they are semiconductors and can be oxidized by disclosed plasma processing including oxygen to raise the resistivity of the material to that of an insulator. For example, the TMDC can also generally comprise MoSe2, WS2, WSe2 , ln2Se3, or Ga Te; [0023), In one specific embodiment, MoS2 deposited unto a substrate is then exposed to an oxygen plasma treatment for different time duration ... while exposed to oxygen plasma, energetic oxygen molecules interact with MoS2 to create MoO3 rich defect regions which are insulating (dielectric). The area coverage of the defect region increases with increasing exposure time. This effect can be exploited in fabricating lateral TMDC-based FETs without the need to pattern the TMDC layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Boyonov et al. with the teaching of Khondaker et al. for the purpose of selectively modifying the electrical properties of a TMD surface as taught by Florida (Para. [0008), a MoS2 flake material is changed by plasma processing from a semiconductor to insulator (dielectric); [0023), while exposed to oxygen plasma, energetic oxygen molecules interact with MoS2 to create MoO3 rich defect regions which are insulating (dielectric). The area coverage of the defect region increases with increasing exposure time. This effect can be exploited in fabricating lateral TM DC-based FETs without the need to pattern the TMDC layer).
Regarding Claim 16, modified Boyonov et al. discloses the device of claim 14, Khondaker et al. further discloses features at a density of at least about 10"5/cm2 (Para. [0097), nucleotides can be delivered via bulk solution to an array of wells (or other features), each well (or other feature) hosting an individual sequencing reaction. The nucleotide delivery will result in parallel sequencing reactions at the wells (or other features); [0104). The density of an array can be from 2 to as many as a billion or more different reaction sites per square cm. Very high density arrays are useful in the invention including, for example, those having at least about 10,000,000 reaction sites/cm2).
Boyonov et al. fail to explicitly disclose wherein the defective TMD layer comprises strained lattice defects, vacancies, interstitial defects, dislocation defects or foreign atom implanted defects with a defect density of at least about 105/cm2.
Khondaker et al. teaches introducing oxygen atoms into a TMD layer to produce foreign atom implanted defects, thereby increasing the electrical resistance of the TMD layer, wherein a defect density of at least about 10"5/cm 2 may be obtained by increasing the plasma exposure time (Para. [0008), a MoS2 flake material is changed by plasma processing from a semiconductor to insulator (dielectric). Although the TMDC material is described herein as being MoS2, the TMDC material can be other materials provided they are semiconductors and can be oxidized by disclosed plasma processing including oxygen to raise the resistivity of the material to that of an insulator. For example, the TMDC can also generally comprise MoSe2, WS2 , WSe2 , ln2Se3 , or Ga Te; [0023), In one specific embodiment, MoS2 deposited unto a substrate is then exposed to an oxygen plasma treatment for different time duration ... while exposed to oxygen plasma, energetic oxygen molecules interact with MoS2 to create MoO3 rich defect regions which are insulating (dielectric). The area coverage of the defect region increases with increasing exposure time. This effect can be exploited in fabricating lateral TMDC-based FETs without the need to pattern the TMDC layer; [0034), The drain current was -285 nA for the as fabricated sample, which decreased exponentially with time to value of less than 20 pA, a drop of more than four orders of magnitude, after only a total of 6 s plasma exposure time. After a 6 s exposure, the current become negligibly small. The rapid drop of current with oxygen plasma exposure evidences electrons are getting trapped in defect regions of the MoS2 and the trapped states are increasing with increasing plasma exposure; Fig. 6A, indicating overlapping defects, which would be a very high density).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Boyonov et al. with the teaching of Khondaker et al for the purpose of selectively modifying the electrical properties of a TMD surface as taught by Khondaker et al (Para. [0008), a MoS2 flake material is changed by plasma processing from a semiconductor to insulator (dielectric); [0023), while exposed to oxygen plasma, energetic oxygen molecules interact with MoS2 to create MoO3 rich defect regions which are insulating (dielectric). The area coverage of the defect region increases with increasing exposure time. This effect can be exploited in fabricating lateral TM DC-based FETs without the need to pattern the TMDC layer).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Boyanov et al., in view of Yu et al. (US Pub 2016/0284811; previously cited).
Regarding Claim 7, Boyonov et al. discloses the device of claim 1. Boyonov et al. fail to explicitly disclose wherein the at least one TMD layer comprises MoSe2, WSe2, TiSe2, ZrSe2, HfSe2, VSe2, NbSe2, TaSe2, TcSe2, ReSe2, COSe2, RhSe2, lrSe2 NiSe2, PdSe2, PtSe2, or any of their modifications or combinations, including modified stoichiometry of selenium contents having MX(2 -x) or MX(2+x), wherein x is in the range of O 1.0.
Yu et al. teaches a TMD layer comprises MoSe2, WSe2, TiSe 2, or ZrSe2, wherein x is in the range of O - 1.0 (Para. (0087], the semiconductor material layer 202 can include one or more transition metal dichalcogenides (TMDCs). The TMDC can be expressed as MX2, where M is a transition metal (such as but not limited to molybdenum (Mo), tungsten (W), titanium (Ti), tin (Sn), and zirconium), and Xis a chalcogen (such as but not limited to sulfur (S) and selenium (Se)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Boyonov et al. with the teaching of Yu for the purpose of tuning the electronic properties of the device as taught by Yu et al. (Para. (0006], A graphene-based material can be configured according to the principles described herein such that the Schottky barrier height between the graphene-based material and many different types of semiconductor material is reduced, including being reduced to a minimum. This provides significantly greater flexibility in the fabrication of electronic devices, since it simplifies the type of materials used as the contact and/or interconnect in the electronic devices).
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Boyanov et al. in view of Yu et al. (US Pub 2016/0284811) and further view of Khondaker et al. (US Pub 2015/0294875; previously cited).
Regarding claim 8, Boyanov et al. in view of Yu et al. discloses the device of claim 7, comprising intentionally altering a region so as to provide vacancy defects. Interstitial defects and aggregated defects so as to increase surface energy and enhance adhesion of lht1 biomolecule (Para. [0090), Useful charge devices include analytical devices that can incorporate a reaction component in direct spatial contact with a transduction element in a way to allow the rapid and convenient conversion of reaction events to detectable signals. Devices based on field-effect transistors (FETs) can directly translate interactions between reaction components (e.g., polymerases) and the transistor surface into readable electrical signals; [0094), In some embodiments a single reaction component can be attached to a charge sensor by creating one single covalent defect on the charge sensor. For example a SWNT can be produced having a single defect such that a variety of attachment chemistries can be used to link a single reaction component to the reactive defect site selectively).
Boyanov et al. fails to explicitly disclose wherein the selenium stoichiometry is intentionally altered so as to provide vacancy defects, interstitial defects, and aggregated defects in order to increase surface energy of the TMD layer.
Khondaker et al. (2015/0294875) teaches wherein the sulfur or selenium stoichiometry of an exposed TMD region is intentionally altered so as to provide vacancy defects, interstitial defects, and aggregated defects so as to increase the surface energy (Para. [0008), a MoS2 flake material is changed by plasma processing from a semiconductor to insulator (dielectric). Although the TMDC material is described herein as being MoS2, the TMDC material can be other materials provided they are semiconductors and can be oxidized by disclosed plasma processing including oxygen to raise the resistivity of the material to that of an insulator. For example, the TMDC can also generally comprise MoSe2, WS2 , WSe2 , ln2Se3 , or Ga Te; [0023). In one specific embodiment, MoS2 deposited unto a substrate is then exposed to an oxygen plasma treatment for different time duration ... while exposed to oxygen plasma, energetic oxygen molecules interact with MoS2 to create MoO3 rich defect regions which are insulating (dielectric). The area coverage of the defect region increases with increasing exposure time. This effect can be exploited in fabricating lateral TM DC-based FETs without the need to pattern the TMDC layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Boyanov et al. and Yu with the teaching of Khondaker et al. (2015/0294875) for the purpose of selectively modifying the electrical properties of a TMD surface as taught by Khondaker et al. (2015/0294875 (Para. [0008), a MoS2 flake material is changed by plasma processing from a semiconductor to insulator (dielectric); [0023]), while exposed to oxygen plasma, energetic oxygen molecules interact with MoS2 to create MoO3 rich defect regions which are insulating (dielectric). The area coverage of the defect region increases with increasing exposure time. This effect can be exploited in fabricating lateral TMDC-based FETs without the need to pattern the TMDC layer).
Regarding Claim 10, modified Boyanov et al. discloses the device of claim 9, comprising intentionally altering a region so as to provide vacancy defects, interstitial defects, and aggregated defects so as to increase surface energy and enhance adhesion of the biomolecule (Para. (0090], Useful charge devices include analytical devices that can incorporate a reaction component in direct spatial contact with a transduction element in a way to allow the rapid and convenient conversion of reaction events to detectable signals. Devices based on field-effect transistors (FETs) can directly translate interactions between reaction components (e.g., polymerases) and the transistor surface into readable electrical signals; (0094], In some embodiments a single reaction component can be attached to a charge sensor by creating one single covalent defect on the charge sensor ... For example a SWNT can be produced having a single defect such that a variety of attachment chemistries can be used to link a single reaction component to the reactive defect site selectively).
Boyanov et al. fails to explicitly disclose wherein the tellurium stoichiometry is intentionally altered so as to provide vacancy defects, interstitial defects, and aggregated defects in order to increase surface energy of the TMD layer.
Khondaker et al. teaches stoichiometry of an exposed TMD region, such as a TMD region comprising Tellurium, is intentionally altered so as to provide vacancy defects, interstitial defects, and aggregated defects so as to increase the surface energy (Para. [0008], a MoS2 flake material is changed by plasma processing from a semiconductor to insulator (dielectric). Although the TMDC material is described herein as being MoS2, the TMDC material can be other materials provided they are semiconductors and can be oxidized by disclosed plasma processing including oxygen to raise the resistivity of the material to that of an insulator. For example, the TMDC can also generally comprise MoSe2, WS2 , WSe2, ln2Se3 , or GaTe; (0023], In one specific embodiment, MoS2 deposited onto a substrate is then exposed to an oxygen plasma treatment for different time duration ... while exposed to oxygen plasma, energetic oxygen molecules interact with MoS2 to create Mo03 rich defect regions which are insulating (dielectric). The area coverage of the defect region increases with increasing exposure time. This effect can be exploited in fabricating lateral TMDC-based FETs without the need to pattern the TMDC layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Boyanov et al. with the teaching of for the purpose of selectively modifying the electrical properties of a TMD surface as taught by Khondaker et al (Para. [0008], a MoS2 flake material is changed by plasma processing from a semiconductor to insulator (dielectric); (0023], while exposed to oxygen plasma, energetic oxygen molecules interact with MoS2 to create Mo03 rich defect regions which are insulating (dielectric). The area coverage of the defect region increases with increasing exposure time. This effect can be exploited in fabricating lateral TM DC-based
FETs without the need to pattern the TMDC layer).
Claims 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Boyanov et al., in view of Quick et al. (US Pub 2014/0027775; previously cited).
Regarding Claim 9, Boyanov et al. discloses the device of claim 1.
Boyanov et al. fails to explicitly disclose wherein the at least one TMD layer comprises MoTe2, WTe2, TiTe2, ZrTe2, HfTe2, VTe2, NbTe2, TaTe2, TcTe2, ReTe2, CoTe2, RhTe2 lrTe2, NiTe2, PdTe2, PtTe2, or any of their modifications or combinations, including modified stoichiometry of tellurium contents having MX(2-x) or MX( 2 +x), wherein x is in the range of 0-1.0.
Quake et al. teaches a TMD layer comprises MoTe2, WTe2, TiTe2, ZrTe2, HfTe2, VTe2, NbTe2, TaTe2, TcTe2, ReTe2, CoTe2, RhTe2 lrTe2, NiTe2, PdTe2, PtTe2, or any of their modifications or combinations, including modified stoichiometry of tellurium contents having MX(2-x) or MX( 2 +x), wherein x is in the range of 0-1.0 (Para. [0014), the metal chalcogenide material 104 may be formed of and include zirconium telluride (ZrTex), copper telluride (CuTex), silver telluride (AgTex), gold telluride (AuTex), zinc telluride (Zn Tex), aluminum telluride (AITex), gallium telluride (GaTex), indium telluride (lnTex), tin telluride (SnTex), bismuth telluride (BiTex), germanium telluride (GeTex), arsenic telluride (ArTex), antimony telluride (SbTex) ... Formulae including "x" above (e.g., ZrTex, CuTex, AgTex, AuTex, Zn Tex, etc.) represent a composition that on average contains x atoms of chalcogen for every one atom of the metal component. As the formulae are representative of relative atomic ratios and not strict chemical formula, the metal chalcogenide material 104 may be stoichiometric or non-stoichiometric, and values of x may be integer or may be non-integer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Boyanov et al. with the teaching of Quake et al. for the purpose of providing a TMD of high purity suitable for semiconductor electronic devices as taught by Quake et al. (Para. [0002). Over the past few decades, there has been interest in chalcogenide materials for use in semiconductor devices, such as non-volatile memories, solar cells, photodetectors, or electroconductive electrodes; [0004), It would be desirable to be able to form additional chalcogenide materials using ALD processes. It would be further desirable if chalcogenide materials formed using the ALD processes exhibited high purity).
Regarding Claim 11, Boyanov et al. discloses the device of claim 1. Boyanov et al. fails to explicitly disclose wherein the TMD layer comprises MoxWy(O2)S2 or (HfxWyCoz)Te2.
Quake et al. teaches a TMD layer comprises MoxWy(O2)S2 or (HfxWyCoz)Te2 (Para. (0015], While the metal chalcogenide material 104 is described above as including at least one binary compound, the metal chalcogenide material 104 may also be formed of and include at least one multinary compound, such as a ternary compound or a quaternary compound. If metal chalcogenide material 104 includes a multinary compound, the metal chalcogenide material 104 may include at least one additional element, such as another alkali metal, alkaline earth metal, transition metal, post-transition metal, or metalloid. The additional element may include, but is not limited to, titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), manganese (Mn), iron (Fe), cobalt (Co); (0020], The chalcogen precursor may be a hydride compound of the chalcogen, an alkyl compound of the chalcogen, or an aryl compound of the chalcogen, such as an alkyl compound of tellurium (Te), selenium (Se), or sulfur (S )).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Boyanov et al. with the teaching of for the purpose of obtaining a TMD with a desired property, such as crystallinity, as taught by Quake et al. (Para. (0015]. The additional element(s) may affect the properties of the metal chalcogenide material 104, such as the ability to form the metal chalcogenide
material 104 in a crystalline form or an amorphous form. The additional element(s) may be selected to be compatible with the chalcogen and the metal during the ALD process. In additional embodiments, the metal chalcogenide material 104 may be formed of a mixture of at least one binary compound and at least one multinary compound).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Boyanov et al., in view of Su et al. (US Pub 2009/0170716; previously cited).
Regarding Claim 12, Boyanov et al. discloses the device of claim 1.
Boyanov et al. fails to explicitly disclose wherein the array of conducting electrode pairs comprise at least one of Au, Pt, Ag, Pd, Rh, or their alloys.
Su et al. teaches microelectronic sequencing devices comprising an array of conducting electrode pairs comprising at least one of Au, Pt, Ag, or Pd, (Abstract, Methods for sequencing nucleic acids are presented. Sequencing is accomplished through the detection of a redox active species that is indicative of nucleotide incorporation. In embodiments of the invention, an electrochemical signal indicative of nucleotide incorporation is amplified through cycling before it is detected. Arrays are provided that are capable of massively parallel nucleic acid sequence determination; (0029], The electrodes 16 and 18 are comprised of electroactive materials. Such as, for example, carbon, nickel, tungsten, aluminum, platinum, palladium, indium tin oxide, or gold).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Boyanov et al. with the teaching of Su for the purpose of using an electrode material appropriate for detection as taught by Su (Para. (0019], Incorporation of a NMP into the complementary DNA strand 24 is detected through the detection of a redox species indicative of the products of the incorporation
reaction. More specifically, a current flow is detected at a Voltage indicative of the oxidation/reduction reaction specific to a product of the incorporation reaction.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Boyanov et al., in view of Khondaker et al. (US Pub 2015/0294875) and Liu et al. (ACS Nano, 18 Feb 2014, Vol. 8 Pgs 2504-2511; previously cited).
Regarding Claim 17, modified Boyanov et al. in view of Khondaker et al. discloses the device of claim 14, comprising porous features at a density of at least about 103/cm2 (Para. (0097], nucleotides can be delivered via bulk solution to an array of wells (or other features), each well (or other feature) hosting an individual sequencing reaction. The nucleotide delivery will result in parallel sequencing reactions at the wells (or other features); (0104], The density of an array can be from 2 to as many as a billion or more different reaction sites per square cm. Very high density arrays are useful in the invention including, for example, those having at least about 10,000,000 reaction sites/cm2).
Boyanov et al. fails to explicitly disclose wherein the defective TMD layer comprises nanoporous defects having an equivalent diameter of at least 2 nm.
Liu teaches a nanoporous TMD layer for DNA sequencing comprising nanoporous defects (pores) having an equivalent diameter of at least 2 nm (Abstract, Atomically thin nanopore membranes are considered to be a promising approach to achieve single base resolution with the ultimate aim of rapid and cheap DNA sequencing ... Nanopores in MoS2 are further sculpted with variable sizes using a
transmission electron microscope (TEM) to drill through suspended portions of the MoS2 membrane. Various types of double-stranded (ds) DNA with different lengths and conformations are translocated through such a novel architecture, showing improved sensitivity (signal-to-noise ratio >10) compared to the conventional silicon nitride (SiNx) nanopores; Pg. E Col. 1, Para. 1, To gain more understanding on the interaction between MoS2 and DNA, we translocated pNEB DNA through a 5 nm diameter MoS2 pore ... both mean current amplitude and mean dwell time are larger for the 5 nm pore compared to the 20 nm pore, implying a local interaction between the edge of the MoS2 pore and the DNA molecule. To extend this statement, this interaction happens only when DNA is sliding through the edge of pore with the effect of retarding DNA translocation. For larger pores (20 nm), translocations tend to occur in a frictionless manner).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Boyanov and Khondaker et al. with the teaching of Liu for the purpose of using a pore size that can achieve single base resolution of DNA as taught by Liu (Abstract, Atomically thin nanopore membranes are considered to be a promising approach to achieve single base resolution with the ultimate aim of rapid and cheap DNA sequencing).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Boyanov et al., in view of Khondaker et al. (US Pub 2015/0294875) and further view of ECOLE POL YTECHNIQUE FEDERALE DE LAUSANNE (EPFL)(hereinafter EPFL; previously cited).
Regarding Claim 18, modified Boyanov et al. in view of Khondaker et al. discloses the device of claim 14.
Boyanov et al. fails to explicitly disclose wherein the defective TMD layer has a bandgap opened to a value of at least 0.2 eV.
EPFL teaches a TMD layer has a bandgap opened to a value of at least 0.2 eV (Para. (0008], The invention concerns a semiconductor device comprising a source electrode, a drain electrode and a semiconducting layer consisting of a single or double 2-dimensional layer(s) made from one of the following materials: MoS2, MoSe2, WS2, WSe2, MoTe2, or WTe2; (0010], Replacing a stack by only one or two 2-dimensional layers of MoS2, MoSe2, WS2, or WSe2, MoTe2, WTe2 provides an enhanced electrostatic control, low power dissipation, direct band gap and tunability. It was shown in Example 1 that a transistor based on a single layer of MoS2 has a room-temperature on/off ratio of 10h8 and an off-state current of 25fA/μm; (0046], Two-dimensional materials are attractive for use in next-generation nanoelectronic devices because, compared to one-dimensional materials, it is relatively easy to fabricate complex structures from them ... single layers of MoS2 have a large intrinsic bandgap of 1.8 eV; (0047], Large-area thin films can also be prepared using MoS2 suspensions. Bulk MoS2 is semiconducting with an indirect band gap of 1.2 eV, while single-layer MoS2 is a direct gap semiconductor with a band gap of 1.8 eV).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Boyanov et al. with the teaching of EPFL for the purpose of providing a tunable band gap as taught by EPFL (Para. (0010], Using a double 2-dimensional layer retains the advantage of a thin material with the additional benefit that the band gap can be tuned with the application of the external electric field).
Response to Arguments
Applicant’s arguments, see page 5, filed 10/21/25, with respect to the claim objection have been fully considered and are persuasive. The claim objection has been withdrawn.
Applicant's arguments filed 10/21/25 regarding the 103 rejection have been fully considered but they are not persuasive.
First, Applicant argues on the bottom of page 5 and top of page 6 that claim 1 is amended to recite “an opening… sized to receive a portion of one and only biomolecule therethrough”. As noted on page 7 in paragraph 3, that Applicant disagrees that the sizing is directed to intended use.
In response, the examiner notes that the claim language in in the 3rd clause of claim 1, “the opening is sized to receive a portion of one and only one biomolecule therethrough” is not a specific size since the size of a biomolecule has a wide range. This size is not limiting to a specific measurement. Therefore, the rejection is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACQUELINE BRAZIN whose telephone number is (571)270-1457. The examiner can normally be reached M-F 8-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Charles Capozzi can be reached at 571-270-3638. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JB/
/CHARLES CAPOZZI/Supervisory Patent Examiner, Art Unit 1798