Prosecution Insights
Last updated: May 29, 2026
Application No. 18/134,612

COMPUTER POWER CONSUMPTION MANAGEMENT BASED ON THE STATE OF THE POWER SUPPLYING ELECTRICAL GRID

Non-Final OA §103
Filed
Apr 14, 2023
Priority
Apr 27, 2022 — EU 22170182.4
Examiner
YEN, PAUL JUEI-FU
Art Unit
2175
Tech Center
2100 — Computer Architecture & Software
Assignee
Dc Systems B V
OA Round
3 (Non-Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
315 granted / 411 resolved
+21.6% vs TC avg
Strong +22% interview lift
Without
With
+22.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
21 currently pending
Career history
440
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
86.6%
+46.6% vs TC avg
§102
4.1%
-35.9% vs TC avg
§112
5.3%
-34.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 411 resolved cases

Office Action

§103
DETAILED ACTION Response to Amendment Applicant’s amendment, filed 12/18/25, for application number 18/134,612 has been received and entered into record. Claims 1, 3-5, and 7-11 have been amended, Claims 2, 6, and 12 are cancelled, and Claims 13-23 are newly added. Therefore, Claims 1, 3-5, 7-11, and 13-23 are presented for examination. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Allowable Subject Matter Claims 13, 14, and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1, 11, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Sok et al., US 11,126,255 B1, in view of Saba, US 2012/0297215 A1. Regarding Claim 1, Sok discloses a method of adapting the electrical power consumption of a digital electronic computer to an instantaneous electrical power available from a power bus [use of the busbar in combination with power supply units on a power shelf unit may provide a convenient and reliable source of DC power to devices of the cloud computing system, col. 3, ll. 11-14], the method comprising: measuring an instantaneous electrical frequency on the power bus in case of the power bus being an alternating current (AC) power bus providing AC electrical power at an electrical frequency, or an instantaneous electrical voltage on the power bus in case of the power bus being a (DC) power bus providing DC electrical power at an electrical voltage to obtain a power supply measurement indicative of an instantaneous level of power supply from the power bus [detecting a change in voltage of a DC power supply signal on a busbar coupled to the server device, col. 16, ll. 15-23]. However, Sok does not explicitly teach throttling, based at least in part on the obtained power supply measurement falling below a first throttling threshold, a first one or more tasks executed by a processing unit of the digital electronic computer by allocating fewer resources of the processing unit to the first one or more tasks to reduce power consumption by the processing unit while performing the first one or more tasks, wherein each of the first one or more tasks has a first priority: and throttling, based at least in part on the obtained power supply measurement falling below a second throttling threshold, a second one or more tasks executed by the processing unit of the digital electronic computer by allocating fewer resources of the processing unit to the second one or more tasks to reduce power consumption by the processing unit while performing the second one or more tasks, wherein each of the second one or more tasks has a lower priority than each of the first one or more tasks, and wherein the first throttling threshold is less than the second throttling threshold. In the analogous art of power conservation, Saba teaches throttling, based at least in part on the obtained power supply measurement falling below a first throttling threshold, a first one or more tasks executed by a processing unit of the digital electronic computer by allocating fewer resources of the processing unit to the first one or more tasks to reduce power consumption by the processing unit while performing the first one or more tasks, wherein each of the first one or more tasks has a first priority: and throttling, based at least in part on the obtained power supply measurement falling below a second throttling threshold, a second one or more tasks executed by the processing unit of the digital electronic computer by allocating fewer resources of the processing unit to the second one or more tasks to reduce power consumption by the processing unit while performing the second one or more tasks, wherein each of the second one or more tasks has a lower priority than each of the first one or more tasks, and wherein the first throttling threshold is less than the second throttling threshold [when the power drops below a certain level, the icons which start or open high power consumption applications such as a GPS, camera and/or a browser application may be modified so that they are rendered in gray-scale while the remaining applications appear in color; the power threshold levels and the order in which application icons are modified to discourage their use may be established by default or they may be established by the user…When the power falls below an even lower second threshold level, icons for applications such as email and browser applications may be modified; that is, the icons are throttled in an established order, i.e. priority, par 28, 31]. It would have been obvious to one of ordinary skill in the art, having the teachings of Sok and Saba before him before the effective filing date of the claimed invention, to incorporate the throttling as taught by Saba into the method as disclosed by Sok, to ensure extended use of electronic devices such as laptops while on battery power [Saba, par 1]. Regarding Claim 11, Sok discloses a method of managing power consumption in a data center that includes a plurality of computing servers and a power bus supplying electrical power to the computing servers [server rack 202 containing server devices 210a-210n; power shelf unit 206 contains power management control system 214, Fig. 2]. The remainder of Claim 11 recites limitations similar to those of Claim 1, and is rejected accordingly. Regarding Claim 15, Sok discloses a digital electronic computer comprising: at least one processor configured to cause the digital electronic computer [power management control system 314 contains alert manager 316, which has processor unit, Fig. 3, 4A], to adapt an electrical power consumption of the digital electronic computer to an instantaneous electrical power available from a power bus [detecting a change in voltage of a DC power supply signal on a busbar coupled to the server device, col. 16, ll. 15-23]. The remainder of Claim 15 recites limitations similar to those of Claim 1, and is rejected accordingly. Claims 3 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Sok and Saba, and further in view of Thacher et al., US 6,745,117 B1. Regarding Claim 3, Sok and Saba disclose the method according to Claim 1. Saba further teaches throttling the first one or more tasks comprises reducing allocation of resources of the processing unit to the first one or more tasks and throttling the second one or more tasks comprises reducing allocation of resources of the processing unit to the second one or more tasks [when the power drops below a certain level, the icons which start or open high power consumption applications such as a GPS, camera and/or a browser application may be modified so that they are rendered in gray-scale while the remaining applications appear in color; the power threshold levels and the order in which application icons are modified to discourage their use may be established by default or they may be established by the user…When the power falls below an even lower second threshold level, icons for applications such as email and browser applications may be modified; that is, the icons are throttled in an established order, i.e. priority, par 28, 31]. However, the combination of references does not explicitly teach reducing allocation of resources increasing linearly as the power supply measurement continues to decrease. In the analogous art of power management in a power-limiting environment, Thacher teaches reducing allocation of resources increasing linearly as the power supply measurement continues to decrease [allocation of power (i.e. resources) to the non-critical loads is decreased in conformance with a generally linear mathematical function between maximum allowable power draw versus time; i.e. less resources are allocated in a linear fashion as maximum power allowable (available) decreases over time, Fig. 6A; col. 4, ll. 60-63]. It would have been obvious to one of ordinary skill in the art, having the teachings of Sok, Saba, and Thacher before him before the effective filing date of the claimed invention, to incorporate the power allocation as taught by Thacher into the method as disclosed by Sok and Saba, to manage power consumption to enhance the longevity of powered devices [Thacher, col. 1, ll. 29-37]. Regarding Claim 16, Sok and Saba disclose the digital electronic computer according to Claim 15. Claim 16 recites limitations similar to those of Claim 3, and is rejected accordingly. Claims 4, 9, 17, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Sok and Saba, and further in view of Glen, US 2011/0268425 A1. Regarding Claim 4, Sok and Saba disclose the method according to Claim 1. However, while Saba teaches throttling the first one or more tasks comprises reducing allocation of resources of the processing unit to the first one or more tasks and throttling the second one or more tasks comprises reducing allocation of resources of the processing unit to the second one or more tasks [when the power drops below a certain level, the icons which start or open high power consumption applications such as a GPS, camera and/or a browser application may be modified so that they are rendered in gray-scale while the remaining applications appear in color; the power threshold levels and the order in which application icons are modified to discourage their use may be established by default or they may be established by the user…When the power falls below an even lower second threshold level, icons for applications such as email and browser applications may be modified; that is, the icons are throttled in an established order, i.e. priority, par 28, 31], the combination of references does not explicitly teach ending, based at least in part on the obtained power supply measurement falling below a first ending threshold; and ending, based at least in part on the obtained power supply measurement falling below a second ending threshold, the second one or more tasks, wherein the second ending threshold is less than the first ending threshold are ended. In the analogous art of power management, Glen teaches ending, based at least in part on the obtained power supply measurement falling below a first ending threshold; and ending, based at least in part on the obtained power supply measurement falling below a second ending threshold, the second one or more tasks, wherein the second ending threshold is less than the first ending threshold are ended [device 100 may enter into a reduced power consumption mode when the power source is below a threshold level; if below a second threshold, then only main video frame is displayed; i.e. less of the processing unit’s resources are allocated to the display task, par 64, ll. 5-15; par 66, ll. 3-5]. It would have been obvious to one of ordinary skill in the art, having the teachings of Sok, Saba, and Glen before him before the effective filing date of the claimed invention, to incorporate the power reduction method as taught by Glen into the method as disclosed by Sok and Saba, to achieve power reduction through reduction of tasks and associated resources rather that lowering frequency clock signals [Glen, par 6]. Regarding Claim 9, Sok and Saba disclose the method according to Claim 1. While Saba further teaches throttling the first one or more tasks comprises reducing allocation of resources of the processing unit to the first one or more tasks and throttling the second one or more tasks comprises reducing allocation of resources of the processing unit to the second one or more tasks [when the power drops below a certain level, the icons which start or open high power consumption applications such as a GPS, camera and/or a browser application may be modified so that they are rendered in gray-scale while the remaining applications appear in color; the power threshold levels and the order in which application icons are modified to discourage their use may be established by default or they may be established by the user…When the power falls below an even lower second threshold level, icons for applications such as email and browser applications may be modified; that is, the icons are throttled in an established order, i.e. priority, par 28, 31], the combination of references does not explicitly teach wherein the digital electronic computer includes a task manager for managing computing tasks, and wherein a second task is at least partly performed by the task manager. In the analogous art of power management, Glen teaches wherein the digital electronic computer includes a task manager for managing computing tasks, and wherein a second task at least partly performed by the task manager [device 100 may enter into a reduced power consumption mode when the power source is below a threshold level; if below a second threshold, then only main video frame is displayed; i.e. device 100 containing a program (i.e. task manager) which manages computing tasks according to power consumption mode, par 64, ll. 5-15; par 66, ll. 3-5]. It would have been obvious to one of ordinary skill in the art, having the teachings of Sok, Saba, and Glen before him before the effective filing date of the claimed invention, to incorporate the power reduction method as taught by Glen into the method as disclosed by Sok and Saba, to achieve power reduction through reduction of tasks and associated resources rather that lowering frequency clock signals [Glen, par 6]. Regarding Claims 17 and 21, Sok and Saba disclose the digital electronic computer according to Claim 15. Claims 17 and 21 recite limitations similar to those of Claim 4 and 9, respectively, and are rejected accordingly. Claims 5 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Sok and Saba, and further in view of Berry et al., US 2008/0168287 A1. Regarding Claim 5, Sok and Saba disclose the method according to Claim 1. Sok discloses obtaining a power supply measurement [detecting a change in voltage of a DC power supply signal on a busbar coupled to the server device, col. 16, ll. 15-23] and Saba further teaches throttling the first one or more tasks comprises reducing allocation of resources of the processing unit to the first one or more tasks and throttling the second one or more tasks comprises reducing allocation of resources of the processing unit to the second one or more tasks [when the power drops below a certain level, the icons which start or open high power consumption applications such as a GPS, camera and/or a browser application may be modified so that they are rendered in gray-scale while the remaining applications appear in color; the power threshold levels and the order in which application icons are modified to discourage their use may be established by default or they may be established by the user…When the power falls below an even lower second threshold level, icons for applications such as email and browser applications may be modified; that is, the icons are throttled in an established order, i.e. priority, par 28, 31]. However, the combination of references does not explicitly teach deriving, from the obtained power supply measurement, a power supply level indicator that indicates the instantaneous level of the power supply from the power bus. In the analogous art of power management, Berry teaches deriving, from the obtained power supply measurement, a power supply level indicator that indicates the instantaneous level of the power supply from the power bus [determining instantaneous power processor draws from instantaneous voltage and current values to be used in power throttled mode, Fig. 2; par 30, ll. 1-3]. It would have been obvious to one of ordinary skill in the art, having the teachings of Sok, Saba, and Berry before him before the effective filing date of the claimed invention, to incorporate the determination of power supply as taught by Berry into the method as disclosed by Sok and Saba, to avoid increase of system costs associated with use of artificial maximum power workload limits which decrease processor yield or require systems to provide more power [Berry, par 3, ll. 13-17]. Regarding Claim 18, Sok and Saba disclose the digital electronic computer according to Claim 15. Claim 18 recites limitations similar to those of Claim 5, and is rejected accordingly. Claims 7 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sok, Saba, and Berry, and further in view of Thacher. Regarding Claims 7 and 19, Sok, Saba, and Berry disclose the method according to Claim 5 and the digital electronic computer according to Claim 18. Claims 7 and 19 recite limitations similar to those of Claim 3, and are rejected accordingly. Claims 8 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sok, Saba, and Berry, and further in view of Glen. Regarding Claims 8 and 20, Sok, Saba, and Berry disclose the method according to Claim 5 and the digital electronic computer according to Claim 18. Claims 8 and 20 recite limitations similar to those of Claim 4, and are rejected accordingly. Claims 10 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Sok and Saba, and further in view of Soverns et al., US 10,903,761 B2. Regarding Claim 10, Sok and Saba disclose the method according to Claim 1. Sok furter discloses measuring the instantaneous electrical voltage on the DC power bus [detecting a change in voltage of a DC power supply signal on a busbar coupled to the server device, col. 16, ll. 15-23]. However, the combination of references does not explicitly teach wherein: the power bus is the DC power bus; a power supply chain of the digital electronic computer includes a DC power supply unit, an input side of the DC power supply unit being electrically connected to the DC power bus; a voltage sensor is arranged at the input side of the DC power supply unit; and the voltage sensor is adapted for carrying out measurement of power supply level from the power bus. In the analogous art of power source management, Soverns teaches wherein: the power bus is the DC power bus [DC Link voltage 106 is a bus that is configured to connect any number of devices together, col. 3, ll. 8-10]; a power supply chain of the digital electronic computer includes a DC power supply unit, an input side of the DC power supply unit being electrically connected to the DC power bus [DC source 1 102 providing power to DC to DC converter 104 (DC power supply), which is connected to DC link 106, Fig. 1]; a voltage sensor is arranged at the input side of the DC power supply unit; and the voltage sensor is adapted for carrying out measurement of power supply level from the power bus [control system 110 reads the voltage of power source 103 and determines if power source 103 can provide power to microgrid 100, col. 3, ll. 33-35]. It would have been obvious to one of ordinary skill in the art, having the teachings of Sok, Saba, and Soverns before him before the effective filing date of the claimed invention, to incorporate the determination of voltage as taught by Soverns into the method as disclosed by Sok and Saba, to determine whether there is sufficient power for the system and take corrective actions when there is not [Soverns, col. 1, ll. 23-38]. Regarding Claim 22, Sok and Saba disclose the digital electronic computer according to Claim 15. Claim 22 recites limitations similar to those of Claim 10, and is rejected accordingly. Response to Arguments Applicant’s arguments filed 12/18/25 have been considered but are moot due to the new rejection based on the references cited above, as well as the newly cited portions of the references previously presented. Conclusion Applicant is reminded that in amending a response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR §1.111(c). Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL J YEN whose telephone number is (571)270-5047. The examiner can normally be reached M-F 8-5 PT. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Paul Yen/Primary Examiner, Art Unit 2175
Read full office action

Prosecution Timeline

Show 1 earlier event
Apr 24, 2025
Non-Final Rejection mailed — §103
Jul 24, 2025
Response Filed
Aug 06, 2025
Final Rejection mailed — §103
Dec 11, 2025
Examiner Interview Summary
Dec 11, 2025
Applicant Interview (Telephonic)
Dec 18, 2025
Request for Continued Examination
Jan 06, 2026
Response after Non-Final Action
May 06, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
99%
With Interview (+22.1%)
3y 0m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 411 resolved cases by this examiner. Grant probability derived from career allowance rate.

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