DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 2-8 and 10-21 are pending. Claims 2, 10-13, and 16 have been amended as per Applicants' request. Claims 9 have been canceled as per Applicants' request.
Papers Submitted
It is hereby acknowledged that the following papers have been received and placed of record in the file:
Amended Claims as filed on April 07, 2026
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 07, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2-4, 6-8, 10-19, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasbun et al. (US 2019/0102298) (hereinafter Hasbun) (published April 04, 2019) in view of Dono (US 2019/0066816) (hereinafter Dono) (published February 28, 2019) and Cornwell et al. (US 2007/0165461) (hereinafter Cornwell) (published July 19, 2007).
Regarding Claim 2, Hasbun discloses a method comprising: isolating a first conductive path of a controller from a memory die of the memory device, wherein the first conductive path is isolated from the memory die at a switching component of the controller;
“In some examples, during a first time duration, the memory controller 605 may access the first number of memory dies 625 in the first tier while the second number of memory dies 626 in the second tier are isolated. During a second time duration following the first time duration, the memory controller 605 (e.g., main master), in collaboration with the repeater 607 (e.g., re-driver), may access the second number of memory dies 626 in the second tier through the first set of TSVs 621 and the second set of TSVs 622 while the first number of memory dies 625 in the first tier are isolated” (Hasbun [0096])
“In some examples, the path selection component 750 may facilitate the selection of one or more paths. For example, path selection component 750 may select the first signal path 720 to communicate a signal to first memory die 710. In other examples, path selection component 750 may select the third signal path 730 to communicate a signal to second memory die 715. In any example, path selection component 750 may select one or more signal paths based on a type of signal (e.g., a binary-symbol signal), a type of data transferred (e.g., control data), or an availability of a channel for data transfer” (Hasbun [0106] the unselected paths are isolated from the memory dies)
coupling a second conductive path of the controller with the memory die based at least in part on isolating the first conductive path from the memory die, wherein the second conductive path is coupled with the memory die at the switching component;
“In some examples, during a first time duration, the memory controller 605 may access the first number of memory dies 625 in the first tier while the second number of memory dies 626 in the second tier are isolated. During a second time duration following the first time duration, the memory controller 605 (e.g., main master), in collaboration with the repeater 607 (e.g., re-driver), may access the second number of memory dies 626 in the second tier through the first set of TSVs 621 and the second set of TSVs 622 while the first number of memory dies 625 in the first tier are isolated” (Hasbun [0096])
“In some examples, the path selection component 750 may facilitate the selection of one or more paths. For example, path selection component 750 may select the first signal path 720 to communicate a signal to first memory die 710. In other examples, path selection component 750 may select the third signal path 730 to communicate a signal to second memory die 715. In any example, path selection component 750 may select one or more signal paths based on a type of signal (e.g., a binary-symbol signal), a type of data transferred (e.g., control data), or an availability of a channel for data transfer” (Hasbun [0106] the unselected paths are isolated from the memory dies)
routing, using the switching component, a signal for activating the memory die based at least in part on coupling the second conductive path with the memory die; and
“The memory controller 605 may send a Chip Enable (CE) signal to the memory dies 625 when the memory controller 605 transmit the second signal 620 through the set of TSVs 621. The CE signal designates a targeted memory die (e.g., 625-a, or any one of the memory dies 625 depicted in the diagram 601) among the memory dies 625 to receive the second signal 620. In some examples, the memory controller 605 may directly send the CE signal to the targeted memory die. When the targeted memory die (e.g., the memory die 625-a) receives the CE signal, the targeted memory die (e.g., the memory die 625-a) may activate its receiver to receive the second signal 620 and decode information contained therein” (Hasbun [0089])
“Memory controller 1401 may include one or more driver circuits (“drivers”) 1405. The driver(s) 1405 may be in electronic communication with the signal paths 1415 (e.g. data buses) and may be configured to communicate (e.g., send or transmit) multi-level signals and/or binary level signals over the one or more signal paths 1415 (e.g. data buses)” (Hasbun [0196])
“A driver 1405 may include an encoder 1440 coupled to (e.g., in electronic communication with) a driving circuit 1435. The encoder 1440 may be configured to receive one or more bit streams 1445 and convert (e.g., encode) the bit streams 1445 into one or more control signals 1450. The driving circuit 1435 may be configured to receive the control signal(s) 1425 and drive a voltage over an internal signal path 1415 based on the control signal(s) 1425” (Hasbun [0197] the driver circuit would be a switching circuit to send the Chip Enable signals to turn on and off the memory dies)
activating the memory die based at least in part on routing the signal.
“When the targeted memory die (e.g., the memory die 625-a) receives the CE signal, the targeted memory die (e.g., the memory die 625-a) may activate its receiver to receive the second signal 620 and decode information contained therein” (Hasbun [0089])
But does not explicitly state determining whether a memory device is operating in a diagnostic mode or a non-diagnostic mode; that the isolating is based at least in part on determining that the memory device is operating in the non-diagnostic mode, and that routing is done while operating in the non-diagnostic mode and using a multiplexer of the switching component.
Dono discloses determining whether a memory device is operating in a diagnostic mode or a non-diagnostic mode;
“In certain examples, during non-test modes, the read data multiplexers 538, 548 can isolate the additional data paths 565, 566 from exchanging data between channel 0 and channel 1. During test mode, the read data multiplexers 538 of channel 0 can isolate the memory array of the channel 1 from the third data path 563, and the read data multiplexers 548 of channel 1 can isolate the memory array of the channel 0 from the first data path 561” (Dono [0039] when there are multiple modes of operation it is obvious that the current operation modes would be determine to know how the device is to function)
that the isolating is based at least in part on determining that the memory device is operating in the non-diagnostic mode,
“In certain examples, during non-test modes, the read data multiplexers 538, 548 can isolate the additional data paths 565, 566 from exchanging data between channel 0 and channel 1. During test mode, the read data multiplexers 538 of channel 0 can isolate the memory array of the channel 1 from the third data path 563, and the read data multiplexers 548 of channel 1 can isolate the memory array of the channel 0 from the first data path 561” (Dono [0039])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the test mode of Dono with the system in Hasbun to yield the predictable results of being able to have multiple modes of operation and identify which mode of operation the device is in. The motivation for doing so would be to increase reliability of the memory as disclosed by Dono. “a plurality of additional data paths of the stacked memory sub-system can couple pairs of channels to allow for I/O circuit testing of each channel without the need for an external test board to provide loopback testing paths for the test data. Providing the additional data paths within the stacked memory sub-system can eliminate the need for costly equipment while increasing I/O testing reliability for stacked memory sub-systems that include a significant number of micro-bump I/O connections” (Dono [0043])
Cornwell, Hasbun, and Dono discloses that routing is done while operating in the non-diagnostic mode and using a multiplexer of the switching component.
“the board-level disabling circuits 270a-270d may use various hardware and/or software implementations to programmably disable selected chip enable signals. For example, the disabling circuit 270c may disable the flash memory die 215c if a circuit element (e.g., pull up-resistor, series resistor, jumper connection) is depopulated so as to prevent the CE3 pin 220c of the package 205 from receiving a chip enable signal. As another example, the disabling circuit 270c may disable the flash memory die 215c if a signal path is shorted to a rail (e.g., Vcc or ground) by a shorting path (e.g., populated with a substantially zero Ohm resistor or diode, active pull-up or pull-down transistor) to effectively short the chip enable signal transmission line so that the CE3 pin 220c may not receive a valid chip enable signal. In some implementations, the disabling circuits 270a-270d are analog switches and/or multiplexers that can connect or disconnect signals to the chip enable pins 220a-220d under the control of the controller 210, for example” (Cornwell [0041])
“A driver 1405 may include an encoder 1440 coupled to (e.g., in electronic communication with) a driving circuit 1435. The encoder 1440 may be configured to receive one or more bit streams 1445 and convert (e.g., encode) the bit streams 1445 into one or more control signals 1450. The driving circuit 1435 may be configured to receive the control signal(s) 1425 and drive a voltage over an internal signal path 1415 based on the control signal(s) 1425” (Hasbun [0197])
“For example, in non-test modes, the memory interface circuit 312 can provide interface circuitry to receive control information from a memory controller and move non-test information between the memory arrays 313 and external circuits using the independent channels (Channels A-H)” (Dono [0024] to be able to move information, the signal has to be a routed through a path)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to modify the driver in the combination of Hasbun and Dono to include the multiplexer of Cornwell to yield the predictable results of being able to connect or disconnect the chip enable signal in relation to when the signal needs to be driven to enable the memory die. The motivation for doing so would be to increase efficiency by not needing to maintain unnecessary signals.
Regarding Claim 3, Hasbun further discloses wherein isolating the first conductive path of the controller from the memory die comprises: isolating the first conductive path of the controller from an input of the memory die.
“In some examples, during a first time duration, the memory controller 605 may access the first number of memory dies 625 in the first tier while the second number of memory dies 626 in the second tier are isolated. During a second time duration following the first time duration, the memory controller 605 (e.g., main master), in collaboration with the repeater 607 (e.g., re-driver), may access the second number of memory dies 626 in the second tier through the first set of TSVs 621 and the second set of TSVs 622 while the first number of memory dies 625 in the first tier are isolated” (Hasbun [0096])
Regarding Claim 4, Hasbun further discloses wherein coupling the second conductive path of the controller with the memory die comprises: coupling the second conductive path of the controller with an input of the memory die based at least in part on isolating the first conductive path of the controller from the memory die.
“In some examples, during a first time duration, the memory controller 605 may access the first number of memory dies 625 in the first tier while the second number of memory dies 626 in the second tier are isolated. During a second time duration following the first time duration, the memory controller 605 (e.g., main master), in collaboration with the repeater 607 (e.g., re-driver), may access the second number of memory dies 626 in the second tier through the first set of TSVs 621 and the second set of TSVs 622 while the first number of memory dies 625 in the first tier are isolated” (Hasbun [0096])
Regarding Claim 6, Hasbun further discloses further comprising: generating, by the controller, the signal for activating the memory die based at least in part on coupling the second conductive path of the controller with the memory die.
“the memory controller 605 may directly send the CE signal to the targeted memory die. When the targeted memory die (e.g., the memory die 625-a) receives the CE signal, the targeted memory die (e.g., the memory die 625-a) may activate its receiver to receive the second signal 620 and decode information contained therein” (Hasbun [0089] CE signal from the control can only be sent to the memory die after it is coupled and are used to activate the memory die)
Regarding Claim 7, Hasbun further discloses further comprising: selecting the signal for activating the memory die based at least in part on coupling the second conductive path of the controller with the memory die; and transmitting, to the memory die, the signal based at least in part on selecting the signal.
“the memory controller 605 may directly send the CE signal to the targeted memory die. When the targeted memory die (e.g., the memory die 625-a) receives the CE signal, the targeted memory die (e.g., the memory die 625-a) may activate its receiver to receive the second signal 620 and decode information contained therein” (Hasbun [0089] CE signal is used to activate the memory die)
“A driver 1405 may include an encoder 1440 coupled to (e.g., in electronic communication with) a driving circuit 1435. The encoder 1440 may be configured to receive one or more bit streams 1445 and convert (e.g., encode) the bit streams 1445 into one or more control signals 1450. The driving circuit 1435 may be configured to receive the control signal(s) 1425 and drive a voltage over an internal signal path 1415 based on the control signal(s) 1425” (Hasbun [0197] the control signal being sent would be the CE signal to activate the target memory die)
Regarding Claim 8, Hasbun and Cornwell further discloses further comprising: blocking one or more signals from being routed from one or more pads of the controller to the memory die based at least in part on transmitting the signal.
“A driver 1405 may include an encoder 1440 coupled to (e.g., in electronic communication with) a driving circuit 1435. The encoder 1440 may be configured to receive one or more bit streams 1445 and convert (e.g., encode) the bit streams 1445 into one or more control signals 1450. The driving circuit 1435 may be configured to receive the control signal(s) 1425 and drive a voltage over an internal signal path 1415 based on the control signal(s) 1425” (Hasbun [0197] the driver receives multiple streams of data and will choose which paths to the memory dies to receive the data and which paths to be blocked see paragraphs [0201-0205] and [0212-0213])
“the board-level disabling circuits 270a-270d may use various hardware and/or software implementations to programmably disable selected chip enable signals. For example, the disabling circuit 270c may disable the flash memory die 215c if a circuit element (e.g., pull up-resistor, series resistor, jumper connection) is depopulated so as to prevent the CE3 pin 220c of the package 205 from receiving a chip enable signal. As another example, the disabling circuit 270c may disable the flash memory die 215c if a signal path is shorted to a rail (e.g., Vcc or ground) by a shorting path (e.g., populated with a substantially zero Ohm resistor or diode, active pull-up or pull-down transistor) to effectively short the chip enable signal transmission line so that the CE3 pin 220c may not receive a valid chip enable signal. In some implementations, the disabling circuits 270a-270d are analog switches and/or multiplexers that can connect or disconnect signals to the chip enable pins 220a-220d under the control of the controller 210, for example” (Cornwell [0041])
Regarding Claim 10, Hasbun discloses a non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to:
“The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium” (Hasbun [0368])
determine, at a controller of a memory device, that the memory device has entered a mode associated with performing a procedure;
“In some examples, memory controller 1310 may be configured to determine a first signaling mode for circuit 1300 and configure one or more output circuits 1335 to generate non-binary symbols that each represent two or more bits output by memory array 1305” (Hasbun [0185])
couple, at a switching component of the controller, a first conductive path of the controller with an input of a memory die of the memory device based at least in part on determining that the memory device has entered the mode;
“In some cases, each output circuit 1335 may include a multiplexer. For example, memory controller 1310 may configure the multiplexer of at least eight output circuits 1335 to output a first output type based during the first signaling mode. For example, the first output type may be a group of bits (e.g., a bit pair) and may correspond to a multi-symbol signal (e.g., PAM4) mode of operation” (Hasbun [0188] when multiplexed, a conductive path is connected while other conductive paths are disconnected)
“In some examples, the path selection component 750 may facilitate the selection of one or more paths. For example, path selection component 750 may select the first signal path 720 to communicate a signal to first memory die 710. In other examples, path selection component 750 may select the third signal path 730 to communicate a signal to second memory die 715. In any example, path selection component 750 may select one or more signal paths based on a type of signal (e.g., a binary-symbol signal), a type of data transferred (e.g., control data), or an availability of a channel for data transfer” (Hasbun [0106])
route, using the switching component of the controller, a signal for activating the memory die based at least in part on coupling the first conductive path of the controller with the input of the memory die and based at least in part on a second conductive path of the controller being isolated from the input of the memory die at the switching component; and
“The memory controller 605 may send a Chip Enable (CE) signal to the memory dies 625 when the memory controller 605 transmit the second signal 620 through the set of TSVs 621. The CE signal designates a targeted memory die (e.g., 625-a, or any one of the memory dies 625 depicted in the diagram 601) among the memory dies 625 to receive the second signal 620. In some examples, the memory controller 605 may directly send the CE signal to the targeted memory die. When the targeted memory die (e.g., the memory die 625-a) receives the CE signal, the targeted memory die (e.g., the memory die 625-a) may activate its receiver to receive the second signal 620 and decode information contained therein” (Hasbun [0089])
“In some examples, the path selection component 750 may facilitate the selection of one or more paths. For example, path selection component 750 may select the first signal path 720 to communicate a signal to first memory die 710. In other examples, path selection component 750 may select the third signal path 730 to communicate a signal to second memory die 715. In any example, path selection component 750 may select one or more signal paths based on a type of signal (e.g., a binary-symbol signal), a type of data transferred (e.g., control data), or an availability of a channel for data transfer” (Hasbun [0106] the unselected paths are isolated from the memory die)
“Memory controller 1401 may include one or more driver circuits (“drivers”) 1405. The driver(s) 1405 may be in electronic communication with the signal paths 1415 (e.g. data buses) and may be configured to communicate (e.g., send or transmit) multi-level signals and/or binary level signals over the one or more signal paths 1415 (e.g. data buses)” (Hasbun [0196])
“A driver 1405 may include an encoder 1440 coupled to (e.g., in electronic communication with) a driving circuit 1435. The encoder 1440 may be configured to receive one or more bit streams 1445 and convert (e.g., encode) the bit streams 1445 into one or more control signals 1450. The driving circuit 1435 may be configured to receive the control signal(s) 1425 and drive a voltage over an internal signal path 1415 based on the control signal(s) 1425” (Hasbun [0197] the driver circuit would be a switching circuit to send the Chip Enable signals to turn on and off the memory dies)
activate the memory die based at least in part on routing the signal.
“When the targeted memory die (e.g., the memory die 625-a) receives the CE signal, the targeted memory die (e.g., the memory die 625-a) may activate its receiver to receive the second signal 620 and decode information contained therein” (Hasbun [0089])
But does not explicitly state that the mode is a diagnostic mode and the procedure is a diagnostic procedure, that the routing is done while operating in the diagnostic mode and using a multiplexer of the switching component.
Dono discloses that the mode is a diagnostic mode and the procedure is a diagnostic procedure,
“At 603, during a test mode of the I/O circuits of a first channel, test information can be received at data terminals of the first channel from an additional data path that couples the first channel to another second channel. In certain examples, a read data multiplexer of the first channel can be used to route the data to the data terminals of the first channel via a first data path of the first channel and the first additional data path of the stacked memory apparatus” (Dono [0041] the procedure happening during the test mode is for diagnostic purposes)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the test mode of Dono with the system in Hasbun to yield the predictable results of being able to have multiple modes of operation and identify which mode of operation the device is in. The motivation for doing so would be to increase reliability of the memory as disclosed by Dono. “a plurality of additional data paths of the stacked memory sub-system can couple pairs of channels to allow for I/O circuit testing of each channel without the need for an external test board to provide loopback testing paths for the test data. Providing the additional data paths within the stacked memory sub-system can eliminate the need for costly equipment while increasing I/O testing reliability for stacked memory sub-systems that include a significant number of micro-bump I/O connections” (Dono [0043])
Cornwell, Hasbun, Dono discloses routing is done while operating in the diagnostic mode and using a multiplexer of the switching component.
“the board-level disabling circuits 270a-270d may use various hardware and/or software implementations to programmably disable selected chip enable signals. For example, the disabling circuit 270c may disable the flash memory die 215c if a circuit element (e.g., pull up-resistor, series resistor, jumper connection) is depopulated so as to prevent the CE3 pin 220c of the package 205 from receiving a chip enable signal. As another example, the disabling circuit 270c may disable the flash memory die 215c if a signal path is shorted to a rail (e.g., Vcc or ground) by a shorting path (e.g., populated with a substantially zero Ohm resistor or diode, active pull-up or pull-down transistor) to effectively short the chip enable signal transmission line so that the CE3 pin 220c may not receive a valid chip enable signal. In some implementations, the disabling circuits 270a-270d are analog switches and/or multiplexers that can connect or disconnect signals to the chip enable pins 220a-220d under the control of the controller 210, for example” (Cornwell [0041])
“A driver 1405 may include an encoder 1440 coupled to (e.g., in electronic communication with) a driving circuit 1435. The encoder 1440 may be configured to receive one or more bit streams 1445 and convert (e.g., encode) the bit streams 1445 into one or more control signals 1450. The driving circuit 1435 may be configured to receive the control signal(s) 1425 and drive a voltage over an internal signal path 1415 based on the control signal(s) 1425” (Hasbun [0197])
“At 603, during a test mode of the I/O circuits of a first channel, test information can be received at data terminals of the first channel from an additional data path that couples the first channel to another second channel. In certain examples, a read data multiplexer of the first channel can be used to route the data to the data terminals of the first channel via a first data path of the first channel and the first additional data path of the stacked memory apparatus” (Dono [0041] to be able to receive information, the signal has to be a routed through a path)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to modify the driver in the combination of Hasbun and Dono to include the multiplexer of Cornwell to yield the predictable results of being able to connect or disconnect the chip enable signal in relation to when the signal needs to be driven to enable the memory die. The motivation for doing so would be to increase efficiency by not needing to maintain unnecessary signals.
Regarding Claim 11, Hasbun and Dono further discloses wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: isolate, at the switching component, the second conductive path of the controller from the input of the memory die based at least in part on determining that the memory device has entered the diagnostic mode, wherein routing the signal is based at least in part on isolating the second conductive path.
“In some examples, the path selection component 750 may facilitate the selection of one or more paths. For example, path selection component 750 may select the first signal path 720 to communicate a signal to first memory die 710. In other examples, path selection component 750 may select the third signal path 730 to communicate a signal to second memory die 715. In any example, path selection component 750 may select one or more signal paths based on a type of signal (e.g., a binary-symbol signal), a type of data transferred (e.g., control data), or an availability of a channel for data transfer” (Hasbun [0106] the unselected paths are isolated from the memory die)
“In some cases, each output circuit 1335 may include a multiplexer. For example, memory controller 1310 may configure the multiplexer of at least eight output circuits 1335 to output a first output type based during the first signaling mode. For example, the first output type may be a group of bits (e.g., a bit pair) and may correspond to a multi-symbol signal (e.g., PAM4) mode of operation” (Hasbun [0188] when multiplexed a conductive path is connected while other paths are disconnected)
“During test mode, the read data multiplexers 538 of channel 0 can isolate the memory array of the channel 1 from the third data path 563, and the read data multiplexers 548 of channel 1 can isolate the memory array of the channel 0 from the first data path 561” (Dono [0039])
Regarding Claim 12, Hasbun and Dono further discloses wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: perform the diagnostic procedure associated with the diagnostic mode on the memory device based at least in part on activating the memory die.
“the memory controller 110 may be an example of a semiconductor die that may execute one or more processes, operations, or procedures configured to control various aspects of the system 100 or initiate various operation or actions” (Hasbun [0044])
“memory controller 1310 may monitor a symbol rate (which may include identifying an associated clock rate) associated with one or more output pins, determine a data rate for the one or more output pins based on the symbol rate (e.g., based on how many bits each symbol represents, which may be known to memory controller 1310 based on a current signaling mode), compare the data rate to one or more threshold data rates, determine a length of time for which the data rate is above or below a threshold data rate, and adjust the signaling mode at one or more output pins between binary-symbol signals or orders of multi-symbol signals, or alternatively or additionally adjust the number of active output pins, in order to optimize output data rate, the number of active output pins, or power consumption based on observed conditions” (Hasbun [0183])
“In some examples, memory controller 1310 may be configured to determine a first signaling mode for circuit 1300 and configure one or more output circuits 1335 to generate non-binary symbols that each represent two or more bits output by memory array 1305” (Hasbun [0185])
“At 603, during a test mode of the I/O circuits of a first channel, test information can be received at data terminals of the first channel from an additional data path that couples the first channel to another second channel. In certain examples, a read data multiplexer of the first channel can be used to route the data to the data terminals of the first channel via a first data path of the first channel and the first additional data path of the stacked memory apparatus” (Dono [0041])
Regarding Claim 13, Dono and Hasbun further discloses wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: output a result of the diagnostic procedure to one or more pads of the controller based at least in part on performing the diagnostic procedure.
“At 603, during a test mode of the I/O circuits of a first channel, test information can be received at data terminals of the first channel from an additional data path that couples the first channel to another second channel. In certain examples, a read data multiplexer of the first channel can be used to route the data to the data terminals of the first channel via a first data path of the first channel and the first additional data path of the stacked memory apparatus” (Dono [0041] the diagnostic procedure being performed)
“memory controller 1310 may monitor a symbol rate (which may include identifying an associated clock rate) associated with one or more output pins, determine a data rate for the one or more output pins based on the symbol rate (e.g., based on how many bits each symbol represents, which may be known to memory controller 1310 based on a current signaling mode), compare the data rate to one or more threshold data rates, determine a length of time for which the data rate is above or below a threshold data rate, and adjust the signaling mode at one or more output pins between binary-symbol signals or orders of multi-symbol signals, or alternatively or additionally adjust the number of active output pins, in order to optimize output data rate, the number of active output pins, or power consumption based on observed conditions” (Hasbun [0183] the result of the procedure is outputted to the pads/pins by activating or deactivating them)
Regarding Claim 14, Hasbun further discloses wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: block one or more signals from one or more pads of the controller from being routed to the memory die based at least in part on routing the signal for activating the memory die.
“In some cases, each output circuit 1335 may include a multiplexer. For example, memory controller 1310 may configure the multiplexer of at least eight output circuits 1335 to output a first output type based during the first signaling mode. For example, the first output type may be a group of bits (e.g., a bit pair) and may correspond to a multi-symbol signal (e.g., PAM4) mode of operation” (Hasbun [0188] when multiplexed, a conductive path is connected while other paths are disconnected)
Regarding Claim 15, Hasbun further discloses wherein the signal is received via a pad of the controller coupled with the first conductive path.
“the memory controller 605 may directly send the CE signal to the targeted memory die. When the targeted memory die (e.g., the memory die 625-a) receives the CE signal, the targeted memory die (e.g., the memory die 625-a) may activate its receiver to receive the second signal 620 and decode information contained therein” (Hasbun [0089])
“In some examples, multiplexer 915 may be coupled with driver 920. Driver 920 may also be coupled with output pin 925. Driver 920 may be configured to receive bits from multiplexer 915, generate a symbol representative of each bit received from multiplexer 915, and supply such symbols to output pin 925” (Hasbun [0134] a multiplexer will couple the selected path (a pad of the controller) to the memory die)
Regarding Claim 16, Hasbun discloses an apparatus, comprising: a memory die; and
“The circuit 1400 may include one or more internal signal paths 1415-a through 1415-N that couple at least one memory die 1403 with a memory controller 1401” (Hasbun [0194])
a controller coupled with the memory die, the controller comprising:
“The circuit 1400 may include one or more internal signal paths 1415-a through 1415-N that couple at least one memory die 1403 with a memory controller 1401” (Hasbun [0194])
a first conductive path for routing, using a switching component, a first signal for activating the memory die; and
“The memory controller 605 may send a Chip Enable (CE) signal to the memory dies 625 when the memory controller 605 transmit the second signal 620 through the set of TSVs 621. The CE signal designates a targeted memory die (e.g., 625-a, or any one of the memory dies 625 depicted in the diagram 601) among the memory dies 625 to receive the second signal 620. In some examples, the memory controller 605 may directly send the CE signal to the targeted memory die. When the targeted memory die (e.g., the memory die 625-a) receives the CE signal, the targeted memory die (e.g., the memory die 625-a) may activate its receiver to receive the second signal 620 and decode information contained therein” (Hasbun [0089])
“Memory controller 1401 may include one or more driver circuits (“drivers”) 1405. The driver(s) 1405 may be in electronic communication with the signal paths 1415 (e.g. data buses) and may be configured to communicate (e.g., send or transmit) multi-level signals and/or binary level signals over the one or more signal paths 1415 (e.g. data buses)” (Hasbun [0196])
“A driver 1405 may include an encoder 1440 coupled to (e.g., in electronic communication with) a driving circuit 1435. The encoder 1440 may be configured to receive one or more bit streams 1445 and convert (e.g., encode) the bit streams 1445 into one or more control signals 1450. The driving circuit 1435 may be configured to receive the control signal(s) 1425 and drive a voltage over an internal signal path 1415 based on the control signal(s) 1425” (Hasbun [0197] the driver circuit would be a switching circuit to send the Chip Enable signals to turn on and off the memory dies)
the switching component coupled with the first conductive path and configured to couple the first conductive path with the memory die, wherein the switching component is operable to direct the first signal to the memory die based at least in part on the switching component isolating a second conductive path from the memory die.
“In some examples, the path selection component 750 may facilitate the selection of one or more paths. For example, path selection component 750 may select the first signal path 720 to communicate a signal to first memory die 710. In other examples, path selection component 750 may select the third signal path 730 to communicate a signal to second memory die 715. In any example, path selection component 750 may select one or more signal paths based on a type of signal (e.g., a binary-symbol signal), a type of data transferred (e.g., control data), or an availability of a channel for data transfer” (Hasbun [0106] the unselected paths are isolated from the memory die)
“A driver 1405 may include an encoder 1440 coupled to (e.g., in electronic communication with) a driving circuit 1435. The encoder 1440 may be configured to receive one or more bit streams 1445 and convert (e.g., encode) the bit streams 1445 into one or more control signals 1450. The driving circuit 1435 may be configured to receive the control signal(s) 1425 and drive a voltage over an internal signal path 1415 based on the control signal(s) 1425” (Hasbun [0197] the driver circuit would be a switching circuit to send the Chip Enable signals to turn on and off the memory dies)
But does not explicitly state that the routing is done while operating in a diagnostic mode and using a multiplexer of the switching component.
Dono discloses operating in a diagnostic mode
“At 603, during a test mode of the I/O circuits of a first channel, test information can be received at data terminals of the first channel from an additional data path that couples the first channel to another second channel. In certain examples, a read data multiplexer of the first channel can be used to route the data to the data terminals of the first channel via a first data path of the first channel and the first additional data path of the stacked memory apparatus” (Dono [0041])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the test mode of Dono with the system in Hasbun to yield the predictable results of being able to have multiple modes of operation and identify which mode of operation the device is in. The motivation for doing so would be to increase reliability of the memory as disclosed by Dono. “a plurality of additional data paths of the stacked memory sub-system can couple pairs of channels to allow for I/O circuit testing of each channel without the need for an external test board to provide loopback testing paths for the test data. Providing the additional data paths within the stacked memory sub-system can eliminate the need for costly equipment while increasing I/O testing reliability for stacked memory sub-systems that include a significant number of micro-bump I/O connections” (Dono [0043])
Cornwell, Hasbun, and Dono discloses that the routing is done while operating in a diagnostic mode and using a multiplexer of the switching component.
“the board-level disabling circuits 270a-270d may use various hardware and/or software implementations to programmably disable selected chip enable signals. For example, the disabling circuit 270c may disable the flash memory die 215c if a circuit element (e.g., pull up-resistor, series resistor, jumper connection) is depopulated so as to prevent the CE3 pin 220c of the package 205 from receiving a chip enable signal. As another example, the disabling circuit 270c may disable the flash memory die 215c if a signal path is shorted to a rail (e.g., Vcc or ground) by a shorting path (e.g., populated with a substantially zero Ohm resistor or diode, active pull-up or pull-down transistor) to effectively short the chip enable signal transmission line so that the CE3 pin 220c may not receive a valid chip enable signal. In some implementations, the disabling circuits 270a-270d are analog switches and/or multiplexers that can connect or disconnect signals to the chip enable pins 220a-220d under the control of the controller 210, for example” (Cornwell [0041])
“A driver 1405 may include an encoder 1440 coupled to (e.g., in electronic communication with) a driving circuit 1435. The encoder 1440 may be configured to receive one or more bit streams 1445 and convert (e.g., encode) the bit streams 1445 into one or more control signals 1450. The driving circuit 1435 may be configured to receive the control signal(s) 1425 and drive a voltage over an internal signal path 1415 based on the control signal(s) 1425” (Hasbun [0197])
“At 603, during a test mode of the I/O circuits of a first channel, test information can be received at data terminals of the first channel from an additional data path that couples the first channel to another second channel. In certain examples, a read data multiplexer of the first channel can be used to route the data to the data terminals of the first channel via a first data path of the first channel and the first additional data path of the stacked memory apparatus” (Dono [0041] to be able to receive information, the signal has to be a routed through a path)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to modify the driver in the combination of Hasbun and Dono to include the multiplexer of Cornwell to yield the predictable results of being able to connect or disconnect the chip enable signal in relation to when the signal needs to be driven to enable the memory die. The motivation for doing so would be to increase efficiency by not needing to maintain unnecessary signals.
Regarding Claim 17, Hasbun and Cornwell further discloses wherein the controller further comprises:
the second conductive path for routing, using the multiplexer of the switching component, a second signal for activating the memory die, wherein the switching component is operable to direct the second signal to the memory die based at least in part on the switching component isolating the first conductive path from the memory die.
“In some examples, the path selection component 750 may facilitate the selection of one or more paths. For example, path selection component 750 may select the first signal path 720 to communicate a signal to first memory die 710. In other examples, path selection component 750 may select the third signal path 730 to communicate a signal to second memory die 715. In any example, path selection component 750 may select one or more signal paths based on a type of signal (e.g., a binary-symbol signal), a type of data transferred (e.g., control data), or an availability of a channel for data transfer” (Hasbun [0106] the unselected paths are isolated from the memory die)
“A driver 1405 may include an encoder 1440 coupled to (e.g., in electronic communication with) a driving circuit 1435. The encoder 1440 may be configured to receive one or more bit streams 1445 and convert (e.g., encode) the bit streams 1445 into one or more control signals 1450. The driving circuit 1435 may be configured to receive the control signal(s) 1425 and drive a voltage over an internal signal path 1415 based on the control signal(s) 1425” (Hasbun [0197] see fig. 14 there are multiple paths for receiving bit stream 1445)
“the board-level disabling circuits 270a-270d may use various hardware and/or software implementations to programmably disable selected chip enable signals. For example, the disabling circuit 270c may disable the flash memory die 215c if a circuit element (e.g., pull up-resistor, series resistor, jumper connection) is depopulated so as to prevent the CE3 pin 220c of the package 205 from receiving a chip enable signal. As another example, the disabling circuit 270c may disable the flash memory die 215c if a signal path is shorted to a rail (e.g., Vcc or ground) by a shorting path (e.g., populated with a substantially zero Ohm resistor or diode, active pull-up or pull-down transistor) to effectively short the chip enable signal transmission line so that the CE3 pin 220c may not receive a valid chip enable signal. In some implementations, the disabling circuits 270a-270d are analog switches and/or multiplexers that can connect or disconnect signals to the chip enable pins 220a-220d under the control of the controller 210, for example” (Cornwell [0041] see fig. 2 there are multiple paths for the different CE signals to activate the respective memory dies)
Regarding Claim 18, Hasbun and Cornwell further discloses wherein the switching component is coupled with the second conductive path and configured to couple the second conductive path with the memory die.
“A driver 1405 may include an encoder 1440 coupled to (e.g., in electronic communication with) a driving circuit 1435. The encoder 1440 may be configured to receive one or more bit streams 1445 and convert (e.g., encode) the bit streams 1445 into one or more control signals 1450. The driving circuit 1435 may be configured to receive the control signal(s) 1425 and drive a voltage over an internal signal path 1415 based on the control signal(s) 1425” (Hasbun [0197] the driver circuit would be a switching circuit to send the Chip Enable signals to turn on and off the memory dies)
“the board-level disabling circuits 270a-270d may use various hardware and/or software implementations to programmably disable selected chip enable signals. For example, the disabling circuit 270c may disable the flash memory die 215c if a circuit element (e.g., pull up-resistor, series resistor, jumper connection) is depopulated so as to prevent the CE3 pin 220c of the package 205 from receiving a chip enable signal. As another example, the disabling circuit 270c may disable the flash memory die 215c if a signal path is shorted to a rail (e.g., Vcc or ground) by a shorting path (e.g., populated with a substantially zero Ohm resistor or diode, active pull-up or pull-down transistor) to effectively short the chip enable signal transmission line so that the CE3 pin 220c may not receive a valid chip enable signal. In some implementations, the disabling circuits 270a-270d are analog switches and/or multiplexers that can connect or disconnect signals to the chip enable pins 220a-220d under the control of the controller 210, for example” (Cornwell [0041] see fig. 2 the multiple paths for the different CE signals are coupled to activate the respective memory dies)
Regarding Claim 19, Hasbun and Cornwell further discloses wherein the switching component comprises: a first input coupled with the first conductive path; and a second input coupled with the second conductive path.
“A driver 1405 may include an encoder 1440 coupled to (e.g., in electronic communication with) a driving circuit 1435. The encoder 1440 may be configured to receive one or more bit streams 1445 and convert (e.g., encode) the bit streams 1445 into one or more control signals 1450. The driving circuit 1435 may be configured to receive the control signal(s) 1425 and drive a voltage over an internal signal path 1415 based on the control signal(s) 1425” (Hasbun [0197] see fig. 14 there are multiple paths for receiving bit stream 1445)
“the board-level disabling circuits 270a-270d may use various hardware and/or software implementations to programmably disable selected chip enable signals. For example, the disabling circuit 270c may disable the flash memory die 215c if a circuit element (e.g., pull up-resistor, series resistor, jumper connection) is depopulated so as to prevent the CE3 pin 220c of the package 205 from receiving a chip enable signal. As another example, the disabling circuit 270c may disable the flash memory die 215c if a signal path is shorted to a rail (e.g., Vcc or ground) by a shorting path (e.g., populated with a substantially zero Ohm resistor or diode, active pull-up or pull-down transistor) to effectively short the chip enable signal transmission line so that the CE3 pin 220c may not receive a valid chip enable signal. In some implementations, the disabling circuits 270a-270d are analog switches and/or multiplexers that can connect or disconnect signals to the chip enable pins 220a-220d under the control of the controller 210, for example” (Cornwell [0041] see fig. 2 each of the multiple paths are coupled with a different input)
Regarding Claim 21, Hasbun further discloses wherein the first conductive path couples a pad of the controller with the switching component.
“Memory controller 1401 may include one or more driver circuits (“drivers”) 1405. The driver(s) 1405 may be in electronic communication with the signal paths 1415 (e.g. data buses) and may be configured to communicate (e.g., send or transmit) multi-level signals and/or binary level signals over the one or more signal paths 1415 (e.g. data buses)” (Hasbun [0196] see fig. 14 the paths 1445 are conductive paths connected to the pads of the controller to the driver 1405)
Claim(s) 5 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasbun (published April 04, 2019), Dono (published February 28, 2019), and Cornwell (published July 19, 2007) as applied to claims 4 and 17 above, and further in view of TAFT (US 2018/0302067) (hereinafter Taft) (published October 18, 2018).
Regarding Claim 5, the combination of Hasbun, Dono and Cornwell disclosed the method of claim 4, but does not explicitly state further comprising: writing a value to a register for selecting the second conductive path, wherein coupling the second conductive path is based at least in part on the value.
Taft discloses further comprising: writing a value to a register for selecting the second conductive path, wherein coupling the second conductive path is based at least in part on the value.
“The Q outputs of flip-flops 120 are provided as signals 715 to the multiplexer 740 and one of the latched delayed SYSREFs is selected by the multiplexer 740 as the output SYSREF_SEL signal to use by other logic for synchronization purposes. The programmable delay value written to register 730 represents a selection (SELECT) signal to cause the multiplexer 740. The delay assessment circuits described herein are reset (their D flip-flops are cleared) before the next low-to-high transition of SYSREF to be able to correctly capture the next assertion of SYSREF” (Taft [0031])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to the modify the multiplexer in the combination of Hasbun, Dono, and Cornwell to include a register to hold the value of the select for the multiplexer as disclosed in Taft. The motivation for doing so would be to improve efficiency, when storing the value in the register the amount of power required is less than continuously driving the signal and also allows for better data retention.
Regarding Claim 20, the combination of Hasbun, Dono, and Cornwell disclosed the apparatus of claim 17, but does not explicitly state further comprising: a register coupled with the switching component, wherein a value stored in the register indicates, to the switching component, whether to select the first conductive path or the second conductive path.
Taft discloses further comprising: a register coupled with the switching component, wherein a value stored in the register indicates, to the switching component, whether to select the first conductive path or the second conductive path.
“The Q outputs of flip-flops 120 are provided as signals 715 to the multiplexer 740 and one of the latched delayed SYSREFs is selected by the multiplexer 740 as the output SYSREF_SEL signal to use by other logic for synchronization purposes. The programmable delay value written to register 730 represents a selection (SELECT) signal to cause the multiplexer 740. The delay assessment circuits described herein are reset (their D flip-flops are cleared) before the next low-to-high transition of SYSREF to be able to correctly capture the next assertion of SYSREF” (Taft [0031])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to the modify the multiplexer in the combination of Hasbun, Dono, and Cornwell to include a register to hold the value of the select for the multiplexer as disclosed in Taft. The motivation for doing so would be to improve efficiency, when storing the value in the register the amount of power required is less than continuously driving the signal and also allows for better data retention.
Response to Arguments
Applicant’s arguments, see pages 7-11 of remarks, filed April 07, 2026, with respect to the rejection(s) of claim(s) 2-21 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Hasbun et al. (US 2019/0102298), Dono (US 2019/0066816) and Cornwell et al. (US 2007/0165461).
The arguments are focused on the prior art not teaching the newly amended limitation of diagnostic and non-diagnostic mode which is disclosed by the new reference Dono as test mode and non-test modes.
Conclusion
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/S.L./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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