DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Foreign priority is not claimed for this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/19/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation in claim 8 stating “a drain of the first common-gate amplifier being coupled to the drain of the first common-source amplifier” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. It would help make the drawings clearer if nodes were added to indicate where two transistors are connected.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 13 is objected to because of the following informalities:
Claim 13 last two lines: “a source of the second common-gate amplifier being coupled to a gate of the first common-source amplifier and the bias resistor” should this read “…coupled to a gate of the second common-source amplifier and the bias resistor.”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 8 and 10 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 20220247358 by Salameh.
Regarding claim 8, Salameh teaches an electronic device (Fig. 6a) comprising:
one or more antennas (Fig. 11 #1102);
an amplifier coupled to the one or more antennas (Fig. 11, Par. 108-109),
the amplifier (Fig. 6a) comprising a bias resistor (Fig. 6a R) configured to receive an input signal (Fig. 6a RFin),
a first common-source amplifier (Fig. 6a M0), a source of the first common-source amplifier being coupled to a ground connection, a drain of the first common-source amplifier configured to receive an input power and provide an amplified signal in response to the input signal (Fig. 6a Vdd), and
a first common-gate amplifier (Fig. 6a MEQ), a source of the first common-gate amplifier being coupled to a gate of the first common-source amplifier (Fig. 6a M0) and the bias resistor (Fig. 6a R), and a drain of the first common-gate amplifier (MEQ) being coupled to the drain of the first common-source amplifier (M0).
Regarding claim 10, Salameh teaches the electronic device of claim 8, comprising a second common-source amplifier (Fig. 3 M0-), a drain of the second common-source amplifier being coupled to the drain of the first common-source amplifier (Fig. 3 M0+). The drains of M0+ and M0- are coupled to the supply voltage VDD, which means they are also coupled together.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Salameh as applied to claim 8 above, and further in view of US 9413309 by Zhao et al.
Regarding claim 9, Salameh teaches the electronic device of claim 8, but fails to teach a first capacitor coupled to the drain and the source of the first common-gate amplifier.
However, Zhao teaches an amplifier circuit (Fig. 1a) with a first capacitor (Fig. 1a #118) coupled to the drain and the source of the first common-gate amplifier (Fig. 1a #114).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine Zhao with Salameh in order to have an amplifier circuit with capacitors that can reduce or eliminate parasitic capacitance associated with the drain of the input common source transistors. This enhances performance and augments gain of the amplifier (Col. 5 lines 33-45).
Allowable Subject Matter
Claims 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 13 is objected to, but would be allowed if rewritten to correct the minor issue stated above.
Claims 1-7 and 14-20 are allowed.
The prior art fails to teach a bias resistor that is connected to the source of both of the common-gate amplifiers.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAREH SHAMIRYAN whose telephone number is (703)756-4616. The examiner can normally be reached M-F: 7:00AM-4:00PM PT.
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/NAREH SHAMIRYAN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843