DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Information Disclosure Statement
The prior art documents submitted by applicant in the Information Disclosure Statement filed on January 8, 2024 have all been considered and made of record (note the attached copy(ies) of form PTO-1449).
Drawings
Six sheets of drawings were filed on January 8, 2024 have been accepted by the examiner.
Election/Restrictions
Claims 11-17 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on September 5, 2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites—wherein the functionally equivalent versions of the photonics circuit…-- renders the other two species in claim 1 (e.g., “functional duplicates of each other with intentionally introduced physical differences in their fabrication layouts” and “differently optically tuned versions of each other”) inoperable when claim 1 is read in combination with claim 5.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 4-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Witzens et al. (WO-2016/150522 A1, herein “Witzens”).
Regarding claim 1, Witzens discloses a photonics integrated circuit (PIC) chip comprising:
a substrate (silicon device layer of a same SOI chip, page 16, lines 13-16);
an interface port unit IPU formed on the substrate (I, the bottom bus line in Fig. 13);
a photonics circuit unit PCU (MZM) formed on the substrate (Fig. 13 and page 16, lines 1-16);
a photonics circuit 1PC (first ring resonator with frequency f1) formed on the substrate and optically coupled between the interface port unit IPU (I) and the photonics circuit unit PCU (MZM); and
a photonics circuit 2PC (second ring resonator with frequency f5) formed on the substrate and optically coupled between the interface port unit IPU (I) and the photonics circuit unit PCU (MZM) in parallel with photonics circuit 1PC; wherein the photonics circuit 1PC and the photonics circuit 2PC are at least one of the following:
functional duplicates of each other with intentionally introduced physical differences in their fabrication layouts;
differently optically tuned versions of each other; and
functionally equivalent versions of each other with intentionally introduced differences in their circuit layouts (Page 49, line -18 to page 50, line 16).
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Claim 4. Witzens discloses the photonics circuits (ring resonator f1 and ring resonator f5) which implies the resonators are tuned to different frequencies and the photonic ring resonators inherently have different losses due to critical parameters such as waveguide dimensions, circuit size, attenuation, and thermal management (Page 3, line 20 – Page 4, line 22).
Claim 5. Witzens discloses the PIC chip of claim 1, wherein the functionally equivalent versions of the photonics circuit 1PC (ring resonator f1) and the photonics circuit 2PC (ring resonator f5) with intentionally introduced differences in their circuit layouts include at least one of the following: one or more optical elements of the photonic circuit 1PC each having a different geometrical size compared to a comparable functionally equivalent element of the photonics circuit 2PC. Since ring resonator f1 and ring resonator f5 support different frequencies and the resonance condition in terms of circumference relationship is
m
λ
=
n
e
f
f
L
; wherein lambda is the resonant wavelength, L is the ring length, and neff is the effective refractive index. Therefore the size of the ring resonator is fundamentally inversely proportional to its resonant frequency. For higher frequencies (shorter wavelengths) the ring circumference is smaller. For lower frequencies (longer wavelengths) the ring circumference is larger.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Witzens in view of Chang et al. (US 2017/0195064 A1, herein “Chang”).
Claim 2. Witzens discloses the invention of claim 1, however, Witzens does not teach the PIC chip interface port unit includes first and second optical ports.
Chang teaches photonic integrated circuit using chip integration wherein a separate chip (102) is provided for optical input source. PIC chip 102 is coupled to PIC chip 106 via plurality of waveguides 124 and 128 (Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Witzens to have multiple optical ports with integrating separate PIC chips. One would be motivated to increase a single optical port to multiple optical ports for handling higher signal density.
Claim 3. Witzens in view of Chang teach the invention of claim 2, but Witzens in view of Chang do not explicitly teach the first and second optical port are spaced between 1 micrometer and 20 millimeters, inclusive, from each other. It would have been obvious to one of ordinary skill in the art at the effective filing date of the invention to optimize the optical port spacing depending on the waveguide width, the PIC chip dimension, and minimizing crosstalk, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955).
Regarding claim 6, Witzens / Chang teach the photonics circuit unit PCU connected to external circuitry that is not part of the PIC chip, wherein: when the PIC chip is used as a receiver r transmitter, the photonics circuit unit PCU (PIC chip 108) receives from the external circuitry (PIC chip 102) via optical ports (128-1…128j) and output to optical ports (1421…142m)
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Claim 7. Witzens / Chang teach the PIC chip of claim 1, further including an optical switch (1301…130n) operative for coupling the photonics circuit unit PCU to either the photonics circuit 1PC or the photonic circuit 2PC (photonic circuit 1, photonic circuit 1).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Witzens / Chang as applied to claim 2 above, and further in view of Evans et al. (US 2019/0342010 A1, herein “Evans”).
Witzens / Chang teach the PIC chip of claim 2, but Witzens / Chang is silent to the limitation “to avoid operational interference between the photonics circuit 1PC and the photonics circuit 2PC during the use of the PIC chip, only one of the optical port 1OP or optical port 2OP at time is coupleable to an external optical fiber that is not part of the PIC chip.
Evans teaches photonic integrated circuits wherein spare channels are provided in the optical multiplexers/demultiplexers (Para [0023]). Spare channels are activated or deactivated and is fed into the inputs of the WDM system (Para [0041]). Evans implements the spare channel activation and deactivation with an 8-channel analog switch integrated circuit such that, for example, faulty channels are deactivated or the inputs or outputs are deselected, while inputs or outputs of corresponding number of spare channels are activated to supply electrical signals to the control driver (Para [0108]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the analog switch integrated circuit provided to regulate the activation of spare input/output channels, as taught by Evans would be modifiable to the integrated PIC chips as taught by Witzens / Chang. One would be motivated to employ spare optical ports as a redundancy in the event of one or more of faulty channels will not affect the operation of the photonic circuits.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Witzens in view of Amersfoort et al. (US 5,629,992, herein “Amersfoort”).
Witzens discloses the PIC chip of claim 1, however, Witzens does not disclose the limitations of claim 19.
Amersfoort teaches a waveguide implementation of wavelength division multiplexing in Fig. 17. The waveguide implementation of the WDM system has an interface port unit have two input optical ports (168), two optical interaction regions (194, 196), and output ports (184) make up the demultiplexer (212). Amersfoort further teaches an embodiment wherein two demultiplexers are in a network having crossed connect as shown in Fig. 15.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Witzen’s PIC chip to integrate a waveguide implementation of a demultiplexer network as taught by Amersfoort for separating first and second stream of light into separate optical channels having different wavelengths. One would be motivated to employ demultiplexer network to handle high density optical signals such as in communication networks.
Allowable Subject Matter
Claims 8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior arts of record do not teach the cross demultiplexing scheme as recited in claim 8. In particular, the prior arts of record do not teach:
the optical demultiplexer 3DM comprises optical inputs I3 and I4 optically coupled to optical outputs O1 and O3 and optical outputs O5 and O6 optically coupled to the optical-electrical converters or photodiodes PD1 and PD2;
the optical demultiplexer 4DM comprises optical inputs I5 and I6 optically coupled to optical outputs O2 and O4 and optical outputs O7 and O8 optically coupled to the optical-electrical converters or photodiodes PD3 and PD4; and
a first set of the optical demultiplexers comprising 1DM, 3DM, and 4DM and a second set of the optical demultiplexers comprising 2DM, 3DM, and 4DM are operative, one set of the optical demultiplexers at a time, whereupon a stream of light including a plurality of optical channels or lanes (L) having different wavelengths of light input into the optical port 1OP or the optical port 2OP, respectively.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erin D Chiem whose telephone number is (571)272-3102. The examiner can normally be reached 10 am - 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A. Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIN D CHIEM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874