DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 7-9, filed on June 25, 2026, with respect to the rejection of claims 1-14 under 35 U.S.C. § 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of U.S. Patent Application Publication No. 2016/0049469 A1 to Yoshikawa et al.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2013/0096825 A1 to Mohanty in view of U.S. Patent Application Publication No. 2016/0049469 A1 to Yoshikawa et al.
Mohanty clearly teaches an Electromechanical Magnetometer And Applications Thereof, comprising:
a substrate layer (608);
a temperature compensation layer (208);
a piezoelectric film layer (204); and
an electrode layer (202);
wherein:
the temperature compensation layer is located between the substrate layer and the piezoelectric film layer (see Figures 6A-6G);
the substrate layer and the temperature compensation layer are integrated by wafer bonding (see paragraphs [0093] and [0127]);
the temperature compensation layer and the piezoelectric film layer are integrated by wafer bonding (see paragraphs [0093] and [0127]); and
the temperature compensation layer is made of a positive temperature coefficient material (see paragraphs [0007], [0013] – [0016], [0018 – [0020], [0054], [0065], and [0165]); and
the electrode layer is arranged on a surface of the piezoelectric film layer (see Figures 2A, 2B, 3A-3D, 3H-3J, and 6A-6G);
wherein said layers have different thicknesses (see paragraphs [0020], [0050], [0057], [0059], [0078], [0079], [0085]-[0089], [0093], [0094], and [0101]-[0108]).
However, it fails to disclose:
said thickness of the substrate layer ranges from 30λ to 150 λ; thick
said thickness of the temperature compensation layer ranges from 0.05λ to 2.0λ;
said thickness of the piezoelectric film layer ranges from 0.05λ to 10λ; and
said thickness of the electrode layer ranges from 0.06λ to 0.15λ,
wherein λ is a wavelength corresponding to the electrode layer.
Yoshikawa et al. discloses a Supporting Substrate For Composite Substrate And Composite Substrate, comprising:
substrate layers of a composite substrate,
wherein:
a thickness of the substrate layer ranges from 30λ to 150 λ (see paragraphs [0053], [0054], [0057], [0058], [0060], [0066], [0068], [0088], [0100], [0102], and [0112]);
a thickness of the temperature compensation layer ranges from 0.05λ to 2.0λ (see paragraphs [0053], [0054], [0057], [0058], [0060], [0066], [0068], [0088], [0100], [0102], and [0112];
a thickness of the piezoelectric film layer ranges from 0.05λ to 10λ (see paragraphs [0053], [0054], [0057], [0058], [0060], [0066], [0068], [0088], [0100], [0102], and [0112]; and
a thickness of the electrode layer ranges from 0.06λ to 0.15λ (see paragraphs [0053], [0054], [0057], [0058], [0060], [0066], [0068], [0088], [0100], [0102], and [0112],
wherein λ is a wavelength corresponding to the electrode layer (see paragraphs [0053], [0054], [0057], [0058], [0060], [0066], [0068], [0088], [0100], [0102], and [0112].
It would have been obvious to one skilled in the art before the effective filling date of the invention to use the thickness ranges as a function of wavelength with respect to temperature as disclosed by Yoshikawa et al. on the electromechanical magnetometer disclosed by Mohanty, for the purpose of tunning the operational frequency and stabilizing the operational temperature coefficient of the layers.
With regards to claim 2, Mohanty discloses:
the temperature compensation layer being made of silicon dioxide SiO2 (see paragraphs [0071] and [0085]).
With regards to claim 3, Mohanty discloses:
the electrode layer being an interdigital electrode layer (see paragraph [0055]) and the interdigital electrode layer being made of at least one of the following materials:
aluminum (see paragraphs [0065] and [0076]), copper, gold (see paragraph [0076]) and an aluminum-copper alloy.
With regards to claim 4, Mohanty discloses:
the piezoelectric film layer being made of at least one of the following materials:
lithium tantalate LiTaO3 (see paragraph [0065]), and lithium niobate LiNbO3 (see paragraph [0065]).
With regards to claim 5, Mohanty discloses:
the substrate layer being made of at least one of the following materials:
silicon Si (see paragraphs [0064], [0065], [0071], [0074], [0080], [0087], [0115], [0116], and [0182]), silicon carbide SiC (see paragraph [0074]), and sapphire (see paragraph [0074]).
With regards to claim 11, Mohanty discloses:
the substrate layer being made of SiC (see paragraph [0074]);
the temperature compensation layer being made of SiO2 (see paragraphs [0071] and [0085]);
the piezoelectric film layer being made of LiTaO3 (see paragraph [0065]); and
the electrode layer is made of gold (see paragraph [0076]).
With regards to claim 12, Mohanty discloses:
the substrate layer being made of SiC (see paragraph [0074]);
the temperature compensation layer being made of SiO2 (see paragraphs [0071] and [0085]);
the piezoelectric film layer being made of LiTaO3 (see paragraph [0065]);
the thickness of the substrate layer is 110λ (see paragraphs [0055], [0066], [0075], [0080], and [0106]);
the thickness of the temperature compensation layer is 0.25λ (see paragraphs [0055], [0066], [0075], [0080], and [0106]);
the thickness of the piezoelectric film layer is 0.1λ (see paragraphs [0055], [0066], [0075], [0080], and [0106]); and
the thickness of the electrode layer is 0.1λ (see paragraphs [0055], [0066], [0075], [0080], and [0106]).
With regards to claim 13, Mohanty discloses:
the substrate layer is made of SiC (see paragraph [0074]);
the temperature compensation layer is made of SiO2 (see paragraphs [0071] and [0085]);
the piezoelectric film layer is made of LiTaO3 (see paragraph [0065]);
the thickness of the substrate layer is 110 λ (see paragraphs [0055], [0066], [0075], [0080], and [0106]);
the thickness of the temperature compensation layer is 0.25 λ (see paragraphs [0055], [0066], [0075], [0080], and [0106]);
the thickness of the piezoelectric film layer is 0.25 λ (see paragraphs [0055], [0066], [0075], [0080], and [0106]); and
the thickness of the electrode layer is 0.1 λ (see paragraphs [0055], [0066], [0075], [0080], and [0106]).
With regards to claim 14, Mohanty in view of Yoshikawa et al. disclose the steps of:
obtaining a substrate layer (608 of Mohanty);
preparing a temperature compensation layer (208 of Mohanty) on the substrate layer (see Figures 6A-6G of Mohanty), wherein:
the substrate layer and the temperature compensation layer are integrated by wafer bonding (see paragraphs [0093] and [0127] of Mohanty); and
a positive temperature coefficient (see paragraphs [0007], [0013] – [0016], [0018 – [0020], [0054], [0065], and [0165] of Mohanty) material is adopted for the temperature compensation layer;
preparing a piezoelectric film layer (204 of Mohanty) on the temperature compensation layer, wherein:
the temperature compensation layer and the piezoelectric film layer are integrated by wafer bonding (see paragraphs [0093] and [0127] of Mohanty); and
preparing an electrode layer (202 of Mohanty) on the piezoelectric film layer (see Figures 6A-6G of Mohanty);
wherein a thickness of the substrate layer ranges from 30A to 150A, a thickness of the temperature compensation layer ranges from 0.05A to 2.0, a thickness of the piezoelectric film layer ranges from 0.05A to 10A, and a thickness of the electrode layer ranges from 0.06A to 0.15A, wherein A is a wavelength corresponding to the electrode layer ((see paragraphs [0053], [0054], [0057], [0058], [0060], [0066], [0068], [0088], [0100], [0102], and [0112] of Yoshikawa et al.).
Conclusion
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/PEDRO J CUEVAS/Primary Examiner, Art Unit 2896 March 20, 2026
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