NON-FINAL OFFICE ACTION
This non-final Office action addresses U.S. Application Serial No. 18/137,801, entitled INDUCTOR COIL AND FORMING METHOD THEREOF.
Claims 1-20 are pending in this application.
Claims 1-5, 11, 14-20 are rejected.
Claims 6-10, 12 and 13 have allowable subject matter.
I. PRIORITY
Examiner recognizes the Applicant’s claim of foreign priority to Chinese Patent Application No. CN20221045308.3, filed April 24, 2022
II. OBJECTION TO CLAIMS
Claim 13 is objected to because there is no article for “number.” Examiner finds this number should be “a number.” Appropriate correction is required.
Claim 17 is objected to because claim 17 repeats a portion of claim 16. Specifically, claim 17 recites “providing a substrate including a base, a device layer on the base, a conductive layer and an electrical interconnection structure” which is identically recited in claim 16, from which claim 17 depends. Appropriate correction is required.
III. OBJECTION TO THE DRAWINGS
The drawings are objected to under 37 C.F.R. §1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the base, the device layer on the base, the conductive layer and the electrical interconnect layer as recited and made in claims 1-20 must be shown or the feature(s) canceled from the claim(s). Examiners find the specification explicitly states these items are “(not shown).” No new matter should be entered.
Corrected drawing sheets in compliance with 37 C.F.R. §1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 C.F.R. §1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
IV. CLAIM INTERPRETATION
After careful review of the original specification, the prosecution history, and unless expressly noted otherwise by the Examiner, the Examiner is unable to locate any lexicographic definitions (either express or implied) with the required clarity, deliberateness, and precision with regard to pending and examined claims. Because the Examiner is unable to locate any lexicographic definitions with the required clarity, deliberateness, and precision, the Examiner concludes that Applicant is not his own lexicographer for the pending and examined claims. See MPEP §2111.01(IV).
The Examiner further finds that because the pending and examined claims herein recite neither “step for” nor “means for” nor any substitute therefore, the examined claims fail Prong (A) as set forth in MPEP §2181(I). Because all examined claims fail Prong (A) as set forth in MPEP §2181(I), the Examiner concludes that all examined claims do not invoke 35 U.S.C. §112(f). See also Ex parte Miyazaki, 89 USPQ2d 1207, 1215-16 (B.P.A.I. 2008)(precedential)(where the Board did not invoke 35 U.S.C. § 112(f) because “means for” was not recited and because applicant still possessed an opportunity to amend the claims).
Because of the Examiner’s findings above that Applicant is not his own lexicographer and the pending and examined claims do not invoke 35 U.S.C. §112(f) the pending and examined claims will be given the broadest reasonable interpretation consistent with the specification since patentee has an opportunity to amend claims. See MPEP §2111, MPEP §2111.01 and In re Yamamoto et al., 222 USPQ 934 (Fed. Cir. 1984). Under a broadest reasonable interpretation, words of the claim must be given their plain meaning, unless such meaning is inconsistent with the specification. See MPEP §2111.01(I). It is further noted it is improper to import claim limitations from the specification, i.e., a particular embodiment appearing in the written description may not be read into a claim when the claim language is broader than the embodiment. See MPEP §2111.01(II).
V. CLAIM REJECTIONS – 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. §102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
V.A. Anticipation Rejections Applying Daley
Claims 1-5. 11. 14-17 and 19 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by U.S. Patent Application Publication No. 2009/0322447 to Douglas Daley et al. (hereinafter “Daley”).
Regarding claim 1, Daley discloses:
1. An inductor coil, comprising:
See Daley FIG. 1, reprinted below.
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a substrate, including a base, a device layer on the base, a conductive layer, and an electrical interconnect structure;
See FIG. 1 above and FIG. 2A, reprinted below, illustrating the base 24, a device
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layer 14, a conductive layer 40 and an interconnect structure 48.
a plurality of stacked coil layers being on the substrate, each coil layer including a plurality of sub-coil structures on a same layer; and
See FIGS. 1 and 2A above, stacked coil layers 50 and 52, each coil comprising a plurality of sub-coil structures on the same layer as shown, with crossing patterns at the opposite side from port terminals 56/58.
a plurality of electrical connection layers between two adjacent coil layers, a projection pattern of each of the plurality of electrical connection layers on a surface of the substrate being within a range of projection patterns of two adjacent coil layers that are in contact with the plurality of electrical connection layers on the surface of the substrate, all the plurality of coil layers being connected in parallel through all the plurality of electrical connection layers, and any section that is perpendicular to the substrate and simultaneously passes through all the plurality of sub-coil structures in two adjacent coil layers passes through an electrical connection layer.
See Daley FIGS., 1 and 2A, see interconnect layers 54 between the stack coils 50 and 52. Further Daley ¶0032 wherein “the bar vias 54 may be replaced by vias (not shown) that are similar to vias 42, 44, 46, 48 associated with the on-chip capacitor 16.” Thus, the interconnect layers 54 may be the bars shown or a plurality of bar vias following the pattern of the interconnect layers 54.
Regarding claim 2, Daley discloses the inductor of claim 1 and further:
wherein materials of the two adjacent coil layers in contact with all the plurality of electrical connection layers are same or different.
Examiners note there are only two possibilities for the material of the coil layers and the interconnect layers, same or different. Thus, Daley discloses these materials are either the same or different.
Regarding claim 3, Daley discloses the inductor of claim 1 and further:
wherein number of sub-coil structures included in each coil layer is greater than one, and the sub-coil structures are arranged in concentric rings.
See Daley FIG. 1 above, note each coil structure 50 and 52 comprises three concentric rings of coil substructures.
Regarding claim 4, Daley discloses the inductor of claim 1 and further:
wherein each electrical connection layer includes a plurality of sub-connection structures in a same layer, and an upper surface and a lower surface of each sub-connection structure respectively contact the sub-coil structures on different layers.
See Daley FIGS., 1 and 2A, see interconnect layers 54 between the stack coils 50 and 52. Further Daley ¶0032 wherein “the bar vias 54 may be replaced by vias (not shown) that are similar to vias 42, 44, 46, 48 associated with the on-chip capacitor 16.” Thus the interconnect layers 54 may be a plurality of bar vias following the pattern of the interconnect layers 54. Furthermore, these bar vias/interconnect layers have upper and lower surfaces contacting the coil layers 50 and 52.
Regarding claim 5, Daley discloses the inductor of claim 5 and further:
wherein number of sub-connection structures included in each electrical connection layer is greater than one, and the sub-connection structures are arranged in concentric rings.
See Daley FIGS., 1 and 2A, see interconnect layers 54 between the stack coils 50 and 52. Further Daley ¶0032 wherein “the bar vias 54 may be replaced by vias (not shown) that are similar to vias 42, 44, 46, 48 associated with the on-chip capacitor 16.” Thus the interconnect layers 54 may be a plurality of bar vias following the pattern of the interconnect layers 54. Furthermore, these bar vias/interconnect layers following the pattern of the bar vias would provide concentric rings of bar vias/interconnect layers.
Regarding claim 11, Daley discloses the inductor of claim 5 and further:
wherein number of the sub-connection structures is equal to number of sub-coil structures in a same layer.
See Daley FIG. 1 above wherein the number of sub-connection structures 54 matches those of the sub-coil structures 52 in the same layer.
Regarding claim 14, Daley discloses the inductor of claim 1 and further:
wherein each electrical connection layer includes a plurality of discretely arranged conductive plugs.
See Daley FIGS., 1 and 2A, see interconnect layers 54 between the stack coils 50 and 52. Further Daley ¶0032 wherein “the bar vias 54 may be replaced by vias (not shown) that are similar to vias 42, 44, 46, 48 associated with the on-chip capacitor 16.”
Regarding claim 15, Daley discloses the inductor of claim 3 and further:
wherein the sub-coil structures in a same layer are electrically connected through connecting bridges.
See Daley FIGS. 1 and 2A above, each of stacked coil layers 50 and 52, each coil comprising a plurality of sub-coil structures on the same layer as shown, with crossing patterns at the opposite side from port terminals 56/58.
Regarding claim 16, Daley discloses the coil of claim 1 and further:
16. A method of forming an inductor coil, comprising:
See Daley FIGS. 1 and 2A above.
providing a substrate comprising a base, a device layer on the base, a conductive layer, and an electrical interconnect structure; and
See Daley FIGS. 1 and 2A illustrating a provided base 24, device layers 14/18, conductive layer 40 and interconnect structure 48.
forming a plurality of stacked coil layers on the substrate, and
See Daley FIGS. 1 and 2A above, illustrating provided stacked coil layers 50 and 52, each coil comprising a plurality of sub-coil structures on the same layer as shown, with crossing patterns at the opposite side from port terminals 56/58.
a plurality of electrical connection layers between two adjacent coil layers, a projection pattern of each of the plurality of electrical connection layers on a surface of the substrate being in a range of projection patterns of two adjacent coil layers in contact with the electrical connection layers on the surface of the substrate; and each coil layer including a plurality of sub-coil structures in a same layer, all the plurality of coil layers being connected in parallel through all the plurality of electrical connection layers, and any section that is perpendicular to the substrate and simultaneously passes through all the plurality of sub-coil structures in two adjacent coil layers passing through an electrical connection layer.
See Daley FIGS., 1 and 2A illustrating proivided interconnect layers 54 between the stack coils 50 and 52. Further Daley ¶0032 wherein “the bar vias 54 may be replaced by vias (not shown) that are similar to vias 42, 44, 46, 48 associated with the on-chip capacitor 16.” Thus the interconnect layers 54 may be a plurality of bar vias following the pattern of the interconnect layers 54. Further note the arrangement shown reads on the recited arrangement of the coil structures and connection layers.
Regarding claim 17, Daley discloses the method of claim 1 and further:
providing a substrate including a base, a device layer on the base, a conductive layer and an electrical interconnection structure; and forming a first dielectric layer on the substrate and a first coil layer in the first dielectric layer.
See Daley FIGS. 1 and 2A illustrating a provided base 24, device layer 14, conductive layer 40 and interconnect structure 48. Further see the provided dielectric layer 18 on the substrate for supporting the first coil layer 52.
Regarding claim 19, Daley discloses the method of claim 1 and further:
forming an interconnection dielectric layer on the first dielectric layer and the first coil layer and the electrical connection layers in the interconnection dielectric layer.
See Daley FIGS. 1 and 2A illustrating an interconnection dielectric layer 18 on which the substrate for supporting the first coil layer 52 and the electrical connection layers 54/42.
VI. CLAIM REJECTIONS – 35 U.S.C. §103
The following is a quotation of 35 U.S.C. §103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
VI.A. Obviousness Rejections Applying Daley and Sano
Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Daley in view of U.S. Patent Application Publication No. 2020/0027637 to Rikiyu Sano et al. (hereinafter “Sano”).
Regarding claim 18, Daley teaches the method of forming the coil of claim 17 as evidenced above. However, Daley does not specifically disclose the manner to which each coil layer is formed. Nevertheless, Sano teaches a method of making a layered coil structure (See Sano FIGS. 5A-5F, reprinted below) wherein the method of Sano teaches forming the first dielectric layer and the first coil layer includes: forming the first dielectric layer 11a/11b on the substrate (shown in Sano FIG. 5B); forming first grooves on the first dielectric layer (shown in Sano FIG. 5C; and forming the first coil layer in the first grooves (shown in Sano FIGS. 5D-5F).
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Sano FIGS. 5A-5C Sano FIGS. 5D-5F
It would have been obvious at the time the invention was filed to incorporate the method of making the coil layers 50 and 52 of Daley in the manner as taught by Sano. Examiners find such a combination is merely applying the known technique of making such coil layers as taught in Sano to a known device as taught in Daley. Furthermore, Examiner finds this application of the method of making is predictable as it would not change the operation or structures of the coil layers of Daley, but merely provide a method of making such coil layers. Furthermore, the method of making according to Sano allows for making a stacked laminate body coil structure. See Sano ¶0069.
Regarding claim 20, Daley teaches the method of forming the coil of claim 19 as evidenced above. However, Daley does not specifically disclose the manner to which the interconnection grooves/bar vias are formed. Nevertheless, Sano teaches a method of making a layered coil body having layers with vias (See Sano ¶¶0117-0118) comprising forming the interconnection dielectric layer and forming interconnection grooves on the interconnection dielectric layer (See Sano ¶0117 wherein “[a]n insulating layer provided with an opening and a via hole is formed”); and forming the electrical connection layers in the interconnection grooves (See Sano ¶0118 wherein a conductive paste is applied to fill the via wherein “a via hole conductor is formed in the via hole”). It would have been obvious at the time the invention was filed to employ the method of making vias as taught in Sano for the vias in Daley. Examiners find such combination is merely applying the known technique of making such bar vias/interconnection layers as taught in Sano to a known device as taught in Daley. Furthermore, Examiner finds this application of the method of making is predictable as it would not change the operation or structures of the coil of Daley, but merely provide a method of making such bar vias/interconnection layers. Furthermore, the method of making according to Sano allows for making a stacked laminate body coil structure. See Sano ¶0069.
VII. ALLOWABLE SUBJECT MATTER
Claims 6-10, 12 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 6-10, Examiner finds the prior art of record in this application does not show or teach “a distance between at least one set of adjacent sub-connection structures is greater than a first pitch of the sub-connection structures” as recited in the claims and in combination with the other features of the claims. The closest prior art above, Daley, shows a pitch between its bar vias/interconnection layers, but does not show one set thereof have a separation greater than the pitch of all the sub-connection structures.
Regarding claim 12, Examiner finds the prior art of record in this application does not show or teach the “number of sub-connection structures is less than number of sub-coil structures in a same layer” as recited in the claim and in combination with the other features of the claim. The closest prior art, Daley, teaches either the same number of sub-connection structures or more sub-connection structures than coil sub-structures, not less.
Regarding claim 13, Examiners find the prior art of record in this application does not show or teach “a ratio of a width of a sub-connection structure to a width of a sub-coil structure ranges from 1:3 to 2:3” as recited in the claim and in combination with the other features of the claims. While Examiner finds Daley necessarily discloses each sub-coil structure has some width as shown above, Examiner does not find a discussion nor teaching of the particular ratio range claimed.
VIII. CONCLUSION
Claims 1-20 are pending.
Claims 1-5, 11, 14-20 are rejected.
Claims 6-10, 12 and 13 have allowable subject matter.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH WHITTINGTON whose telephone number is (571) 272-2264. The examiner can normally be reached 8:30am - 5:00pm, Monday - Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Fischer can be reached at (571) 272-6779. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/KENNETH WHITTINGTON/Primary Examiner, Art Unit 3992