Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Applicant’s Amendment
Acknowledgment is made of applicant’s amendment, filed 20 September 2025, cancelling claims 2, 12 and 20.
Therefore, claims 1, 3-11 and 13-19 remain pending in the application. Of these, claims 1 and 13 are independent.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 3-11 and 13-19 are rejected under 35 U.S.C. §103 as being unpatentable over Navon et al. (US 9,947,401 B2) in view of Scheuerlein et al. (US 2013/0135925 A1) and further in view of Stansfield (US 9,406,351 B2).
Examiner’s Note:
A reference must be considered in its entirety, not in isolation.”— In re Wesslau, 353 F.2d 238.
“The test for obviousness is what the combined teachings of the references would have suggested to those of ordinary skill in the art.”
— In re Keller, 642 F.2d 413 (CCPA 1981).
Key Note for the Applicant to consider:
There is no legal requirement that: all limitations appear in one figure, or all limitations be disclosed in one paragraph.
Thus, This Office Action properly relies on the teachings of the references as a whole, not on a rigid, element-by-element figure overlay.
Also, The examiner used “the cited references are relied upon for their combined teachings as understood by a person of ordinary skill in the art. The Office Action does not require a one-to-one correspondence between individual claim limitations and a single figure or paragraph of any reference. Rather, the rejection properly relies on the collective disclosures of the references, which, when combined, render the claimed subject matter obvious under 35 U.S.C. §103.”
Regarding independent claim 1, Navon discloses a memory system including a controller that maintains per-block state information representative of access history and allowable usage, and that determines which memory blocks are accessed or written based on stored values.
Scheuerlein discloses memory cell arrays in which each cell comprises a resistance-change element connected in series with a selector/switching element, and teaches that array behavior varies spatially due to electrical effects such as line resistance and IR drop.
Stansfield further discloses memory arrays divided into blocks or subarrays with drive circuitry positioned along array edges, and teaches that electrical characteristics depend on physical distance from the drive circuitry.
A person of ordinary skill in the art would have been motivated to combine Navon’s access-aware controller with Scheuerlein’s resistive memory structure and Stansfield’s block-based array architecture to adapt access frequency based on distance from the drive circuit, thereby improving reliability and endurance. The combination yields the claimed system without requiring undue experimentation.
As for Claim 3 : Claim 3 recites that the allowable number of accesses varies according to distance. As explained above, Scheuerlein teaches distance-dependent electrical behavior across resistive memory arrays, and Stansfield explicitly describes varying electrical characteristics based on proximity to drive circuitry. It would have been obvious to reflect this distance dependency in the allowable access counts managed by Navon’s controller.
As for Claim 4: Claim 4 recites a two-dimensional array with drive circuits positioned along different edges. Stansfield discloses memory arrays arranged in orthogonal directions with multiple peripheral drive circuits located at array edges. Incorporating this arrangement into Navon’s system is a straightforward architectural choice.
As for Claim 5: Claim 5 recites determining distance as a total distance from two drive circuits. Stansfield teaches that multiple drive paths may influence electrical behavior, and a person of ordinary skill in the art would reasonably calculate combined distance metrics to reflect cumulative effects.
As for Claim 6: Claim 6 recites using the shorter of two distances. Selecting a minimum distance metric is an obvious design optimization to conservatively model worst-case electrical behavior in the array.
As for Claim 7: Claim 7 adds a temperature detector. Navon teaches monitoring operational conditions, and Scheuerlein explains that resistive memory behavior is temperature dependent. Adding temperature sensing to refine access control is an obvious enhancement.
As for Claim 8: Claim 8 recites modifying access rates based on temperature. This follows directly from Navon’s adaptive controller logic combined with Scheuerlein’s disclosure that temperature affects memory characteristics.
As for Claim 9: Claim 9 specifies that predetermined access includes read and/or write operations. Navon’s access counting encompasses both read and write events, making this limitation inherent.
As for Claim 10: Claim 10 recites stacked resistance-change and switching elements. Scheuerlein explicitly discloses such stacked resistive memory cells.
As for Claim 11: Claim 11 specifies a magnetoresistance effect element. Scheuerlein discloses resistive memory elements broadly, and substituting an MRAM element is an obvious variant within the same field.
Regarding Independent Claim 13: Claim 13 recites method steps corresponding directly to the controller operations of claim 1, namely storing access-related values, comparing those values, and performing memory operations in an out-of-phase manner across duplicated arrays. Navon teaches these controller decisions, Scheuerlein supplies the resistive memory array context, and Stansfield teaches duplicated or partitioned array structures. Performing the disclosed control logic as a method does not impart patentable distinction over the apparatus.
As for Claim 14: Claim 14 merely restates duplication of the memory array, which is already taught by Stansfield’s multi-subarray architectures and is inherent in claim 13.
As for Claim 15: Claim 15 recites alternating first and second operations between duplicated arrays. Navon teaches scheduling and alternating operations across memory regions, making this an obvious control strategy.
As for Claim 16: Claim 16 specifies read and refresh operations. Both are standard memory operations explicitly contemplated by Navon and Stansfield.
As for Claim 17: Claim 17 adds transmitting command sequences from a controller. This is inherent in any controller-driven memory system and explicitly disclosed by Navon.
As for Claim 18: Claim 18 recites always reading from the array performing read operations. This is an obvious implementation detail to avoid contention and follows directly from the alternating scheme of claim 15.
As for Claim 19: Claim 19 recites sub-arrays arranged in layers with data propagation to subsequent AI layers. Stansfield discloses layered and hierarchical memory organizations, and Navon’s controller logic naturally extends to managing such layered data flow.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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HIEN N. NGUYEN
Primary Examiner
Art Unit 2824
/HN/
January 10, 2026
/HIEN N NGUYEN/Primary Examiner, Art Unit 2824