DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/12/2026 has been entered.
Status of Claims
The following is an office action in response to the communication filed on 01/12/2026.
Claims 1 and 9-10 are amended.
Claims 18-19 are cancelled.
Claims 1-17 and 20 are currently pending.
Claims 1- have been examined.
Information Disclosure Statement
The Information Disclosure Statements received on 01/12/2026, 03/12/2026, and 04/24/2026 have been reviewed and considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 6-12, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (DE 102018220820 A1; hereinafter Kim) in view of Baumeister et al. (US 20170217443 A1; hereinafter Baumeister) and further in view of Chynoweth et al. (US 20190041950 A1; hereinafter Chynoweth).
Regarding claim 1, Kim discloses the subject matter indicated in bold below:
A method comprising (see Kim at least pg. 2, paragraph 2 “The present invention relates to a multi-vehicle multi-core processor error monitoring apparatus and method, and more particularly to a multivehicle multi-core processor error monitoring system and method for monitoring errors and causes of errors in each of a plurality of vehicle multi-core processors.”):
monitoring, using at least one monitoring core processor in a plurality of monitoring core processors, one or more monitoring processes executed by at least another monitoring core processor in the plurality of monitoring core processors (see Kim at least pg. 4, paragraph 4 “The fault monitoring system 200 . . . [includes] an error control processor 210 and a variety of multi-core processors 230 and 240 [(i.e., monitoring core processors).]”; pg. 4, paragraph 10 “. . . the error monitoring processor 210 [monitors] Errors of the multitude of multi-core processors 230 and 240 . . .”), wherein
each monitoring core processor in the plurality of monitoring core processors is . . . communicatively coupled to at least one corresponding performance core processor of a plurality of performance core processors, and further configured to monitor execution of one or more performance processes by the at least one corresponding performance core processor (see Kim at least pg. 5, paragraph 1 “The first multi-core processor 230 receives an error monitoring signal which is a request from the error monitoring processor 210 and after performing an operation on the request in each of the first processor 320 and the second processor 330 , This sends the data processing result to the error monitoring processor 210[.]”), wherein . . . the top-level monitoring processor is configured to monitor execution of monitoring processes by the remaining monitoring core processors of the plurality of monitoring core processors (see Kim at least pg. 4, paragraph 10 “. . . the error monitoring processor 210 [(i.e., top level monitor) monitors] Errors of the multitude of multi-core processors 230 and 240 [(i.e., remaining monitoring core processors)] . . .”; pg. 4, paragraph 11 “The multitude of multi-core processors 230 and 240 perform an operation on each request and return a data processing result to an error control processor as an error monitoring response.”; pg. 5, paragraph 2 “. . . the error control processor [210 stores] a data processing request time . . . and a response time . . . for a data processing request . . .”); . . .
each monitoring core processor in the plurality of monitoring core processors is communicatively coupled to each of the plurality of monitoring core processors (see Kim at least Figure 3- monitoring cores 210, 230, and 240 are in communication with each other); and
executing, using the at least one monitoring core processor, based on the monitoring, at least one action responsive to at least one communication received from the at least another monitoring core processor (see Kim at least pg. 5, paragraph 3, “Finally, the error monitoring processor [210 saves] at least the time of data input / output to a monitoring system, the data processing request time, the data processing result request time and the error issuing time and using it monitors the communication speed, the delay gate and the quality of service (QoS) [(i.e., responsive action)].”).
While Kim discloses monitoring cores communicatively coupled to each other, it does not appear to explicitly disclose the monitoring processors being co-located. And while Kim discloses performance core processors, it does not appear to explicitly disclose that the performance processors are configured to execute performance core processes.
Baumeister teaches that multi-core processing systems are an alternative to multi-chip processing systems (see Baumeister at least [0007] “Microcontrollers (MCU) . . . are, from the view of the programming model, a single core system, but frequently a plurality of processor cores are physically present in order to bring about parallel software implementation. Resources such as, for example, memory resources and/or peripheral resources, are, however, frequently not implemented multiple times and are shared by the processor cores. In contrast to this, multi-chip microcontrollers make available the entire resources multiple times.”).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention with a reasonable expectation of success to have modified the multi-core processing system and communicatively coupled monitoring cores of Kim with the single-chip multi-core processing as taught by Baumeister to have the monitoring processors be co-located. Doing so would reduce cost by reducing the number of integrated circuits required by the processing system and reducing the complexity of the processing system implementation, as recognized by Baumeister (see Baumeister at least [0009] “. . . multi-chip systems are, however, more expensive compared to multi-core systems . . . The use of a plurality of chips for high-availability systems therefore constitutes a significant increase in the costs, to which, in particular, a larger number of integrated circuits and increased complexity of the underlying circuit carrier contribute.”).
While Kim and Baumeister disclose performance core processors, they do not appear to explicitly disclose that the performance processors are configured to execute performance core processes.
Chynoweth teaches the subject matter underlined below:
. . . each performance core processor in the plurality of performance core processors is configured to execute one or more performance core processes (see Chynoweth at least [0113] “For perceptual computing and other purposes, various sensors may be present within the system and may be coupled to processor 1410 in different manners . . . these sensors may include an accelerometer 1441, an ambient light sensor (ALS) 1442, a compass 1443 and a gyroscope 1444.”); . . .
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention with a reasonable expectation of success to have modified the performance core processors of Kim with the performance core processes as taught by Chynoweth to have each performance core processor configured to execute a performance core process. Doing so would align the monitored performance processors with a functional purpose.
Regarding claim 2, Regarding claim 2, Kim, Baumeister, and Chynoweth disclose the analogous subject matter to claim 1 as recited in the claim and applied above. Additionally, Kim discloses the subject matter indicated in bold below:
. . . wherein each monitoring core processor in the plurality of monitoring core processors is coupled with the at least one corresponding performance core processor (see Kim at least Figure 3- processors 320 and 330 are coupled to 230, and processors 340 and 350 are coupled to 240).
While Kim discloses multi-core processing systems and coupling monitoring core processors with performance core processors, it does not appear to explicitly disclose the monitoring core processors being co-located using a common integrated circuit.
Baumeister teaches that multi-core processing systems are an alternative to multi-chip processing systems (see Baumeister at least [0007] “Microcontrollers (MCU) . . . are, from the view of the programming model, a single core system, but frequently a plurality of processor cores are physically present in order to bring about parallel software implementation. Resources such as, for example, memory resources and/or peripheral resources, are, however, frequently not implemented multiple times and are shared by the processor cores. In contrast to this, multi-chip microcontrollers make available the entire resources multiple times.”).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention with a reasonable expectation of success to have modified the multi-core processing system and processing core-coupled monitoring cores of Kim with the single-chip multi-core processing as taught by Baumeister to have the monitoring processors be co-located by a common integrated circuit. Doing so would reduce cost by reducing the number of integrated circuits required by the processing system and reducing the complexity of the processing system implementation, as recognized by Baumeister (see Baumeister at least [0009] “. . . multi-chip systems are, however, more expensive compared to multi-core systems . . . The use of a plurality of chips for high-availability systems therefore constitutes a significant increase in the costs, to which, in particular, a larger number of integrated circuits and increased complexity of the underlying circuit carrier contribute.”).
Regarding claim 3, Kim, Baumeister, and Chynoweth disclose the analogous subject matter to claim 2 as recited in the claim and applied above.
While Kim discloses performance cores, it does not appear to explicitly disclose that the performance core processes are associated with a sensing device of a vehicle.
Chynoweth teaches the subject matter underlined below:
. . . wherein the one or more performance core processes is associated with an operation of at least one sensing device of a vehicle, the at least one sensing device comprising at least one of the following: a camera, a motion sensor (see Chynoweth at least [0113] “For perceptual computing and other purposes, various sensors may be present within the system and may be coupled to processor 1410 in different manners . . . these sensors may include an accelerometer 1441, an ambient light sensor (ALS) 1442, a compass 1443 and a gyroscope 1444.”), an image capturing device, a scanner, a keypad sensing device, a LiDAR, a radar, a microphone, an ultrasonic sensor, an inertial sensor, a GPS receiver, an odometry sensor, and any combination thereof.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention with a reasonable expectation of success to have modified the performance core processors of Kim with the motion sensor-associated performance core processes as taught by Chynoweth to have a performance core process associated with an operation of at least one sensing device of a vehicle, the sensing device(s) comprising at least a motion sensor. Doing so would align the monitored performance processors with a functional purpose of leveraging on-board vehicle sensors.
Regarding claim 6, Kim, Baumeister, and Chynoweth disclose the analogous subject matter to claim 1 as recited in the claim and applied above. Additionally, Kim discloses the subject matter indicated in bold below:
. . . detecting a failure of the at least another monitoring core processor (see Kim at least pg. 6, paragraph 4 “. . . in the quality of service (QoS) mode, the monitoring module may . . . detect whether a problem is caused by a communication error or an operation error when a problem occurs.”; pg. 6, paragraph 9 “. . . through the QoS mode, the error monitoring processor measures 210 the read / write operation time of the buffer as described above . . .”);
using at least a third monitoring core processor in the plurality of monitoring core processors to monitor the one or more monitoring processes previously executed by at least another monitoring core processor based on the detected failure (see Kim at least pg. 4, paragraph 10 “. . . the error monitoring processor 210 [(i.e., third monitoring core processor) monitors] Errors of the multitude of multi-core processors 230 and 240[.] In particular, the error monitoring processor [210 transmits] an error control signal requesting the plurality of multi-core processors 230 and 240 . . .”; pg. 5, paragraph 1 “The first multi-core processor 230 receives an error monitoring signal which is a request from the error monitoring processor 210 and after performing an operation on the request in each of the first processor 320 and the second processor 330[,] This sends the data processing result to the error monitoring processor 210[.]”); and
receiving the at least one communication from the third monitoring core processor (see Kim at least pg. 5, paragraph 1 “The first multi-core processor 230 receives an error monitoring signal which is a request from the error monitoring processor 210 [(i.e., third monitoring core processor)] . . .”).
Regarding claim 7, Kim, Baumeister, and Chynoweth disclose the analogous subject matter to claim 1 as recited in the claim and applied above. Additionally, Kim discloses the subject matter indicated in bold below:
. . . wherein the one or more monitoring processes are executed using at least one predetermined execution pattern (see Kim at least Figure 5- monitoring process flow diagram shown to execute in ordered steps).
Regarding claim 8, Kim, Baumeister, and Chynoweth disclose the analogous subject matter to claim 1 as recited in the claim and applied above. Additionally, Kim discloses the subject matter indicated in bold below:
. . . wherein the at least one action comprises at least one of the following: adjusting execution of the one or more performance core processes (see Kim at least pg. 7, paragraph 12 “. . . if any operation request times are not met, the fault monitoring system will run 200 error counting through, and if the number of error counters exceeds a predetermined threshold, may . . . reset the associated multi-core processor [(i.e., adjust execution of core processes)].”), adjusting execution of the one or more monitoring core processes, executing no action, and any combination thereof.
Regarding claim 9, Kim discloses the subject matter indicated in bold below:
A system, comprising (see Kim at least pg.2, paragraph 2 “The present invention relates to a multi-vehicle multi-core processor error monitoring apparatus and method, and more particularly to a multivehicle multi-core processor error monitoring system and method for monitoring errors and causes of errors in each of a plurality of vehicle multi-core processors.”):
at least one processor (see Kim at least pg. 4, paragraph 4 “. . . an error control processor 210 and a variety of multi-core processors 230 and 240[.]”), and
at least one non-transitory storage media storing instructions that, when executed by the at least one processor, cause the at least one processor to perform operations comprising (see Kim at least pg. 3, paragraph 1 “. . . the present invention provides a multiprocessor error monitoring system and methods for monitoring an error and cause of failure of each of a plurality of processors, and providing a computer-readable storage medium having a program stored thereon for executing the method.”):
monitoring, using at least one monitoring core processor in a plurality of monitoring core processors, one or more monitoring processes executed by at least another monitoring core processor in the plurality of monitoring core processors (see Kim at least pg. 4, paragraph 4 “The fault monitoring system 200 . . . [includes] an error control processor 210 and a variety of multi-core processors 230 and 240[(i.e., monitoring core processors).]”; pg. 4, paragraph 10 “. . . the error monitoring processor 210 [monitors] Errors of the multitude of multi-core processors 230 and 240 . . .”), wherein
each monitoring core processor in the plurality of monitoring core processors is . . . communicatively coupled to at least one corresponding performance core processor of a plurality of performance core processors, and further configured to monitor execution of one or more performance processes by the at least one corresponding performance core processor (see Kim at least pg. 5, paragraph 1 “The first multi-core processor 230 receives an error monitoring signal which is a request from the error monitoring processor 210 and after performing an operation on the request in each of the first processor 320 and the second processor 330 , This sends the data processing result to the error monitoring processor 210[.]”), wherein . . . the top-level monitoring processor is configured to monitor execution of monitoring processes by the remaining monitoring core processors of the plurality of monitoring core processors (see Kim at least pg. 4, paragraph 10 “. . . the error monitoring processor 210 [(i.e., top level monitor) monitors] Errors of the multitude of multi-core processors 230 and 240 [(i.e., remaining monitoring core processors)] . . .”; pg. 4, paragraph 11 “The multitude of multi-core processors 230 and 240 perform an operation on each request and return a data processing result to an error control processor as an error monitoring response.”; pg. 5, paragraph 2 “. . . the error control processor [210 stores] a data processing request time . . . and a response time . . . for a data processing request . . .”); . . .
each monitoring core processor in the plurality of monitoring core processors is communicatively coupled to each of the plurality of monitoring core processors (see Kim at least Figure 3- monitoring cores 210, 230, and 240 are in communication with each other); and
executing, using the at least one monitoring core processor, based on the monitoring, at least one action responsive to at least one communication received from the at least another monitoring core processor (see Kim at least pg. 5, paragraph 3, “Finally, the error monitoring processor [210 saves] at least the time of data input / output to a monitoring system, the data processing request time, the data processing result request time and the error issuing time and using it monitors the communication speed, the delay gate and the quality of service (QoS) [(i.e., responsive action)].”).
While Kim discloses monitoring cores communicatively coupled to each other, it does not appear to explicitly disclose the monitoring processors being co-located. And while Kim discloses performance core processors, it does not appear to explicitly disclose that the performance processors are configured to execute performance core processes.
Baumeister teaches that multi-core processing systems are an alternative to multi-chip processing systems (see Baumeister at least [0007] “Microcontrollers (MCU) . . . are, from the view of the programming model, a single core system, but frequently a plurality of processor cores are physically present in order to bring about parallel software implementation. Resources such as, for example, memory resources and/or peripheral resources, are, however, frequently not implemented multiple times and are shared by the processor cores. In contrast to this, multi-chip microcontrollers make available the entire resources multiple times.”).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention with a reasonable expectation of success to have modified the multi-core processing system and communicatively coupled monitoring cores of Kim with the single-chip multi-core processing as taught by Baumeister to have the monitoring processors be co-located. Doing so would reduce cost by reducing the number of integrated circuits required by the processing system and reducing the complexity of the processing system implementation, as recognized by Baumeister (see Baumeister at least [0009] “. . . multi-chip systems are, however, more expensive compared to multi-core systems . . . The use of a plurality of chips for high-availability systems therefore constitutes a significant increase in the costs, to which, in particular, a larger number of integrated circuits and increased complexity of the underlying circuit carrier contribute.”).
While Kim and Baumeister disclose performance core processors, they do not appear to explicitly disclose that the performance processors are configured to execute performance core processes.
Chynoweth teaches the subject matter underlined below:
. . . each performance core processor in the plurality of performance core processors is configured to execute one or more performance core processes (see Chynoweth at least [0113] “For perceptual computing and other purposes, various sensors may be present within the system and may be coupled to processor 1410 in different manners . . . these sensors may include an accelerometer 1441, an ambient light sensor (ALS) 1442, a compass 1443 and a gyroscope 1444.”); . . .
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention with a reasonable expectation of success to have modified the performance core processors of Kim with the performance core processes as taught by Chynoweth to have each performance core processor configured to execute a performance core process. Doing so would align the monitored performance processors with a functional purpose.
Regarding claim 10, Kim discloses the subject matter indicated in bold below:
At least one non-transitory storage media storing instructions that, when executed by at least one processor, cause the at least one processor to perform operations comprising (see Kim at least pg. 3, paragraph 1 “. . . the present invention provides a multiprocessor error monitoring system and methods for monitoring an error and cause of failure of each of a plurality of processors, and providing a computer-readable storage medium having a program stored thereon for executing the method.”):
monitoring, using at least one monitoring core processor in a plurality of monitoring core processors, one or more monitoring processes executed by at least another monitoring core processor in the plurality of monitoring core processors (see Kim at least pg. 4, paragraph 4 “The fault monitoring system 200 . . . [includes] an error control processor 210 and a variety of multi-core processors 230 and 240[(i.e., monitoring core processors).]”; pg. 4, paragraph 10 “. . . the error monitoring processor 210 [monitors] Errors of the multitude of multi-core processors 230 and 240 . . .”), wherein
each monitoring core processor in the plurality of monitoring core processors is . . . communicatively coupled to at least one corresponding performance core processor of a plurality of performance core processors, and further configured to monitor execution of one or more performance processes by the at least one corresponding performance core processor (see Kim at least pg. 5, paragraph 1 “The first multi-core processor 230 receives an error monitoring signal which is a request from the error monitoring processor 210 and after performing an operation on the request in each of the first processor 320 and the second processor 330 , This sends the data processing result to the error monitoring processor 210[.]”), wherein . . . the top-level monitoring processor is configured to monitor execution of monitoring processes by the remaining monitoring core processors of the plurality of monitoring core processors (see Kim at least pg. 4, paragraph 10 “. . . the error monitoring processor 210 [(i.e., top level monitor) monitors] Errors of the multitude of multi-core processors 230 and 240 [(i.e., remaining monitoring core processors)] . . .”; pg. 4, paragraph 11 “The multitude of multi-core processors 230 and 240 perform an operation on each request and return a data processing result to an error control processor as an error monitoring response.”; pg. 5, paragraph 2 “. . . the error control processor [210 stores] a data processing request time . . . and a response time . . . for a data processing request . . .”); . . .
each monitoring core processor in the plurality of monitoring core processors is communicatively coupled to each of the plurality of monitoring core processors (see Kim at least Figure 3- monitoring cores 210, 230, and 240 are in communication with each other); and
executing, using the at least one monitoring core processor, based on the monitoring, at least one action responsive to at least one communication received from the at least another monitoring core processor (see Kim at least pg. 5, paragraph 3, “Finally, the error monitoring processor [210 saves] at least the time of data input / output to a monitoring system, the data processing request time, the data processing result request time and the error issuing time and using it monitors the communication speed, the delay gate and the quality of service (QoS) [(i.e., responsive action)].”).
While Kim discloses monitoring cores communicatively coupled to each other, it does not appear to explicitly disclose the monitoring processors being co-located. And while Kim discloses performance core processors, it does not appear to explicitly disclose that the performance processors are configured to execute performance core processes.
Baumeister teaches that multi-core processing systems are an alternative to multi-chip processing systems (see Baumeister at least [0007] “Microcontrollers (MCU) . . . are, from the view of the programming model, a single core system, but frequently a plurality of processor cores are physically present in order to bring about parallel software implementation. Resources such as, for example, memory resources and/or peripheral resources, are, however, frequently not implemented multiple times and are shared by the processor cores. In contrast to this, multi-chip microcontrollers make available the entire resources multiple times.”).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention with a reasonable expectation of success to have modified the multi-core processing system and communicatively coupled monitoring cores of Kim with the single-chip multi-core processing as taught by Baumeister to have the monitoring processors be co-located. Doing so would reduce cost by reducing the number of integrated circuits required by the processing system and reducing the complexity of the processing system implementation, as recognized by Baumeister (see Baumeister at least [0009] “. . . multi-chip systems are, however, more expensive compared to multi-core systems . . . The use of a plurality of chips for high-availability systems therefore constitutes a significant increase in the costs, to which, in particular, a larger number of integrated circuits and increased complexity of the underlying circuit carrier contribute.”).
While Kim and Baumeister disclose performance core processors, they do not appear to explicitly disclose that the performance processors are configured to execute performance core processes.
Chynoweth teaches the subject matter underlined below:
. . . each performance core processor in the plurality of performance core processors is configured to execute one or more performance core processes (see Chynoweth at least [0113] “For perceptual computing and other purposes, various sensors may be present within the system and may be coupled to processor 1410 in different manners . . . these sensors may include an accelerometer 1441, an ambient light sensor (ALS) 1442, a compass 1443 and a gyroscope 1444.”); . . .
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention with a reasonable expectation of success to have modified the performance core processors of Kim with the performance core processes as taught by Chynoweth to have each performance core processor configured to execute a performance core process. Doing so would align the monitored performance processors with a functional purpose.
Regarding claim 11, Kim, Baumeister, and Chynoweth disclose the analogous subject matter to claim 9 as recited in the claim and applied above. Additionally, Kim discloses the subject matter indicated in bold below:
. . . wherein each monitoring core processor in the plurality of monitoring core processors is coupled with the at least one corresponding performance core processor (see Kim at least Figure 3- processors 320 and 330 are coupled to 230, and processors 340 and 350 are coupled to 240).
While Kim discloses multi-core processing systems and coupling monitoring core processors with performance core processors, it does not appear to explicitly disclose the monitoring core processors being co-located using a common integrated circuit.
Baumeister teaches that multi-core processing systems are an alternative to multi-chip processing systems (see Baumeister at least [0007] “Microcontrollers (MCU) . . . are, from the view of the programming model, a single core system, but frequently a plurality of processor cores are physically present in order to bring about parallel software implementation. Resources such as, for example, memory resources and/or peripheral resources, are, however, frequently not implemented multiple times and are shared by the processor cores. In contrast to this, multi-chip microcontrollers make available the entire resources multiple times.”).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention with a reasonable expectation of success to have modified the multi-core processing system and processing core-coupled monitoring cores of Kim with the single-chip multi-core processing as taught by Baumeister to have the monitoring processors be co-located by a common integrated circuit. The examiner supplies the same rationale for the combination of these references as supplied with regard to claim 2 above.
Regarding claim 12, Kim, Baumeister, and Chynoweth disclose the analogous subject matter to claim 11 as recited in the claim and applied above.
While Kim discloses performance cores, it does not appear to explicitly disclose that the performance core processes are associated with a sensing device of a vehicle.
Chynoweth teaches the subject matter underlined below:
. . . wherein the one or more performance core processes is associated with an operation of at least one sensing device of a vehicle, the at least one sensing device comprising at least one of the following: a camera, a motion sensor (see Chynoweth at least [0113] “For perceptual computing and other purposes, various sensors may be present within the system and may be coupled to processor 1410 in different manners . . . these sensors may include an accelerometer 1441, an ambient light sensor (ALS) 1442, a compass 1443 and a gyroscope 1444.”), an image capturing device, a scanner, a keypad sensing device, a LiDAR, a radar, a microphone, an ultrasonic sensor, an inertial sensor, a GPS receiver, an odometry sensor, and any combination thereof.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention with a reasonable expectation of success to have modified the performance core processors of Kim with the motion sensor-associated performance core processes as taught by Chynoweth to have a performance core process associated with an operation of at least one sensing device of a vehicle, the sensing device(s) comprising at least a motion sensor. The examiner supplies the same rationale for the combination of these references as supplied with regard to claim 3 above.
Regarding claim 15, Kim, Baumeister, and Chynoweth disclose the analogous subject matter to claim 9 as recited in the claim and applied above. Additionally, Kim discloses the subject matter indicated in bold below:
. . . detecting a failure of the at least another monitoring core processor (see Kim at least pg. 6, paragraph 4 “. . . in the quality of service (QoS) mode, the monitoring module may . . . detect whether a problem is caused by a communication error or an operation error when a problem occurs.”; pg. 6, paragraph 9 “. . . through the QoS mode, the error monitoring processor measures 210 the read / write operation time of the buffer as described above . . .”);
using at least a third monitoring core processor in the plurality of monitoring core processors to monitor the one or more monitoring processes previously executed by at least another monitoring core processor based on the detected failure (see Kim at least pg. 4, paragraph 10 “. . . the error monitoring processor 210 [(i.e., third monitoring core processor) monitors] Errors of the multitude of multi-core processors 230 and 240[.] In particular, the error monitoring processor [210 transmits] an error control signal requesting the plurality of multi-core processors 230 and 240 . . .”; pg. 5, paragraph 1 “The first multi-core processor 230 receives an error monitoring signal which is a request from the error monitoring processor 210 and after performing an operation on the request in each of the first processor 320 and the second processor 330[,] This sends the data processing result to the error monitoring processor 210[.]”); and
receiving the at least one communication from the third monitoring core processor (see Kim at least pg. 5, paragraph 1 “The first multi-core processor 230 receives an error monitoring signal which is a request from the error monitoring processor 210 [(i.e., third monitoring core processor)] . . .”).
Regarding claim 16, Kim, Baumeister, and Chynoweth disclose the analogous subject matter to claim 9 as recited in the claim and applied above. Additionally, Kim discloses the subject matter indicated in bold below:
. . . wherein the one or more monitoring processes are executed using at least one predetermined execution pattern (see Kim at least Figure 5- monitoring process flow diagram shown to execute in ordered steps).
Regarding claim 17, Kim, Baumeister, and Chynoweth disclose the analogous subject matter to claim 9 as recited in the claim and applied above. Additionally, Kim discloses the subject matter indicated in bold below:
. . . wherein the at least one action comprises at least one of the following: adjusting execution of the one or more performance core processes (see Kim at least pg. 7, paragraph 12 “. . . if any operation request times are not met, the fault monitoring system will run 200 error counting through, and if the number of error counters exceeds a predetermined threshold, may . . . reset the associated multi-core processor [(i.e., adjust execution of core processes)].”), adjusting execution of the one or more monitoring core processes, executing no action, and any combination thereof.
Claims 4 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Baumeister and further in view of Chynoweth and Marasigan et al. (US 11097735 B1; hereinafter Marasigan).
Regarding claim 4, Kim, Baumeister, and Chynoweth disclose the analogous subject matter to claim 1 as recited in the claim and applied above.
While Kim discloses performance cores, it does not appear to explicitly disclose a performance core process that is associated with execution of a maneuver of a vehicle.
Marasigan teaches the subject matter indicated with dashed underline below:
. . . wherein the one or more performance core processes is associated with execution of at least one maneuver of a vehicle (see Marasigan at least pg. 43, col. 21, lines 51-67, col. 22, lines 1-21 “The processor 104 may execute the machine-readable instructions 196D to maneuver the transport to a second lane to pass the first transport in the first lane. The processor 104 may execute the machine-readable instructions 196E to maneuver the transport to the first lane when there are no other transports traveling in the first lane at a third distance behind the first transport and at or near the speed of the second transport.”).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention with a reasonable expectation of success to have modified the performance core processors of Kim with the vehicle maneuver-associated performance core processes as taught by Marasigan to have a performance core process associated with execution of at least one maneuver of a vehicle. Doing so would enable control of vehicle movement, as recognized by Marasigan (see Marasigan at least pg. 43, col. 21, lines 51-67, col. 22, lines 1-21 “The processor 104 may execute the machine-readable instructions 196D to maneuver the transport to a second lane to pass the first transport in the first lane. The processor 104 may execute the machine-readable instructions 196E to maneuver the transport to the first lane when there are no other transports traveling in the first lane at a third distance behind the first transport and at or near the speed of the second transport.”).
Regarding claim 13, Kim, Baumeister, and Chynoweth disclose the analogous subject matter to claim 9 as recited in the claim and applied above.
While Kim discloses performance cores, it does not appear to explicitly disclose a performance core process that is associated with execution of a maneuver of a vehicle.
Marasigan teaches the subject matter indicated with dashed underline below:
. . . wherein the one or more performance core processes is associated with execution of at least one maneuver of a vehicle (see Marasigan at least pg. 43, col. 21, lines 51-67, col. 22, lines 1-21 “The processor 104 may execute the machine-readable instructions 196D to maneuver the transport to a second lane to pass the first transport in the first lane. The processor 104 may execute the machine-readable instructions 196E to maneuver the transport to the first lane when there are no other transports traveling in the first lane at a third distance behind the first transport and at or near the speed of the second transport.”).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention with a reasonable expectation of success to have modified the performance core processors of Kim with the vehicle maneuver-associated performance core processes as taught by Marasigan to have a performance core process associated with execution of at least one maneuver of a vehicle. The examiner supplies the same rationale for the combination of these references as supplied with regard to claim 4 above.
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Baumeister and further in view of Chynoweth and Yigzaw et al. (US 20170123872 A1; hereinafter Yigzaw).
Regarding claim 5, Kim, Baumeister, and Chynoweth disclose the analogous subject matter to claim 1 as recited in the claim and applied above. Additionally, Kim discloses the subject matter indicated in bold below:
. . . wherein the at least one communication comprises an error report identifying at least one error associated with execution of the one or more performance core processes and detected by the at least another monitoring core processor (see Kim at least pg. 5, paragraph 3 “Finally, the error monitoring processor saves 210 at least the time of data input / output to a monitoring system, the data processing request time, the data processing result request time and the error issuing time and using it monitors the communication speed, the delay gate and the quality of service (QoS).”; pg. 6, paragraph 4 “On the other hand, in the quality of service (QoS) mode, the monitoring module may 410 detect whether a problem is caused by a communication error or an operation error when a problem occurs.”).
While Kim discloses an error report identifying an error associated with execution of the performance core processes, it does not appear to explicitly disclose that the error report is part of the communication.
Yigzaw teaches the subject matter indicated with bolded underline below:
. . . wherein the at least one communication comprises an error report identifying at least one error associated with execution of the one or more performance core processes (see Yigzaw at least [0091] “. . . the processor further comprises a system agent circuit to receive an indication of the error within the block range from a non-volatile controller coupled to the non-volatile block storage and to report the error to the core, the core to store the error indicator in the block status storage responsive to the error report.”) . . .
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention with a reasonable expectation of success to have modified the error reporting of Kim with the error report communications as taught by Yigzaw to have the error report be part of the communication. Doing so would further distribute the monitoring processes and associated computational load across monitoring core resources.
Regarding claim 14, Kim, Baumeister, and Chynoweth disclose the analogous subject matter to claim 1 as recited in the claim and applied above. Additionally, Kim discloses the subject matter indicated in bold below:
. . . wherein the at least one communication comprises an error report identifying at least one error associated with execution of the one or more performance core processes and detected by the at least another monitoring core processor (see Kim at least pg. 5, paragraph 3 “Finally, the error monitoring processor saves 210 at least the time of data input / output to a monitoring system, the data processing request time, the data processing result request time and the error issuing time and using it monitors the communication speed, the delay gate and the quality of service (QoS).”; pg. 6, paragraph 4 “On the other hand, in the quality of service (QoS) mode, the monitoring module may 410 detect whether a problem is caused by a communication error or an operation error when a problem occurs.”).
While Kim discloses an error report identifying an error associated with execution of the performance core processes, it does not appear to explicitly disclose that the error report is part of the communication.
Yigzaw teaches the subject matter indicated with bolded underline below:
. . . wherein the at least one communication comprises an error report identifying at least one error associated with execution of the one or more performance core processes (see Yigzaw at least [0091] “. . . the processor further comprises a system agent circuit to receive an indication of the error within the block range from a non-volatile controller coupled to the non-volatile block storage and to report the error to the core, the core to store the error indicator in the block status storage responsive to the error report.”) . . .
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention with a reasonable expectation of success to have modified the error reporting of Kim with the error report communications as taught by Yigzaw to have the error report be part of the communication. The examiner supplies the same rationale for the combination of these references as supplied with regard to claim 5 above.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Baumeister and further in view of Chynoweth and Siewiorek (Siewiorek, D. P. (1984). Architecture of fault-tolerant computers. Computer, 17(08), 9-18.; hereinafter Siewiorek).
Regarding claim 20, Kim, Baumeister, and Chynoweth disclose the analogous subject matter to claim 9 as recited in the claim and applied above.
While Kim discloses a plurality of monitoring core processors and the monitoring of processors in the plurality of monitoring core processors for failure (see Kim at least pg. 4, paragraph 10 “. . . the error monitoring processor 210 [monitors] Errors of the multitude of multi-core processors 230 and 240 [(i.e., plurality of monitoring core processors)] . . .”; pg. 7, paragraph 14 “. . . it is possible to determine not only a processing kernel in which a problem occurs in a multi-core system, but also to determine whether the cause of the problem is an operation error . . .”), it does not appear to explicitly disclose a monitoring core processor of the plurality of monitoring core processors serving as a backup monitor that performs operations of a failing monitoring core processor of the plurality of monitoring core processors.
Siewiorek teaches the subject matter underlined below:
. . . wherein a core processor of the plurality of core processors serves as a backup processor that performs operations of a failing core processor of the plurality of core processors (see at least pg. 17, col. 1, paragraph 1 “. . . the active processor runs a self-diagnostic program. If the diagnostic fails, control is passed to the standby processor.”).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention with a reasonable expectation of success to have modified the plurality of monitoring core processors and the monitoring of processors in the plurality of monitoring core processors for failure of Kim with the core processor of the plurality of core processors serving as a backup processor that performs operations of a failing core processor of the plurality of core processors as taught by Siewiorek to have a monitoring core processor of the plurality of monitoring core processors serve as a backup monitor that performs operations of a failing monitoring core processor of the plurality of monitoring core processors. Doing so would provide the system with fault tolerance.
Response to Arguments
Applicant's arguments filed 01/12/2026 have been fully considered but they are not persuasive.
Applicant argues, “The Applicant does not concede the correctness of the Examiner's assertions. However, to expedite prosecution, the Applicant has amended the claims to include the subject matter of claims 18 and 19. The Examiner errs by asserting that "cores 230 and 240 must perform a data processing operation and extract data to send, which is inherently a form of monitoring within each of the cores 230 and 240." Kim explicitly assigns monitoring roles to error monitoring processor 210 and data processing/control roles to multi-core processors 230 and 240. Kim describes that error monitoring processor 210 conducts monitoring (queries, timing capture, speed/delay/QoS analysis). Kim provides that it ‘monitors the error monitoring processor 210 Errors of the multitude of multi-core processors 230 and 240.’ Kim, p. 4, para. 3; (Errors in original). Kim also provides ‘[f]inally, the error monitoring processor 210 saves ... and using it monitors the communication speed, the delay ... and QoS.’ Kim, p. 4, para. 3. With respect to processors 230 and 240, Kim provides the ‘multitude of multi-core processors 230 and 240 perform an operation on each request and return a data processing result to an error control processor as an error monitoring response. Preferably, each of the processors performs 320 . 330 . 340 and 350 the multi-core processors 230 and 240 an operation on each request.’ Kim, p. 4, para. 4.
“Kim plainly draws a functional line where error monitoring processor 210 monitors while processors 230 and 240 execute operations. The Examiner fails to identify any teaching in Kim that characterizes processors 230 and 240 as monitoring processors. One of ordinary skill in the art would recognize that performing an operation and returning data for another processor's monitoring is not the same as performing monitoring itself. Put another way, monitoring is not necessarily present or inevitable when ‘perform[ing] a data processing operation and extract[ing] data to send.’ MPEP 2112 provides that ‘[i]n relying upon the theory of inherency, the examiner must provide a basis in fact and/or technical reasoning to reasonably support the determination that the allegedly inherent characteristic necessarily flows from the teachings of the applied prior art.’ MPEP 2112; (Emphasis in original). Kim plainly describes centralized monitoring at the error monitoring processor 210. The Examiner fails to provide a basis in fact and/or technical reasoning to reasonably support the determination that the allegedly inherent monitoring necessarily flows from the data processing by processors 230 and 240 of Kim. For at least this reason, the present claims are allowable over the cited art,” (from remarks pg. 8-9).
As to Point (A), Examiner respectfully disagrees. The Applicant appears to argue that monitoring is not necessarily present or inevitable when “perform[ing] a data processing operation and extract[ing] data to send” via a processor, and as such, the argument of inherency used to support the rejection of the claims under 35 U.S.C. 103 is invalid. Under the broadest reasonable interpretation of the claims, monitoring means to watch, keep track of, observe, or check something, usually but not always for a special purpose. In order to perform a data processing operation and extract data to send in a processor, the processor must necessarily monitor the data it handles in that it is watching, tracking, observing, or checking data for the special purpose of data processing and extraction. If a processor were unable to monitor the data it handles, then these processes would necessarily be inoperable since the data must be watchable, trackable, observable, or otherwise checkable to the processor to be operated upon in the manners described by the Kim reference. That there are other monitoring functions performed by processors that are explicitly labeled “monitoring” in the prior art does not negate that other functions described, despite being labeled differently, necessarily require a monitoring process to function. See MPEP §2111 for more information on interpreting claims under their broadest reasonable interpretation consistent with the specification.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Swanson et al. (US 11036543 B1) discloses error checking methodologies for multicore processors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TABITHA KRESS whose telephone number is (703) 756-1763. The examiner can normally be reached MTWR 06:30-16:30 CST.
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/TABITHA KRESS/Examiner, Art Unit 3667
/Hitesh Patel/Supervisory Patent Examiner, Art Unit 3667
6/1/26
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