DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The instant application having Application No. 18/139,912 has a total of 20 elected claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
INFORMATION CONCERNING OATH/DECLARATION
Oath/Declaration
The applicant’s oath/declaration has been reviewed by the examiner and is found to conform to the requirements prescribed in 37 C.F.R. 1.63.
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(C), the applicant’s submissions of the Information Disclosure Statements 04/26/2023, 02/13/2024 and 03/20/2025 are acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kollu (US pub. 2017/0052916), hereinafter, “Kollu”.
At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references.
2. As per claim 1, Kollu discloses a computer system, comprising: a host means (processor complex 702 of fig. 8 combined with computer connected to serial interface 875 or ethernet PHY 885, as discloses in paragraph 0040) comprising a host memory space (see fig. 8); and a non-volatile memory (NVM) device (the combination of switch core 456/895, port 452 and chassis 600 of fig. 7. Looking at fig. 8, see paragraph 0042, which states that port 882 is connected to retimer 606/host 602, which has the SSD , and paragraph 0038, which discloses “FIG. 6 is an illustration of 1 U chassis 600 containing an array of hosts 500. In a typical configuration the 1 U chassis 600 would be 1.75″ high, 15″ wide and 17″ deep. A host array 602 of hosts 500 are connected to PCIe fabric switches 640, which are connected to PCIe retimers 606. The PCIe retimers 606 are connected to top-of-rack switch 450”) comprising a NVM (PCIe NVME SSD storages 516 of the host arrays 602 of figs. 5-7, as disclose in paragraphs 0037, 0038 and 0040) and a controller (control subsystem 825 of fig. 8) coupled to the NVM (see figs. 5-8), wherein the host means is configured to dynamically activate (in fig. 8, see path from processor complex 702 to port 882 via 825, 830 and 835, not bypassing 830, leading to SSD inside chassis 600, host 602, as also disclose in fig. 7 and paragraphs 0040 and 0041; in other words, 830, being a part of ‘NVM’ is ‘activated’ by having data goes through it) and deactivate (in fig. 8, see path from processor complex 702 to port 882 via 825 and 835, bypassing 830, leading to SSD inside chassis 600, host 602, as also disclose in fig. 7. in other words, 830, being a part of ‘NVM’ is ‘deactivated’ by having data goes bypassed it) one or more portions of the NVM mapped to the host memory space for direct access by the host means (see figs. 6 and 7, which show two direct PCIe points along the path between processor complex 702 and host array 602).
3. As per claim 2, Kollu discloses “The computer system of claim 1” [See rejection to claim 1 above], wherein the host means is operable to access the NVM device through a memory aperture mapped into the host memory space (see claim 1 of Kollu or paragraph 0041, which discloses “The translate block 826 examines the frame header and performs any necessary address translations. There can be various embodiments of the translation block 826, with examples of translation operation provided in U.S. Pat. No. 7,752,361 and U.S. Pat. No. 7,120,728, both of which are incorporated herein by reference in their entirety. Those examples also provide examples of the control/data path splitting of operations. The router block 827 examines the frame header and selects the desired output port for the frame. The filter block 828 examines the frame header, and the payload header in some cases, to determine if the frame should be transmitted. In the preferred embodiment of the present invention, hard zoning is accomplished using the filter block 828. The queuing block 829 schedules the frames for transmission based on various factors including quality of service, priority and the like”).
4. As per claim 3, Kollu discloses wherein the host means includes a communication link linking the NVM to a memory aperture in the host memory space (see paragraph 0037).
5. As per claim 4, Kollu discloses wherein the host means is operable to send load/store commands to the host memory space to access the NVM (see paragraphs 0056 and 0064).
6. As per claim 5, Kollu discloses wherein the host means is further configured to establish driver access to the NVM (see fig. 10B).
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 6-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Kollu (US pub. 2017/0052916), hereinafter, “Kollu”, in view of Boyd et al. (US pub. # 2016/0162416), hereinafter, “Boyd”.
9. As per claim 6, Kollu discloses “The computer system of claim 1” [See rejection to claim 1 above], but fails to expressly discloses wherein the host means comprises a dynamic random access memory (DRAM) and a NVM express (NVMe) driver.
Boyd discloses wherein the host means comprises a dynamic random access memory (DRAM) and a NVM express (NVMe) driver (see fig. 2).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Boyd’s teaching of a system compromising a storage device, a bus, and a host apparatus including a host memory and a driver module, wherein the host apparatus is coupled to the storage device via the bus, wherein the driver module is operable to: retrieve a logical to physical address mapping from the host memory; and provide the logical to physical address mapping to the storage device via the bus along with a read or write operation request, into Kollu’s teaching of a host connected to storage devices via switches using a PCI Express (PCIe) link, for the ability/benefit of integrating a DRAM within the host for writing to the storage device such that latency between the host and the storage device is reduced.
10. As per claims 7 and 12, Kollu discloses a non-volatile memory (NVM) device (the combination of switch core 456/895, port 452 and chassis 600 of fig. 7. Looking at fig. 8, see paragraph 0042, which states that port 882 is connected to retimer 606/host 602, which has SSD, and paragraph 0038, which discloses “FIG. 6 is an illustration of 1 U chassis 600 containing an array of hosts 500. In a typical configuration the 1 U chassis 600 would be 1.75″ high, 15″ wide and 17″ deep. A host array 602 of hosts 500 are connected to PCIe fabric switches 640, which are connected to PCIe retimers 606. The PCIe retimers 606 are connected to top-of-rack switch 450”), comprising: a NVM (PCIe NVME SSD storages 516 of the host arrays 602 of figs. 5-7, as disclose in paragraphs 0037, 0038 and 0040); and a controller (switch core 895, media interface 880 and port 882, combined) coupled to the NVM (see figs. 5-8), wherein the controller comprises an anomaly detector module (PCIe port 1240, as discloses in paragraph 0051) and is configured to: establishing a peripheral component interface express (PCIe) link with a host (see fig. 12B and paragraph 0051); negotiate an alignment size of a minimum transaction packet size to load/store commands with the host (‘negotiate an alignment size of a minimum transaction packet size’ is being equated to having a transmitted packet, which has a size of data; therefore, see paragraph 0051. Note, the claim language doesn’t disclose how a ‘negotiation’ takes place, or having different sizes of data); initializing a PCIe memory space mapping of one or more portions of the NVM of the NVM device to a host memory space through the PCIe link between the host and the NVM device (see paragraph 0041 and paragraph 0051, which discloses “The queues 1228 and 1230 allow direct mapping between buffers in host memory and the queues 1228 and 1230 if desired. Packets coming from the fabric 1266 are provided to a memory 1226 in the memory block 1222 and then to the queues 1228. Packets are provided from the queues 1228 and memory 1226 to a fabric receive to PCIe transmit packet processor and framing hardware assist 1210. The packet processor and framing hardware assist 1210 performs the header conversion for the Ethernet to PCIe transfer and other conventional egress packet processor functions, in conjunction with the IOH 1220 and the control of the CPU 1218”); and routing data through the PCIe link by addressing the PCIe memory space mapping the one or more portion of the NVM of the NVM device (see paragraphs 0056 and 0064).
but fails to expressly discloses wherein the routing comprises utilizing driverless access for received load/store commands and address translation.
Boyd discloses wherein the routing comprises utilizing driverless access for received load/store commands and address translation (see abstract and paragraph 0053 of Boyd and fig. 6 which shows direct data transfer via dashed lines 606 and 607).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Boyd’s teaching of a system compromising a storage device, a bus, and a host apparatus including a host memory and a driver module, wherein the host apparatus is coupled to the storage device via the bus, wherein the driver module is operable to: retrieve a logical to physical address mapping from the host memory; and provide the logical to physical address mapping to the storage device via the bus along with a read or write operation request, into Kollu’s teaching of a host connected to storage devices via switches using a PCI Express (PCIe) link, for the ability/benefit of reducing latency, lowering power consumption, and increasing performance.
11. As per claim 8, the combination of Kollu and Boyd discloses “The NVM device of claim 7” [See rejection to claim 7 above], wherein the controller is configured to execute the load/store commands sequentially (see paragraph 0051 of Kollu).
12. As per claims 9 and 13, Kollu discloses wherein the controller is configured to execute the load/store commands in parallel to read/write commands in different portions of the NVM (see fig. 7 and paragraph 0070).
13. As per claim 10, Kollu discloses wherein the anomaly detector module (PCIe port 1240 of fig. 12B) comprises: a parameter tracking module (CPU 1218); a normal-pattern fitting module (framing hardware assist 1208); and an anomaly determination module (framing hardware assist 1210) (note, an ‘anomaly detector module’ is not a well-known term in the art).
14. As per claim 11, Kollu discloses wherein the anomaly detector module comprises a countermeasure module (IOH 1220).
15. As per claim 14, the combination of Kollu and Boyd discloses “The NVM device of claim 12” [See rejection to claim 12 above], wherein a first portion of the NVM is allocated for the driverless access and a second portion of the NVM is allocated for the driver access (see fig. 6 of Boyd).
16. As per claim 15, the combination of Kollu and Boyd discloses “The NVM device of claim 14” [See rejection to claim 14 above], wherein the first portion and the second portion are distinct (see fig. 1 of Boyd).
17. As per claim 16, the combination of Kollu and Boyd discloses “The NVM device of claim 14” [See rejection to claim 14 above], wherein at least a portion of the first portion and at least a portion of the second portion correspond to a same portion(see fig. 1 of Boyd).
18. As per claim 17, the combination of Kollu and Boyd discloses “The NVM device of claim 16” [See rejection to claim 16 above], wherein, for the same portion, the driver access is active when the driverless access inactive and the driver access is inactive when the driverless access is active (see fig. 6 and paragraph 0044 of Boyd).
19. As per claim 18, the combination of Kollu and Boyd discloses “The NVM device of claim 12” [See rejection to claim 12 above], wherein the controller is further configured to establish, with the host, an alignment size of a minimum transaction packet size for the load/store commands received from the host using driverless access (see fig. 6 and paragraphs 0035 and 0044 of Boyd).
20. As per claim 19, the combination of Kollu and Boyd discloses “The NVM device of claim 12” [See rejection to claim 12 above], wherein wherein the controller is further configured to: track one or more parameters associated with the received load/store commands, wherein the one or more parameters comprises: a logical block address (LBA) range accessed associated with the received load/store commands; a timing of the received load/store commands (see paragraph 0028 of Boyd); a size of data accessed in the received load/store commands; an originating source of the received load/store commands; a type of access command of the received load/store commands; and contents of data programmed or read associated with the received load/store commands.
21. As per claim 20, the combination of Kollu and Boyd discloses “The NVM device of claim 19” [See rejection to claim 19 above], wherein the controller is further configured to: determine that the tracked one or more parameters exceeds a threshold; and implement a countermeasure based on a parameter exceeding the threshold responsive to the determining (see paragraph 0044 of Boyd).
CLOSING COMMENTS
CONCLUSION
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the
application as recommended by M.P.E.P. 707.07(i):
a (1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received a first action on the merits and are subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the
Examiner should be directed to Ernest Unelus whose telephone number is (571) 272-
8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
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/Ernest Unelus/
Primary Examiner
Art Unit 2181