DETAILED ACTION
Response to Arguments
Applicant’s arguments, see “Claim Rejections - 35 U.S.C. § 102” on pg 7 of 8, filed 7 Jul 2026, with respect to the rejections of claims 1-2 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Prodic (US 20080204160 A1) in view of Woo (US 20150309529 A1).
Applicant’s arguments, see “Claim Rejections - 35 U.S.C. § 102” on pg 7 of 8, filed 7 Jul 2026, with respect to the rejections of claims 8-9 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Prodic (US 20080204160 A1) in view of Ware (US 6675272 B2) and further in view of Woo (US 20150309529 A1).
Applicant’s arguments, see “Claim Rejections - 35 U.S.C. § 102” on pg 7 of 8, filed 7 Jul 2026, with respect to the rejections of claims 15-16 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Prodic (US 20080204160 A1) in view of Ware (US 6675272 B2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Prodic (US 20080204160 A1) in view of Woo (US 20150309529 A1).
Regarding Claim 1, Prodic discloses an An apparatus (Fig 1) comprising: a multiphase power converter (100, Fig 1) including first phase circuitry (Power Stage 1, Fig 1) and second phase circuitry (Power Stage 2, which is not shown in full but as a generic copy stacked behind Power Stage 1, Fig 1), the first phase circuitry coupled between a power input and a power output and has a first control input (Power Stage 1 is connected between Vg(t) input and Vout(t) and has a control input C1(t), Fig 1), and the second phase circuitry coupled between the power input and the power output and has a second control input (Power Stage 2 is connected between Vg(t) input and Vout(t) and has a control input C2(t), Fig 1); and controller circuitry having inputs (Universal MDPWM Controller IC has inputs V2_(t), V3_(t), V4_(t), ext clk, and Protection, Fig 1), a first control output (C1(t), Fig 1), and a second control output (C2(t), Fig 1), the first control output coupled to the first control input (C1(t) is connected between the output of the controller and the input of Power Stage 1, Fig 1), the second control output coupled to the second control input (C2(t) is connected between the output of the controller and the input of Power Stage 2, Fig 1); and transmit a first pulse at the first control output at the first time (the Phase Angle input to SP module of Fig 2 interleaves the phases and sends out SP1/Start P1 to trigger phase 1's RS latch to cause C1(t) to go high at a different time from other phases as shown in Fig 3A/B, Figs 2 & 3A/B, [0037-9 & 59]), and transmit a second pulse at the second control output at the second time (the Phase Angle input to SP module of Fig 2 interleaves the phases and sends out SP2/Start P2 to trigger phase 2's RS latch to cause C2(t) to go high at a different time from other phases as shown in Fig 3A/B, Figs 2 & 3A/B, [0037-9 & 59]).
Prodic does not disclose the controller circuitry configurable to: determine first and second times responsive to a difference between a first propagation delay between the first control output and the first control input and a second propagation delay between the second control output and the second control input.
Woo teaches a conventional propagation-delay-responsive control-pulse timing adjustment for use in a system where a common controller transmits timed signals to multiple destination circuits over paths of differing propagation delay (see Fig 5A) including a controller circuitry configurable to: determine first and second times ("first module is configured to start storing said data element at a first time and said second module is configured to start storing said data element at a second time respectively", Claim 8) responsive to a difference between a first propagation delay between the first control output and the first control input and a second propagation delay between the second control output and the second control input ("To compensate the propagation delay (Δt) of the data signals along the data buses, the memory controller activates the clock and control signals for module B (CK_B 623, CMD_B 624, ADDRESS_B 625, and chip select signal (not shown)) relative to when the data and strobe signals reach module B. More specifically, as shown, a time offset Δt is added between CMD_A and CMD_B (see 605 and 606), between CK_A and CK_B (see 607 and 608), and between ADDRESS_A and ADDRESS_B (see 609 and 610).", [0053]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the propagation-delay-responsive control-pulse timing adjustment in Prodic, as taught by Woo, as it provides the advantage of compensating for unequal signal path delays so that control/data transitions arrive at their respective destinations in proper timing alignment ([0053] of Woo).
Regarding Claim 2, the combination of Prodic and Woo discloses all of the limitations of claim 1, and further discloses wherein the first phase circuitry and the second phase circuitry are spaced from the controller circuitry by different distances ("data buses have different trace lengths between said memory controller and said first module and between said memory controller and said second module.", Claim 13 of Woo).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Prodic (US 20080204160 A1) in view of Ware (US 6675272 B2) and further in view of Woo (US 20150309529 A1).
Regarding Claim 8, Prodic discloses a determine first and second times responsive to a first propagation delay and a second propagation delay (the Phase Angle inputs to SP module of Fig 2 interleaves the phases and sends out SP1/Start P1 to trigger phase 1's RS latch to cause C1(t) to go high at a different time from phase 2's C2(t) as shown in Fig 3A/B, Figs 2 & 3A/B, [0037-9 & 59]) and first phase circuitry (Power Stage 1, Fig 1) of a multiphase power converter (100, Fig 1) and second phase circuitry of the multiphase power converter (Power Stage 2 of 100, Fig 1); transmit a first pulse to the first phase circuitry at the first time (the Phase Angle input to SP module of Fig 2 interleaves the phases and sends out SP1/Start P1 to trigger phase 1's RS latch to cause C1(t) to go high at a different time from other phases as shown in Fig 3A/B, Figs 2 & 3A/B, [0037-9 & 59]); and transmit a second pulse to the second phase circuitry at the second time (the Phase Angle input to SP module of Fig 2 interleaves the phases and sends out SP1/Start P1 to trigger phase 1's RS latch to cause C1(t) to go high at a different time from other phases as shown in Fig 3A/B, Figs 2 & 3A/B, [0037-9 & 59]).
Prodic does not disclose non-transitory machine-readable storage medium comprising instructions that, when executed, configure processor circuitry to at least: times responsive to a difference between a first propagation delay between the processor circuitry and first phase circuitry and a second propagation delay between the processor circuitry and second phase circuitry.
Ware teaches a path delay adjustment technique for use in a system with a central controller that transmits multiple timed signals over paths of different lengths (Fig 2) including determine first and second times ("a memory device positioned a first distance from the controller will have a different set of characteristic delays with respect to signals communicated with the controller than a second memory device positioned at a second position.", Col 23[9-13]) responsive to a difference between a first propagation delay between the processor circuitry and first phase circuitry (slice 1's memory component 116 along it's individual data bus 108 from 102, Fig 2) and a second propagation delay between the processor circuitry and second phase circuitry (slice Ns's memory component 118 along it's individual data bus 108 from 102, Fig 1) ("The cost of this phasing decision is that the controller must adjust the read and write clocks for each slice to different phase values", Col 16[8-12]); transmit a first pulse to the first phase circuitry at the first time (722, Fig 7); and transmit a second pulse to the second phase circuitry at the second time (741, Fig 7).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the path delay adjustment technique in Prodic, as taught by Ware, as it provides the advantage of compensating for propagation delays in systems with unequal path length.
Ware does not teach a non-transitory machine-readable storage medium comprising instructions.
Wu teaches a conventional instruction-based, processor-executed control implementation for use in a multiphase power converter (see Fig 7-8) including a non-transitory machine-readable storage medium comprising instructions ("the example processes of FIGS. 7 and 8 may be implemented using coded instructions (e.g., computer and/or machine readable instructions) stored on a non-transitory computer and/or machine readable medium", [0060]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the instruction-based, processor-executed control implementation in Prodic, as taught by Wu, as it provides the advantage of enabling the converter control algorithm to be reconfigurable.
Regarding Claim 9, the combination of Prodic, Ware, and Woo discloses all of the limitations of claim 8, and further discloses a wherein the first phase circuitry and the second phase circuitry are spaced from the processor circuitry by different distances the physical positioning of the memory devices with respect to the controller ("Thus, a memory device positioned a first distance from the controller will have a different set of characteristic delays with respect to signals communicated with the controller than a second memory device positioned at a second position.", Col 23[8-14] of Ware).
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Prodic (US 20080204160 A1) in view of Ware (US 6675272 B2).
Regarding Claim 15, Prodic discloses a method (method of operating a multiphase digital pwm controller, Fig 1) comprising: controller circuitry (Universal MDPWM Controller IC, Fig 1) and first phase circuitry (Power Stage 1, Fig 1) of a multiphase power converter (100, Fig 1) and second phase circuitry of the multiphase power converter (Power Stage 2 of 100, Fig 1); transmitting, by the controller circuitry, a first pulse to the first phase circuitry at the first time (the Phase Angle input to SP module of Fig 2 interleaves the phases and sends out SP1/Start P1 to trigger phase 1's RS latch to cause C1(t) to go high at a different time from other phases as shown in Fig 3A/B, Figs 2 & 3A/B, [0037-9 & 59]); and transmitting, by the controller circuitry, a second pulse to the second phase circuitry at the second time (the Phase Angle input to SP module of Fig 2 interleaves the phases and sends out SP1/Start P1 to trigger phase 1's RS latch to cause C1(t) to go high at a different time from other phases as shown in Fig 3A/B, Figs 2 & 3A/B, [0037-9 & 59]).
Prodic does not disclose determining, by controller circuitry, first and second times responsive to a difference between a first propagation delay between the controller circuitry and first phase circuitry and a second propagation delay between the controller circuitry and second phase circuitry.
Ware teaches a path delay adjustment technique for use in a system with a central controller that transmits multiple timed signals over paths of different lengths (Fig 2) including determining, by controller circuitry (102, Fig 2), first and second times ("a memory device positioned a first distance from the controller will have a different set of characteristic delays with respect to signals communicated with the controller than a second memory device positioned at a second position.", Col 23[9-13]) responsive to a difference between a first propagation delay between the controller circuitry and first phase circuitry (slice 1's memory component 116 along it's individual data bus 108 from 102, Fig 2) and a second propagation delay between the controller circuitry and second phase circuitry (slice Ns's memory component 118 along it's individual data bus 108 from 102, Fig 1) ("The cost of this phasing decision is that the controller must adjust the read and write clocks for each slice to different phase values", Col 16[8-12]); transmitting, by the controller circuitry, a first pulse to the first phase circuitry at the first time (722, Fig 7); and transmitting, by the controller circuitry, a second pulse to the second phase circuitry at the second time (741, Fig 7).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the path delay adjustment technique in Prodic, as taught by Ware, as it provides the advantage of compensating for propagation delays in systems with unequal path length.
Regarding Claim 16, the combination of Prodic and Ware discloses all of the limitations of claim 15, and further discloses wherein the first phase circuitry and the second phase circuitry are spaced from the controller circuitry by different distances ("Thus, a memory device positioned a first distance from the controller will have a different set of characteristic delays with respect to signals communicated with the controller than a second memory device positioned at a second position.", Col 23[8-14] of Ware).
REASONS FOR ALLOWANCE
Claims 3-4, 6-7, 10-11, 13-14, 17-18, & 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER C CAULK whose telephone number is (571)270-0623. The examiner can normally be reached M-F 8:30-5:30, every other Fri off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached on (571)270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.C.C./Examiner, Art Unit 2838
/GARY L LAXTON/Primary Examiner, Art Unit 2838 8/21/2026
Prosecution Insights