DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 19 Mar 2026 has been entered.
Information Disclosure Statement
The information disclosure statement submitted on 19 Mar 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 15 is objected to because of the following informalities:
Claim 15 recites the limitation "the processor circuitry" in line 4. There is insufficient antecedent basis for this limitation in the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Woo (US 20150309529 A1).
Regarding Claim 1, Woo discloses an apparatus (memory system, Fig 1A) comprising: phase circuits (DIMMs 521 & 522, Fig 5B) including first phase circuitry (521, Fig 5B) and second phase circuitry (522, Fig 5B), the first phase circuitry coupled between a power input and a power output (DIMMs are well known in the art to be connected to the motherboard's power input/output, [0017]) and has a first control input (e.g. 524 from 210, Fig 5B), and the second phase circuitry coupled between the power input and the power output (DIMMs are well known in the art to be connected to the motherboard's power input/output, [0017]) and has a second control input (e.g. 525 from 210, Fig 5B); and controller circuitry (memory controller 210, Fig 2A) having inputs ("memory controller is configured to: determine a propagation delay between said first module and said second module with respect to signals transmitted from said memory controller", the memory controller is able to determine the propagation delay by receiving information about the delay after sending signals to the DIMMs, Claim 8), a first control output (524 to DIMM, Fig 5B), and a second control output (525 to DIMM, Fig 5B), the first control output coupled to the first control input (524 from 210 to DIMM, Fig 5B), the second control output coupled to the second control input (525 from 210 to DIMM, Fig 5B); and the controller circuitry configurable to: determine first and second times ("first module is configured to start storing said data element at a first time and said second module is configured to start storing said data element at a second time respectively", Claim 8) responsive to a difference between a first propagation delay between the first control output and the first control input and a second propagation delay between the second control output and the second control input ("To compensate the propagation delay (Δt) of the data signals along the data buses, the memory controller activates the clock and control signals for module B (CK_B 623, CMD_B 624, ADDRESS_B 625, and chip select signal (not shown)) relative to when the data and strobe signals reach module B. More specifically, as shown, a time offset Δt is added between CMD_A and CMD_B (see 605 and 606), between CK_A and CK_B (see 607 and 608), and between ADDRESS_A and ADDRESS_B (see 609 and 610).", [0053]); the controller circuitry configurable to: transmit a first pulse at the first control output at the first time ("memory controller is further configured to: transmit first write command and address signals to said first DIMM at a first time", Claim 2), and transmit a second pulse at the second control output at the second time ("transmit second write command and address signals to said second DIMM at a second time, wherein said second time is delayed with respect to said first time based on the first and second signal latencies.", Claim 2).
Regarding Claim 2, Woo discloses an apparatus of claim 1, wherein the first phase circuitry and the second phase circuitry are spaced from the controller circuitry by different distances ("data buses have different trace lengths between said memory controller and said first module and between said memory controller and said second module.", Claim 13).
Claims 8-9 & 15-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ware (US 6675272 B2).
Regarding Claim 8, Ware discloses a non-transitory machine-readable storage medium comprising instructions (memory system 101, Fig 1) that, when executed, configure processor circuitry (102, Fig 2) to at least: determine first and second times ("a memory device positioned a first distance from the controller will have a different set of characteristic delays with respect to signals communicated with the controller than a second memory device positioned at a second position.", Col 23[9-13]) responsive to a difference between a first propagation delay between the processor circuitry and first phase circuitry (slice 1's memory component 116 along it's individual data bus 108 from 102, Fig 2) and a second propagation delay between the processor circuitry and second phase circuitry (slice Ns's memory component 118 along it's individual data bus 108 from 102, Fig 1) ("The cost of this phasing decision is that the controller must adjust the read and write clocks for each slice to different phase values", Col 16[8-12]); transmit a first pulse to the first phase circuitry at the first time (722, Fig 7); and transmit a second pulse to the second phase circuitry at the second time (741, Fig 7).
Regarding Claim 9, Ware discloses non-transitory machine-readable storage medium of claim 8, wherein the first phase circuitry and the second phase circuitry are spaced from the processor circuitry by different distances the physical positioning of the memory devices with respect to the controller ("Thus, a memory device positioned a first distance from the controller will have a different set of characteristic delays with respect to signals communicated with the controller than a second memory device positioned at a second position.", Col 23[8-14]).
Regarding Claim 15, Ware discloses a method (memory system 101, Fig 1) comprising: determining, by controller circuitry (102, Fig 2), first and second times ("a memory device positioned a first distance from the controller will have a different set of characteristic delays with respect to signals communicated with the controller than a second memory device positioned at a second position.", Col 23[9-13]) responsive to a difference between a first propagation delay between the controller circuitry and first phase circuitry (slice 1's memory component 116 along it's individual data bus 108 from 102, Fig 2) and a second propagation delay between the processor circuitry and second phase circuitry (slice Ns's memory component 118 along it's individual data bus 108 from 102, Fig 1) ("The cost of this phasing decision is that the controller must adjust the read and write clocks for each slice to different phase values", Col 16[8-12]); transmitting, by the controller circuitry, a first pulse to the first phase circuitry at the first time (722, Fig 7); and transmitting, by the controller circuitry, a second pulse to the second phase circuitry at the second time (741, Fig 7).
Regarding Claim 16, it is rejected for the same reasons as stated above for Claim 9.
REASONS FOR ALLOWANCE
Claims 3-4, 6-7, 10-11, 13-14, 17-18, & 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 3, Woo discloses all of the limitations of Claim 2.
Woo does not disclose, “wherein the controller circuitry has a first current sense input coupled to the first phase circuitry and a second current sense input coupled to the second phase circuitry, and the controller circuitry is configurable to: determine a first delay corresponding to an amount of time for the first pulse to reach the first phase circuitry responsive a first current sense signal at the first current sense input determine a second delay corresponding to an amount of time for the second pulse to reach the second phase circuitry responsive to a second current sense signal at the second current sense input: and determine the first and second times responsive to the first delay and the second delay.”
Prior art Ware (US 6675272 B2), Burstein (US 6031361 A), Kliza (US 5852640 A), Kuroda (US 20060077798 A1), Zhang (US 20030197245 A1) and Rice (US 7138788 B2) are considered to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “wherein the controller circuitry has a first current sense input coupled to the first phase circuitry and a second current sense input coupled to the second phase circuitry, and the controller circuitry is configurable to: determine a first delay corresponding to an amount of time for the first pulse to reach the first phase circuitry responsive a first current sense signal at the first current sense input determine a second delay corresponding to an amount of time for the second pulse to reach the second phase circuitry responsive to a second current sense signal at the second current sense input: and determine the first and second times responsive to the first delay and the second delay.”
Dependent Claims 4 & 7 are allowable by virtue of their dependency on claim 3.
Regarding Claim 6, Woo discloses all of the limitations of Claim 2, and further discloses wherein the first phase circuitry, the second phase circuitry, and the controller circuitry are mounted on a printed circuit board ("Although using separate command and address lines for the two modules requires additional pins on the associated host device and additional wires on the circuit board", [0048]).
Woo does not disclose, “the first and second phase circuitries are located on a same region of the printed circuit board relative to a location of the controller circuitry.”
Prior art Ware (US 6675272 B2), Burstein (US 6031361 A), Kliza (US 5852640 A), Kuroda (US 20060077798 A1), Zhang (US 20030197245 A1) and Rice (US 7138788 B2) are considered to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “the first and second phase circuitries are located on a same region of the printed circuit board relative to a location of the controller circuitry.”
Regarding Claim 10, Ware discloses all of the limitations of Claim 8.
Ware does not disclose “further comprising instructions that, when executed, configure the processor circuitry to: determine a first delay corresponding to an amount of time for the first pulse to reach the first phase circuitry responsive to a first current sense signal from the first phase circuitry; determine a second delay corresponding to an amount of time for the second pulse to reach the second phase circuitry responsive to a second current sense signal from the second phase circuitry; and determine the first and second times responsive to the first delay and the second delay.”
Prior art Woo (US 20150309529 A1), Burstein (US 6031361 A), Kliza (US 5852640 A), Kuroda (US 20060077798 A1), Zhang (US 20030197245 A1) and Rice (US 7138788 B2) are considered to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “further comprising instructions that, when executed, configure the processor circuitry to: determine a first delay corresponding to an amount of time for the first pulse to reach the first phase circuitry responsive to a first current sense signal from the first phase circuitry; determine a second delay corresponding to an amount of time for the second pulse to reach the second phase circuitry responsive to a second current sense signal from the second phase circuitry; and determine the first and second times responsive to the first delay and the second delay.”
Dependent Claim 11 is allowable by virtue of its dependency on claim 10.
Regarding Claim 13, Ware discloses all of the limitations of Claim 8.
Ware does not disclose “wherein the first phase circuitry, the second phase circuitry, and the processor circuitry are mounted on a printed circuit board, and the first and second phase circuitries are located on a same region of the printed circuit board relative to a location of the processor circuitry.”
Prior art Woo (US 20150309529 A1), Burstein (US 6031361 A), Kliza (US 5852640 A), Kuroda (US 20060077798 A1), Zhang (US 20030197245 A1) and Rice (US 7138788 B2) are considered to be the closest prior art.
Woo teaches wherein the first phase circuitry, the second phase circuitry, and the controller circuitry are mounted on a printed circuit board ("Although using separate command and address lines for the two modules requires additional pins on the associated host device and additional wires on the circuit board", [0048]).
However, none of the prior art, taken singly or in combination, teach “the first and second phase circuitries are located on a same region of the printed circuit board relative to a location of the processor circuitry.”
Regarding Claim 14, Ware discloses all of the limitations of Claim 8.
Ware does not disclose “further comprising instructions that, when executed, configure the processor circuitry to: determine a first delay corresponding to an amount of time for the first pulse to reach the first phase circuitry responsive to a first current sense signal from the first phase circuitry; determine a second delay corresponding to an amount of time for the second pulse to reach the second phase circuitry responsive to a second current sense signal from the second phase circuitry; and determine the first and second times responsive to the first delay and the second delay.”
Prior art Woo (US 20150309529 A1), Burstein (US 6031361 A), Kliza (US 5852640 A), Kuroda (US 20060077798 A1), Zhang (US 20030197245 A1) and Rice (US 7138788 B2) are considered to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “further comprising instructions that, when executed, configure the processor circuitry to: determine a first delay corresponding to an amount of time for the first pulse to reach the first phase circuitry responsive to a first current sense signal from the first phase circuitry; determine a second delay corresponding to an amount of time for the second pulse to reach the second phase circuitry responsive to a second current sense signal from the second phase circuitry; and determine the first and second times responsive to the first delay and the second delay.”
Regarding Claim 17, it is indicated as allowable for the same reasons as stated above for Claim 10.
Dependent Claims 18 & 20 are allowable by virtue of their dependency on claim 17.
Conclusion
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/J.C.C./Examiner, Art Unit 2838
/GARY L LAXTON/Primary Examiner, Art Unit 2838 4/04/2026