DETAILED ACTION
This non-final office action is responsive to application 18/140,435 as submitted 27 April 2023.
Claim status is currently pending and under examination for claims 1-20 of which independent claims are 1, 12 and 19.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The application has an effective filing date of 05/12/22.
Information Disclosure Statement
As required by MPEP 609(c), the applicant’s submissions of the Information Disclosure Statement dated 04/27/23 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by MPEP 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) because the claim limitations use a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such functional claim limitations include the following:
Claim 1: A digital signal processing device comprising:
“generator configured to generate”
“calculator configured to receive”
Claim 2: The digital signal processing device of claim 1, wherein
“generator is further configured to set”
Claim 3: The digital signal processing device of claim 2, wherein
“generator is further configured to calculate”
Claim 4: The digital signal processing device of claim 2, wherein
“calculator is further configured to acquire”
Claim 5: The digital signal processing device of claim 4, wherein
“generator is further configured to generate”
Claim 6: The digital signal processing device of claim 5, wherein
“generator is further configured to generate”
Claim 7: The digital signal processing device of claim 5, wherein
“calculator is further configured to calculate”
Claim 8: The digital signal processing device of claim 7, wherein
“calculator is further configured to calculate”
Claim 9: The digital signal processing device of claim 7, wherein
“calculator is further configured to calculate”
Claim 10: The digital signal processing device of claim 1, wherein
“converter configured to convert”
Claim 11: The digital signal processing device of claim 10, wherein
“converter is further configured to convert”
Claim 19: A digital signal processing device, comprising:
“first lookup table generator configured to generate”
“second lookup table generator configured to generate”
“calculator configured to receive”
“converter configured to convert”
Claim 20: The digital signal processing device of claim 19, wherein
“generator is further configured to: set”
Because these claim limitations are being interpreted under 35 U.S.C. 112(f), they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
The corresponding structure is interpreted in light of the specification. The specification fails to make it clear that the functions are limited to particular embodiments. The functional components are illustrated by drawings Figs 1 and 6 showing block diagram of device and the specification largely repeats claim language stating per PG Pub No 2023/0367356A1
[0148] “each of the components represented by a block as illustrated in Figs. 1, 6 and 11 may be implemented as various numbers of hardware, software and/or firmware …the components, elements, modules, or units represented by a block or processing steps may employ any number of related art techniques for electronics configurations, signal processing and/or control, data processing and the like”
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitations to avoid them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-11 and 19-20 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention. Particularly, claims recite generators, calculator and converter configured to perform functions which invoke 35 U.S.C. 112(f). However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The functional components are illustrated Figs 1 and 6, and described [0148] of the PG Pub. Neither the specification nor the drawings describe sufficient supporting structure for each functional unit that clearly links the structure, material, or acts in performance of the entire claimed function. Accordingly, the claims are indefinite and are rejected under 35 U.S.C. 112(b). For purpose of examination, the functional components are interpreted as any combination of hardware or software. The deficiency is not cured by claims depending from 1 and 19. Therefore, claims 1-11 and 19-20 are rejected under 35 USC 112(b).
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. In determining whether the claims are subject matter eligible, the examiner applies guidance set forth under MPEP 2106.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter? Yes—all claims fall within one of the four statutory categories: claims 1-11 and 19-20 are a device/machine, and claims 12-18 are method/process. Accordingly, all of the claims are to statutory subject matter and the analysis should proceed as per MPEP 2106.03.
Step 2A, prong one: Does the claim recite an abstract idea, law of nature or natural phenomenon? Yes—the claims, under the broadest reasonable interpretation, recites an abstract idea. In this case, claims fall within the grouping of abstract idea being “Mathematical Concepts” and/or “Mental Processes” enumerated under MPEP 2106.04(a), but for the recitation of generic computer components. In particular, claims recite:
Claim 1:
“a lookup table generator configured to generate a first lookup table corresponding to a first exponential function, based on an input scaling value” (Mental process generated by-hand with aid of pen and paper, for values of a math/exponential function)
“a softmax calculator configured to… calculate a first index of the first lookup table, the first index corresponding to a first input value of the plurality of input values… calculate a first intermediate value based on the first exponential function value and the first input value” (Mathematical Calculation)
Claim 12:
“generating a first lookup table corresponding to a first exponential function, based on the input scaling value” (Mental process generated by-hand with aid of pen and paper, for values of a math/exponential function)
“calculating a first index of the first lookup table, the first index corresponding to a first input value of the plurality of input values” and “calculating a first intermediate value based on the first exponential function value” (Mathematical Calculation)
Claim 19:
“a first lookup table generator configured to generate a first lookup table corresponding to a first exponential function, based on an input scaling value” and “a second lookup table generator configured to generate a second lookup table corresponding to a second exponential function, based on the input scaling value and a size of the first lookup table” (Mental process generated by-hand with aid of pen and paper, for values of a math/exponential function)
“a softmax calculator configured to… calculate a first index of the first lookup table and a second index of the second lookup table, the first index and the second index each corresponding to a first input value of the plurality of input values… calculate a first intermediate value based on the first exponential function value and the second exponential function value” (Mathematical Calculation)
Focus of the claims concern softmax calculation using lookup tables. When read in light of the specification, math calculation of a softmax function is described e.g. [0029], and providing table values for the math does not preclude mental performance. The table values provide math values per [0047] as exponential function values. As such, the claims recite and are drawn to mathematical calculations with mental processes as the abstract idea.
Step 2A, prong two: Does the claim recite additional elements that integrate the judicial exception into a practical application? No—a practical application is not integrated by the judicial exception because the additional elements are as follows:
Claim 1:
“A digital signal processing device comprising: one or more memories storing instructions; and one or more processors configured to execute the instructions to implement”
MPEP 2106.05(f) merely uses a computer as a tool to implement an abstract idea, or mere instructions to perform an abstract idea on a computer. Recited at a high level of generality
“receive input data indicating a plurality of input values” and “read a first exponential function value corresponding to the first index from the first lookup table” MPEP 2106.05(g) adding insignificant extra-solution activity to the judicial exception, e.g. mere data gathering
“generate output data indicating a plurality of output values respectively corresponding to the plurality of input values, wherein a first output value of the plurality of output values is generated based on the first intermediate value” MPEP 2106.05(g) adding insignificant extra-solution activity to the judicial exception, e.g. necessary data outputting
Claim 12:
“digital signal processing device” MPEP 2106.05(f) merely uses a computer as a tool to implement an abstract idea. Recited at a high level of generality
“receiving an input scaling value and input data indicating a plurality of input values” and “reading a first exponential function value corresponding to the first index from the first lookup table” MPEP 2106.05(g) adding insignificant extra-solution activity to the judicial exception, e.g. mere data gathering
“generating output data indicating a plurality of output values respectively corresponding to the plurality of input values, wherein a first output value of the plurality of output values is generated based on the first intermediate value” MPEP 2106.05(g) adding insignificant extra-solution activity to the judicial exception, e.g. necessary data outputting
Claim 19:
“A digital signal processing device comprising: one or more memories storing instructions; and one or more processors configured to execute the instructions to implements”
MPEP 2106.05(f) merely uses a computer as a tool to implement an abstract idea, or mere instructions to perform an abstract idea on a computer. Recited at a high level of generality
“receive input data indicating a plurality of input values… read a first exponential function value corresponding to the first index from the first lookup table, read a second exponential function value corresponding to the second index from the second lookup table”
MPEP 2106.05(g) adding insignificant extra-solution activity to the judicial exception, e.g. mere data gathering
“generate output data indicating a plurality of output values respectively corresponding to the plurality of input values, wherein a first output value of the plurality of output values is generated based on the first intermediate value” MPEP 2106.05(g) adding insignificant extra-solution activity to the judicial exception, e.g. necessary data outputting
Balance of the claims concern device for implementation to receive input and generate output. As set forth per MPEP 2106.04(a)(2) “A claim that requires a computer may still recite a mental process” in other words, mere computer implementation does not preclude judicial exceptions. Further, the input and output does not meaningfully limit the claim such that the claim as a whole is more than a drafting effort designed to monopolize the exception. There is no recitation of a use for the output to be applied in some concrete, real-world application. Therefore, the claim remains drawn to abstract ideas and the additional elements do not integrate the abstract idea into a practical application.
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception? No—the claims do not include additional elements that amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea in to a practical application, the additional elements are identified with respect to MPEP 2106.05 and do not demonstrate inventive concept. Particularly, the additional elements are as follows:
Claim 1:
“A digital signal processing device comprising: one or more memories storing instructions; and one or more processors configured to execute the instructions to implement”
MPEP 2106.05(f) merely uses a computer as a tool to implement an abstract idea, or mere instructions to perform an abstract idea on a computer. Recited at a high level of generality. Particularly, the device does not qualify as a particular machine under MPEP 2106.05(b).
“receive input data indicating a plurality of input values” and “read a first exponential function value corresponding to the first index from the first lookup table” MPEP 2106.05(g) adding insignificant extra-solution activity to a judicial exception, e.g. mere data gathering. Particularly, said extra-solution activity is a well-understood, routine and conventional (WURC) activity under MPEP 2106.05(d)(II)(i,iv) “Receiving or transmitting data” and “retrieving information in memory”
“generate output data indicating a plurality of output values respectively corresponding to the plurality of input values, wherein a first output value of the plurality of output values is generated based on the first intermediate value” MPEP 2106.05(g) adding insignificant extra-solution activity to the judicial exception, e.g. necessary data outputting. Particularly, said extra-solution activity is a well-understood, routine and conventional (WURC) activity under MPEP 2106.05(d)(II)(v) “Determining an estimated outcome”
Claim 12:
“digital signal processing device” MPEP 2106.05(f) merely uses a computer as a tool to implement an abstract idea. Recited at a high level of generality. Particularly, the device does not qualify as a particular machine under MPEP 2106.05(b).
“receiving an input scaling value and input data indicating a plurality of input values” and “reading a first exponential function value corresponding to the first index from the first lookup table” MPEP 2106.05(g) adding insignificant extra-solution activity to the judicial exception, e.g. mere data gathering. Particularly, said extra-solution activity is a well-understood, routine and conventional (WURC) activity under MPEP 2106.05(d)(II)(i,iv) “Receiving or transmitting data” and “retrieving information in memory”
“generating output data indicating a plurality of output values respectively corresponding to the plurality of input values, wherein a first output value of the plurality of output values is generated based on the first intermediate value” MPEP 2106.05(g) adding insignificant extra-solution activity to the judicial exception, e.g. necessary data outputting. Particularly, said extra-solution activity is a well-understood, routine and conventional (WURC) activity under MPEP 2106.05(d)(II)(v) “Determining an estimated outcome”
Claim 19:
“A digital signal processing device comprising: one or more memories storing instructions; and one or more processors configured to execute the instructions to implements”
MPEP 2106.05(f) merely uses a computer as a tool to implement an abstract idea, or mere instructions to perform an abstract idea on a computer. Recited at a high level of generality. Particularly, the device does not qualify as a particular machine under MPEP 2106.05(b).
“receive input data indicating a plurality of input values… read a first exponential function value corresponding to the first index from the first lookup table, read a second exponential function value corresponding to the second index from the second lookup table”
MPEP 2106.05(g) adding insignificant extra-solution activity to the judicial exception, e.g. mere data gathering. Particularly, said extra-solution activity is a well-understood, routine and conventional (WURC) activity under MPEP 2106.05(d)(II)(i,iv) “Receiving or transmitting data” and “retrieving information in memory”
“generate output data indicating a plurality of output values respectively corresponding to the plurality of input values, wherein a first output value of the plurality of output values is generated based on the first intermediate value” MPEP 2106.05(g) adding insignificant extra-solution activity to the judicial exception, e.g. necessary data outputting. Particularly, said extra-solution activity is a well-understood, routine and conventional (WURC) activity under MPEP 2106.05(d)(II)(v) “Determining an estimated outcome”
Significantly more is not satisfied for at least the reasons above. Mere input and output does not shed any light into a particular transformation, and the device does not require anything beyond generic computer implementation. If the claim language provides only a result-oriented solution, with insufficient detail for how a computer accomplishes it, then the claims do contain an inventive concept. Taken alone, their additional elements do not amount to significantly more than the above-identified judicial exception (the abstract idea). Looking at the claim as a whole with the limitations as an ordered combination adds nothing that is not already present when looking at the elements taken individually. Their collective functions merely provide conventional computer implementation.
In view of the foregoing, claims are found ineligible under 35 U.S.C. 101. This rejection applies to independent claims 1, 12 and 19 as well to dependent claims 2-11, 13-18 and 20. Dependent claims when analyzed as a whole are held to be patent ineligible under 35 U.S.C. 101 because the additional recited limitations fail to establish that the claims are not directed to an abstract idea, or that they include additional elements which integrate the judicial exception into a practical application or amount to significantly more.
Dependent claim 2 discloses setting size of lookup table to a smaller number from among smallest integer greater than or equal to reciprocal of scaled input value, and a total amount of numbers that are representable using a number of bits of the first value. The limitation is considered part of the abstract idea as mathematical relationships, e.g. operand ‘ ≥ ‘ greater than or equal to reciprocal values in relationship to integer values. There are no additional elements.
Dependent claim 3 discloses calculating the first exponential function based on the input scaling value and the size of the lookup table, and generate the lookup table having calculation results of the first exponential function as values corresponding to an index. The limitation is considered to elaborate the abstract idea including mathematical calculations. There are no additional elements.
Dependent claim 4 discloses wherein calculator acquires largest value of inputs and calculate the first index corresponding to first value based on the input value, size of lookup table, and the largest value. This is considered part of the abstract idea being mathematical calculations. For example, largest value can be magnitude or absolute value. There are no additional elements.
Dependent claim 5 discloses generating a second lookup table corresponding to second exponential function, based on the input scaling value and the size of the first lookup table. This is considered part of the abstract idea including mental processes that can be generated by-hand with aid of pen and paper for the math/exponential function. There are no additional elements.
Dependent claim 6 discloses generating the second lookup table such that a calculation result of the second exponential function is 0, based on an index of the second lookup table being greater than or equal to a preset reference index. This is considered part of the abstract idea including mathematical relationships such as operand ‘ ≥ ‘ greater than or equal to index for a zero-value. There are no additional elements.
Dependent claim 7 discloses calculating second index of second table with corresponding value, read a second exponential function value from second index of second table, and calculate the first intermediate value based on first and second exponential values. The limitations of calculating are considered part of the abstract idea of mathematical calculations. The limitation of reading is an additional element which fall under MPEP 2106.05(g) insignificant extra-solution activity, and particularly is a WURC activity under MPEP 2106.05(d)(II)(iv) retrieving information in memory. Accordingly, the claim remains directed to the abstract idea and the additional elements do not integrate the judicial exception into a practical application or amount to significantly more.
Dependent claim 8 discloses calculate the second index corresponding to first value, based on first value, size of first lookup table, and the largest value. The limitation is considered to embellish the abstract idea being mathematical calculations. There are no additional elements.
Dependent claim 9 discloses calculate the first intermediate value by multiplying the first exponential function value by the second exponential function value. This is considered part of the abstract idea being mathematical calculation of multiplying. There are no additional elements.
Dependent claim 10 discloses converting a data type of the output data. This may be considered part of the abstract idea including mental processes and/or math conversion. For example, converting a floating-point to integer value. There are no additional elements.
Dependent claim 11 discloses converting the data type into a quantized integer type based on a value of scaled output and an output zero-point value. This is considered part of the abstract idea including math conversion. For example, zero-point value can be mantissa or quotient, and quantization may be performed such as binarization of integer values. There are no additional elements.
Dependent claim 13 discloses limitations of claims 2-3 and the rejections thereof are applied for the reasons already noted above.
Dependent claim 14 discloses limitation of claim 4 and the rejection thereof is applied for the reasons already noted above.
Dependent claim 15 discloses limitation of claim 5 and the rejection thereof is applied for the reasons already noted above.
Dependent claim 16 discloses limitation of claim 7 and the rejection thereof is applied for the reasons already noted above.
Dependent claim 17 discloses limitation of claim 8 and the rejection thereof is applied for the reasons already noted above.
Dependent claim 18 discloses limitation of claim 11 and the rejection thereof is applied for the reasons already noted above.
Dependent claim 20 discloses limitation of claims 2-3 and the rejections thereof are applied for the reasons already noted above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over: Petig, Christof, US PG Pub No 2022/0383077A1 hereinafter Petig as evidenced by priority document (attached, see PTO-892), in view of Xi et al., US PG Pub No 2023/0161554A1 hereinafter Xi, and further in view of Yamano et al., US PG Pub No 2024/0104166A1 hereinafter Yamano as evidenced by priority document (attached, see PTO-892).
With respect to claim 1, Petig teaches:
A digital signal processing device {Petig discloses [0048] “data processing device 100, represented in Fig. 7” as a [0038] “device for executing the SoftMax function”} comprising:
one or more memories storing instructions {Petig [0048] “memory 200 for storing” comprising [0028] “computer program including instructions”}; and
one or more processors configured to execute the instructions to implement {Petig [0048] “processor 101” for [0028] “instructions which, when the program is executed by a computer, cause the computer to carry out the steps of the method”}:
a lookup table generator configured to generate a first lookup table corresponding to a first exponential function, based on an input scaling value {Petig see Fig 4:S10 illustrating “Generate Lookup Table T” described e.g. [0047] introduces exponential functions [0042-47], and discloses [0059] “input scaling factor”. See e.g. [0080] lookup table T1 scaled}; and
a softmax calculator configured to receive input data indicating a plurality of input values {Petig [0042] “SoftMax function can use the following mathematical formula… where zi may represent an input number (real value)” in vector form [0040]}, calculate a first index of the first lookup table, the first index corresponding to a first input value of the plurality of input values {Petig [0050-52] “lookup index consisting in an integer… index j giving the position of the fraction component fcj in the lookup table T” calculation comprises Eq.3, see similar at [0008], [0080-82]}, read a first exponential function value corresponding to the first index from the first lookup table {Petig [0082-85] “retrieve from the lookup table T1 the fraction component fci, using the obtained lookup index” again [0008], Fig 4:S17}, and generate output data indicating a plurality of output values respectively corresponding to the plurality of input values {Petig see [0084-86] “generates in a sixth N/2-bit register R6i, termed result register, a binary number qi representative of the exponential value of said input number zi” result/output register R6i shown Fig 4:S18, cont’d [0097] scaled output, and introduces outputs given inputs per [0059,42]},
However, Petig does not expressly disclose “intermediate value” that is disclosed by Xi:
calculate a first intermediate value based on the first exponential function value and the first input value, wherein a first output value of the plurality of output values is generated based on the first intermediate value {Xi [0076-77] “intermediate exponent value exp1 …output yexp = 127 + (127-xexp) / 2 = (381 - xexp) / 2” where xexp is input and yexp is output, shown Fig 6 see exp1 between 650 and 665 adders, input before 605 and output after 680. The (exp)onential is described with respect to reciprocal function that is introduced as equivalent softmax [0029]}.
Xi is directed to devices for accelerating calculations including softmax using LUTs lookup tables thus being analogous. A person having ordinary skill in the art would have considered it obvious prior to the effective filing date to specify intermediate exponent values per Xi in combination as applying known techniques to known devices ready for improvement to yield predictable results and/or a motivation of “significant speed improvements and energy efficiency improvements” [0031], which may include adjusting the exponent values [0077], and using a multiplexer to select intermediate values [0058].
Finally, support for combination and motivation is provided by Yamano. Particularly, at [0066] product of exponential functions which can be seen as intermediate values for calculating softmax [0061-62], and specifies [0074] reads from lookup tables shown Figs 7B, 5:406,407 with indexes for each of the lookup tables being addressable [0103]. Yamano is directed to devices for softmax calculation with lookup tables thus being analogous. A person having ordinary skill in the art would have considered it obvious prior to the effective filing date to employ the teachings of Yamano in combination to arrive at the invention as claimed for a motivation [0001,04] “speeding up numerical calculation of a softmax function… processing load of the softmax is reduced” e.g. [0124] “reduce the processing load… while suppressing the size of the look up table required to approximate the exponential function with high accuracy” similar at [0026-28] advantageous effects.
With respect claim 2, the combination of Petig, Xi and Yamano teaches the digital signal processing device of claim 1, wherein the lookup table generator is further configured to
set a size of the first lookup table to a smaller number from among: a smallest integer greater than or equal to a reciprocal number of the input scaling value, and a total amount of numbers that are representable using a number of bits of the first input value {Xi discloses [0081] “lookup table 810 includes two tables with sizes of 32x12 bit and 16x12-bit. The smaller 16-entry table is selected when reciprocal is performed” size of lookup table is set by selecting described with respect to number of bits as well as reciprocal cont’d [0086] “reciprocal and reciprocal-square-root linear interpolation lookup table 810, the number of bits used in the pre-computed quantized slopes kq and the pre-computed quantized offsets eq, which affects the size of the lookup tables and the size of the integer multiplier” integer scaled by multiplier. The BRI of ‘among’ is comprising as an open-ended alternatives. See also [0099] “small sized lookup tables”}.
A person having ordinary skill in the art would have considered it obvious prior to the effective filing date to set size of lookup table according to the teachings of Xie to arrive at the invention as claimed for a motivation [0099] “small sized lookup tables…make this technique very area efficient when targeting FPGAs with rich lookup table (LUT) resources” such that the small sized LUTs are less compute-intensive than large LUTs. This is confirmed by both Petig [0047] and Yamano [0026].
With respect to claim 3, the combination of Petig, Xi and Yamano teaches the digital signal processing device of claim 2, wherein the lookup table generator is further configured to
calculate the first exponential function based on the input scaling value and the size of the first lookup table {Petig [0043,47] “calculation of the exponential function for each input… uses a lookup table of a small size to reduce the calculation efforts” and the input being scaled [0059]}, and generate the first lookup table having calculation results of the first exponential function as values corresponding to an index {Petig Fig 4:S10 “Generate Lookup Table T” described e.g. [0085-80] “lookup table T1 at the step S17 into said result register” with “size M of the lookup table T1 (the multiplication or scaling result be rounding to the nearest integer) to obtain a lookup index”}.
With respect to claim 4, the combination of Petig, Xi and Yamano teaches the digital signal processing device of claim 2, wherein the softmax calculator is further configured to
acquire a largest value of the plurality of input values, and calculate the first index corresponding to the first input value, based on the first input value, the size of the first lookup table, and the largest value {Petig [0059] “largest values of the original input numbers and the size” and/or [0061-62] “maximal original input number xmax and subtract xi from xmax so as to obtain a input number zi … zi = xmax - xi” is calculation, applied in formula [0086] for the indexes [0080-86]. See Fig 4:S12 as well as Figs 2:S12 and 3A:Col2}.
With respect to claim 5, the combination of Petig, Xi and Yamano teaches the digital signal processing device of claim 4, wherein the lookup table generator is further configured to
generate a second lookup table corresponding to a second exponential function, based on the input scaling value and the size of the first lookup table {Petig [0100-07] “lookup table T2 at step S17” shown Fig 4:S17 based on the first lookup table S10 generated in dataflow indicated by arrows, respective scaling and size are e.g. S145 as Sin scaled input and S16 size M, again [0100-0107] functions with exponents in superscript are detailed and describe exponential values thereof}.
With respect to claim 6, the combination of Petig, Xi and Yamano teaches the digital signal processing device of claim 5, wherein the lookup table generator is further configured to
generate the second lookup table such that a calculation result of the second exponential function is 0, based on an index of the second lookup table being greater than or equal to a preset reference index {Petig [0103-04] fcM-1 ≈ 0 “fraction component fci retrieved from lookup table T2 …result register R6i, if needed by adding bits set at 0” equation provides exponents and indexing with sub- and super-scripts, the fraction may regard significant bits, and the fraction being greater than or equal to is disclose [0079]. Similar functionality may consider lookup tables T3-T6 [0114-15], [0120-33]}.
With respect to claim 7, the combination of Petig, Xi and Yamano teaches the digital signal processing device of claim 5, wherein the softmax calculator is further configured to
calculate a second index of the second lookup table, the second index corresponding to the first input value {Petig [0081-83] “lookup indexes” emphasis plural, e.g. shown Fig 4:S17 “Look Up T with indi” (ind)ex, described [0050-52] “lookup index consisting in an integer varying… index j giving the position of the fraction component fcj in the lookup table T” calculation comprises Eq.3, similar at [0008]. See also Yamano Fig 7B illustrates 2nd index of 2nd table}, read a second exponential function value corresponding to the second index from the second lookup table {Petig [0103-06] “retrieve from the lookup table T2” fraction components of function with exponents See also Yamano [0074] reads}, and
However Petig does not disclose intermediate value which is disclosed by Xi:
calculate the first intermediate value, based on the first exponential function value and the second exponential function value {Xi [0076-77] “intermediate exponent value exp1” and [0058] “intermediate value exp2” shown e.g. Figs 6 and 9. The (exp)onentials is described with respect to reciprocal function that is introduced as equivalent softmax [0029]}.
A person having ordinary skill in the art would have considered it obvious prior to the effective filing date to specify intermediate exponent values per Xi in combination as applying known techniques to known devices ready for improvement to yield predictable results and/or a motivation of “significant speed improvements and energy efficiency improvements” [0031], which may include adjusting the exponent values [0077], and using a multiplexer to select intermediate values [0058].
Finally, support for combination and motivation is provided by Yamano. Particularly, at [0066] product of exponential functions which can be seen as intermediate values for calculating softmax [0061-62], and specifies [0074] reads from lookup tables shown Figs 7B, 5:406,407. A person having ordinary skill in the art would have considered it obvious prior to the effective filing date to employ the teachings of Yamano in combination to arrive at the invention as claimed for a motivation [0001,04] “speeding up numerical calculation of a softmax function… processing load of the softmax is reduced” e.g. [0124] “reduce the processing load… while suppressing the size of the look up table required to approximate the exponential function with high accuracy” see [0026-28] advantageous effects.
With respect to claim 8, the combination of Petig, Xi and Yamano teaches the digital signal processing device of claim 7, wherein the softmax calculator is further configured to
calculate the second index corresponding to the first input value, based on the first input value, the size of the first lookup table, and the largest value {Petig [0081-83] “lookup indexes” emphasis plural, e.g. shown Fig 4:S17 “Look Up T with indi” (ind)ex, described [0050-52] “lookup index consisting in an integer varying… index j giving the position of the fraction component fcj in the lookup table T” calculation comprises Eq.3, similar at [0008]. See also Yamano Fig 7B}. Motivation for combination is applied similarly as in claim 7.
With respect to claim 9, the combination of Petig, Xi and Yamano teaches the digital signal processing device of claim 7, wherein the softmax calculator is further configured to
calculate the first intermediate value by multiplying the first exponential function value by the second exponential function value {Yamano [0066] “product of the exponential functions” Eq.4 details thereby calculating values considered intermediate as applied to softmax [0061-62]}. Motivation for combination is applied similarly as in claim 7.
With respect claim 10, the combination of Petig, Xi and Yamano teaches the digital signal processing device of claim 1, wherein the one or more processors are further configured to execute the instructions to implement
a type converter configured to convert a data type of the output data {Petig discloses [0111] “converting the floating-point numbers stored in the registers R8, into decimal values”}.
With respect claim 11, the combination of Petig, Xi and Yamano teaches the digital signal processing device of claim 10, wherein the type converter is further configured to
convert the data type of the output data into a quantized integer type, based on an output scaling value and an output zero-point value {Yamano [0134] “quantized and converted into an integer” see Figs 9B-10 right-column showing the values converted e.g. 0.9375, described [0093-98], [0077-78] where rounding conveys a way of scaling output values. See also [0059]}.
A person having ordinary skill in the art would have considered it obvious prior to the effective filing date to convert according to Yamano for Petig’s conversion to arrive at the invention as claimed as simple substitution among known techniques for converting data to obtain predictable results and which Yamano characterizes per [0059] “it goes without saying that the data may be converted into data of an integer.”
With respect to claim 12, Petig teaches:
A softmax calculation method, which is performed by a digital signal processing device, the softmax calculation method {Petig [0047] “method of executing a SoftMax function on the data processing device” again at [0054]} comprising:
receiving an input scaling value and input data indicating a plurality of input values {Petig [0059] “received in the step S11…input scaling factor” Fig 4:S411, similarly at [0068-76] the scaled input may be received by registers};
generating a first lookup table corresponding to a first exponential function, based on the input scaling value {Petig Fig 4:S10 illustrating “Generate Lookup Table T” described e.g. [0047] introduces exponential functions [0042-47], and discloses [0059] “input scaling factor”. See e.g. [0080] lookup table T1 scaled};
calculating a first index of the first lookup table, the first index corresponding to a first input value of the plurality of input values {Petig [0050-52] “lookup index consisting in an integer… index j giving the position of the fraction component fcj in the lookup table T” calculation comprises Eq.3, see similar at [0008], [0080-82]};
reading a first exponential function value corresponding to the first index from the first lookup table {Petig [0082-85] “retrieve from the lookup table T1 the fraction component fci, using the obtained lookup index” again [0008], Fig 4:S17};
generating output data indicating a plurality of output values respectively corresponding to the plurality of input values {Petig discloses [0084-86] “generates in a sixth N/2-bit register R6i, termed result register, a binary number qi representative of the exponential value of said input number zi” result/output register R6i shown Fig 4:S18, cont’d [0097] scaled output, and introduces outputs given inputs [0059,42]},
However, Petig does not expressly disclose “intermediate value” which is disclosed by Xi:
calculating a first intermediate value based on the first exponential function value; and
wherein a first output value of the plurality of output values is generated based on the first intermediate value {Xi [0076-77] “intermediate exponent value exp1 …output yexp = 127 + (127-xexp) / 2 = (381 - xexp) / 2” where xexp is input and yexp is output, shown Fig 6 see exp1 between 650 and 665 adders, input before 605 and output after 680. The (exp)onential is described with respect to reciprocal function that is introduced as equivalent softmax [0029]}.
Xi is directed to devices for accelerating calculations including softmax using LUTs lookup tables thus being analogous. A person having ordinary skill in the art would have considered it obvious prior to the effective filing date to specify intermediate exponent values per Xi in combination as applying known techniques to known devices ready for improvement to yield predictable results and/or a motivation of “significant speed improvements and energy efficiency improvements” [0031], which may include adjusting the exponent values [0077], and using a multiplexer to select intermediate values [0058].
Finally, support for combination and motivation is provided by Yamano. Particularly, at [0066] product of exponential functions which can be seen as intermediate values for calculating softmax of [0061-62], and specifies [0074] reads from lookup tables shown Figs 7B, 5:406,407 with indexes for each of the lookup tables being addressable [0103]. Yamano is directed to devices for softmax calculation with lookup tables thus being analogous. A person having ordinary skill in the art would have considered it obvious prior to the effective filing date to employ the teachings of Yamano in combination to arrive at the invention as claimed for a motivation [0001,04] “speeding up numerical calculation of a softmax function… processing load of the softmax is reduced” e.g. [0124] “reduce the processing load… while suppressing the size of the look up table required to approximate the exponential function with high accuracy” similarly as per [0026-28] advantageous effects.
With respect claim 13, the combination of Petig, Xi and Yamano teaches the softmax calculation method of claim 12, wherein the generating the first lookup table comprises:
calculating the first exponential function, based on the input scaling value and the size of the first lookup table {Petig [0043,47] “calculation of the exponential function for each input… uses a lookup table of a small size to reduce the calculation efforts” and the input being scaled [0059]}; and
generating the first lookup table having calculation results of the first exponential function as values corresponding to an index {Petig Fig 4:S10 “Generate Lookup Table T” described e.g. [0085-80] “lookup table T1 at the step S17 into said result register” with “size M of the lookup table T1 (the multiplication or scaling result be rounding to the nearest integer) to obtain a lookup index”}.
Petig further suggests [0050] “any other size of the lookup table T, preferably of the kind M-2m (m being an integer), can be used”. However, Petig does not appear to disclose the following limitation which is met by Xi:
setting, as a size of the first lookup table, a smaller number from among: a smallest integer greater than or equal to a reciprocal number of the input scaling value and a total amount of numbers representable using a number of bits of the first input value {Xi discloses [0081] “lookup table 810 includes two tables with sizes of 32x12 bit and 16x12-bit. The smaller 16-entry table is selected when reciprocal is performed” size of lookup table is set by selecting described with respect to number of bits as well as reciprocal cont’d [0086] “reciprocal and reciprocal-square-root linear interpolation lookup table 810, the number of bits used in the pre-computed quantized slopes kq and the pre-computed quantized offsets eq, which affects the size of the lookup tables and the size of the integer multiplier” integer scaled by multiplier. The BRI of ‘among’ is comprising as an open-ended alternatives. See also [0099] “small sized lookup tables” };
A person having ordinary skill in the art would have considered it obvious prior to the effective filing date to set size of lookup table according to the teachings of Xie to arrive at the invention as claimed for a motivation [0099] “small sized lookup tables…make this technique very area efficient when targeting FPGAs with rich lookup table (LUT) resources” such that the small sized LUTs are less compute-intensive than large LUTs. This is confirmed by both Petig [0047] and Yamano [0026].
With respect to claim 14, the combination of Petig, Xi and Yamano teaches the softmax calculation method of claim 13, and further teaches the limitation of claim 4. Therefore, the rejection of claim 4 is applied to claim 14.
With respect to claim 15, the combination of Petig, Xi and Yamano teaches the softmax calculation method of claim 14, and further teaches the limitation of claim 5. Therefore, the rejection of claim 5 is applied to claim 15.
With respect to claim 16, the combination of Petig, Xi and Yamano teaches the softmax calculation method of claim 15, and further teaches the limitation of claim 7. Therefore, the rejection of claim 7 is applied to claim 16.
With respect to claim 17, the combination of Petig, Xi and Yamano teaches the softmax calculation method of claim 16, and further teaches the limitation of claim 8. Therefore, the rejection of claim 8 is applied to claim 17.
With respect claim 18, the combination of Petig, Xi and Yamano teaches the softmax calculation method of claim 12, further comprising
converting a type of the output data into a quantized integer type, based on an output scaling value and an output zero-point value {Yamano [0134] “quantized and converted into an integer” see Figs 9B-10 right-column showing the values converted e.g. 0.9375, described [0093-98], [0077-78] where rounding conveys a way of scaling output values. See also [0059]}.
A person having ordinary skill in the art would have considered it obvious prior to the effective filing date to convert according to Yamano for Petig’s conversion to arrive at the invention as claimed as simple substitution among known techniques for converting data to obtain predictable results and which Yamano characterizes per [0059] “it goes without saying that the data may be converted into data of an integer.”
With respect to claim 19, Petig teaches:
A digital signal processing device {Petig discloses [0048] “data processing device 100, represented in Fig. 7” as a [0038] “device for executing the SoftMax function”} comprising:
one or more memories storing instructions {Petig [0048] “memory 200 for storing” comprising [0028] “computer program including instructions”}; and
one or more processors configured to execute the instructions to implement {Petig [0048] “processor 101” for [0028] “instructions which, when the program is executed by a computer, cause the computer to carry out the steps of the method”}:
a first lookup table generator configured to generate a first lookup table corresponding to a first exponential function, based on an input scaling value {Petig Fig 4:S10 “Generate Lookup Table T” described e.g. [0047] introduces exponential functions [0042-47], and discloses [0059] “input scaling factor”. See e.g. [0080] lookup table T1 scaled};
a second lookup table generator configured to generate a second lookup table corresponding to a second exponential function, based on the input scaling value and a size of the first lookup table {Petig [0100-07] “lookup table T2 at step S17” shown Fig 4:S17 based on the first lookup table S10 generated in dataflow indicated by arrows, respective scaling and size are e.g. S145 as Sin scaled input and S16 size M, again [0100-0107] functions with exponents in superscript are detailed and describe exponential values thereof};
a softmax calculator configured to receive input data indicating a plurality of input values {Petig [0042] “SoftMax function can use the following mathematical formula… where zi may represent an input number (real value)” in vector form [0040]}, calculate a first index of the first lookup table and a second index of the second lookup table, the first index and the second index each corresponding to a first input value of the plurality of input values {Petig [0081-83] “lookup indexes” emphasis plural, e.g. shown Fig 4:S17 “Look Up T with indi” (ind)ex, described [0050-52] “lookup index consisting in an integer varying… index j giving the position of the fraction component fcj in the lookup table T” calculation comprises Eq.3, similar at [0008]}, read a first exponential function value corresponding to the first index from the first lookup table, read a second exponential function value corresponding to the second index from the second lookup table {Petig [0082-85] “retrieve from the lookup table T1 the fraction component fci, using the obtained lookup index” as well as [0103-06] “retrieve from the lookup table T2” similarly described}, and generate output data indicating a plurality of output values respectively corresponding to the plurality of input values {Petig [0084-86] “generates in a sixth N/2-bit register R6i, termed result register, a binary number qi representative of the exponential value of said input number zi” result/output register R6i shown Fig 4:S18, cont’d [0097] scaled output, and introduces outputs given inputs per [0059,42]}, and a type converter configured to convert a data type of the output data {Petig discloses [0111] “converting the floating-point numbers stored in the registers R8i into decimal values”}.
However, Petig does not disclose “intermediate value” which is disclosed by Xi:
calculate a first intermediate value based on the first exponential function value and the second exponential function value, wherein a first output value of the plurality of output values is generated based on the first intermediate value; {Xi [0058] “intermediate value exp2” shown e.g. Figs 9:940, 3:360 mux inputs, and [0076-77] “intermediate exponent value exp1 …output yexp = 127 + (127-xexp) / 2 = (381 - xexp) / 2” where xexp is input and yexp is output, shown Fig 6 see exp1 between 650 and 665 adders, input before 605 and output after 680. The (exp)onential is described with respect to reciprocal function that is introduced as equivalent softmax [0029]}
Xi is directed to devices for accelerating calculations including softmax using LUTs lookup tables thus being analogous. A person having ordinary skill in the art would have considered it obvious prior to the effective filing date to specify intermediate exponent values per Xi in combination as applying known techniques to known devices ready for improvement to yield predictable results and/or a motivation of “significant speed improvements and energy efficiency improvements” [0031], which may include adjusting the exponent values [0077], and using a multiplexer to select intermediate values [0058].
Finally, support for combination and motivation is provided by Yamano. Particularly, at [0066] product of exponential functions which can be seen as intermediate values for calculating softmax [0061-62], and specifies [0074] reads from lookup tables shown Figs 7B, 5:406,407 with indexes for each of the lookup tables being addressable [0103], as well as converting floating-point into fixed-point [0059,93]. Yamano is directed to devices for softmax calculation with lookup tables thus being analogous. A person having ordinary skill in the art would have considered it obvious prior to the effective filing date to employ the teachings of Yamano in combination to arrive at the invention as claimed for a motivation [0001,04] “speeding up numerical calculation of a softmax function… processing load of the softmax is reduced” e.g. [0124] “reduce the processing load… while suppressing the size of the look up table required to approximate the exponential function with high accuracy” see [0026-28] advantageous effects.
With respect claim 20, the combination of Petig, Xi and Yamano teaches the digital signal processing device of claim 19, wherein the first lookup table generator is further configured to:
calculate the first exponential function, based on the input scaling value and the size of the first lookup table {Petig [0043,47] “calculation of the exponential function for each input… uses a lookup table of a small size to reduce the calculation efforts” and the input being scaled [0059]}; and
generate the first lookup table having calculation results of the first exponential function as values corresponding to an index {Petig Fig 4:S10 “Generate Lookup Table T” described e.g. [0085-80] “lookup table T1 at the step S17 into said result register” with “size M of the lookup table T1 (the multiplication or scaling result be rounding to the nearest integer) to obtain a lookup index”}.
Petig further suggests [0050] “any other size of the lookup table T, preferably of the kind M-2m (m being an integer), can be used”. However, Petig does not appear to disclose the following limitation which is met by Xi:
set the size of the first lookup table to a smaller number from among: a smallest integer greater than or equal to a reciprocal number of the input scaling value, and a total amount of numbers representable using a number of bits of the first input value {Xi [0081] “lookup table 810 includes two tables with sizes of 32x12 bit and 16x12-bit. The smaller 16-entry table is selected when reciprocal is performed” size of lookup table is set by selecting described with respect to number of bits as well as reciprocal cont’d [0086] “reciprocal and reciprocal-square-root linear interpolation lookup table 810, the number of bits used in the pre-computed quantized slopes kq and the pre-computed quantized offsets eq, which affects the size of the lookup tables and the size of the integer multiplier” integer scaled by multiplier. The BRI of ‘among’ is comprising as an open-ended alternatives. See also [0099] “small sized lookup tables” };
A person having ordinary skill in the art would have considered it obvious prior to the effective filing date to set size of lookup table according to the teachings of Xie to arrive at the invention as claimed for a motivation [0099] “small sized lookup tables…make this technique very area efficient when targeting FPGAs with rich lookup table (LUT) resources” such that the small sized LUTs are less compute-intensive than large LUTs. This is confirmed by both Petig [0047] and Yamano [0026].
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Ham et al., “A3: Accelerating Attention Mechanisms in Neural Networks with Approximations” arXiv: 2002.10941v1 Seoul National Univ. Korea, see [P.4 ¶4] “multiplication of two exponent operations” math, e = e x e “two smaller lookup tables” softmax Fig 5 pseudocode, and Fig 4
Hsu et al., US Patent No 11,861,452B1 quantized softmax w/ lut index, intermediate values
Imber et al., US PG Pub No 2022/0391172A1 softmax exp lut hardware, Fig 11B
Akerib et al., US PG Pub No 2019/0114555A1 see [0049-50] Eqs.9-10 exp-product
Vasyltsov et al., US PG Pub No 2021/0117155A1 Samsung discloses softmax w/ luts
Yu et al., “NN-LUT: Neural Approximation of Non-Linear Operations for Efficient Transformer Inference” arXiv: 2112.02191v1 Hanyang Univ. Seoul Korea, see [Sect. 3.1-3.2]
Stevens et al., “SofterMax: Hardware/Software Co-Design of an Efficient Softmax for Transformers” arXiv: 2103.09301v1 see Fig 4
Conclusion
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/CHASE P. HINCKLEY/Examiner, Art Unit 2124
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