DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed January 29, 2026 has been entered. Claims 1-20 remain pending in the application. Applicant’s amendments to the specification and claims have overcome each and every objection previously presented in the Non-Final Office Action mailed October 29, 2025.
Response to Arguments
Applicant’s arguments, see page 10, filed January 29, 2026, with respect to the rejections of claims 1-20 under 35 U.S.C. § 101 have been fully considered and are persuasive. The rejections of claims 1-20 have been withdrawn.
Applicant’s arguments, see page 11, filed January 29, 2026, with respect to the rejections of claims 1-20 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art reference Mu (Patent Publication Number US 2018/0191312 A1), hereafter referred to as Mu.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 18/309,007 in view of Mu.
Regarding claim 1, claim 1 of the co-pending application recites most of the limitations recited in claim 1 of the present application. However, the present application additionally recites “wherein the first resistor is a programmable or variable resistor, wherein the second resistor is a programmable or variable resistor”.
However, Mu teaches wherein the first resistor is a programmable or variable resistor (Mu, Fig. 8, 400), wherein the second resistor is a programmable or variable resistor (Fig. 8, 400).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified claim 1 of the co-pending application to incorporate the teachings of Mu to implement the resistors of Seth as variable resistors, which would have the effect of enabling optimization of the resistance values of the resistors of Seth (Mu, Paragraph 38, lines 1-9). Therefore, claim 1 of the co-pending application meets claim 1 of the present application under an obviousness-type double patenting rejection.
Regarding claims 2-6, claims 2-6 of the co-pending application recite identical limitations to those recited in claims 2-6 of the present application, except for the feature of claim 1 addressed above. Therefore, claims 2-6 of the co-pending application meet claims 2-6 of the present application under an obviousness-type double patenting rejection.
Regarding claim 7, claim 7 of the co-pending application recites most of the limitations recited in claim 7 of the present application. However, the present application additionally recites “wherein the first resistor is a programmable or variable resistor, wherein the second resistor is a programmable or variable resistor”.
However, Mu teaches wherein the first resistor is a programmable or variable resistor (Mu, Fig. 8, 400), wherein the second resistor is a programmable or variable resistor (Fig. 8, 400).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified claim 7 of the co-pending application to incorporate the teachings of Mu to implement the resistors of Seth as variable resistors, which would have the effect of enabling optimization of the resistance values of the resistors of Seth (Mu, Paragraph 38, lines 1-9). Therefore, claim 7 of the co-pending application meets claim 7 of the present application under an obviousness-type double patenting rejection.
Regarding claims 8-14, claims 8-14 of the co-pending application recite identical limitations to those recited in claims 8-14 of the present application, except for the feature of claim 7 addressed above. Therefore, claims 8-14 of the co-pending application meet claims 8-14 of the present application under an obviousness-type double patenting rejection.
Regarding claim 15, claim 15 of the co-pending application recites most of the limitations recited in claim 15 of the present application. However, the present application additionally recites “wherein the first resistor is a programmable or variable resistor, wherein the second resistor is a programmable or variable resistor”.
However, Mu teaches wherein the first resistor is a programmable or variable resistor (Mu, Fig. 8, 400), wherein the second resistor is a programmable or variable resistor (Fig. 8, 400).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified claim 15 of the co-pending application to incorporate the teachings of Mu to implement the resistors of Seth as variable resistors, which would have the effect of enabling optimization of the resistance values of the resistors of Seth (Mu, Paragraph 38, lines 1-9). Therefore, claim 15 of the co-pending application meets claim 15 of the present application under an obviousness-type double patenting rejection.
Regarding claims 16-20, claims 16-20 of the co-pending application recite identical limitations to those recited in claims 16-20 of the present application, except for the feature of claim 15 addressed above. Therefore, claims 16-20 of the co-pending application meet claims 16-20 of the present application under an obviousness-type double patenting rejection.
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1 and 7 recite the limitations “wherein the first resistor is a programmable or variable resistor” and “wherein the second resistor is a programmable or variable resistor”. Applicant argues that these limitations are supported by paragraph 15 of the instant specification. Examiner respectfully disagrees.
The first and second resistors of paragraph 15 of the instant specification are not the same as the first and second resistors of claims 1 and 7. Paragraph 15 describes “[t]he first amplifier may be configured to generate a first current, based at least on a voltage sensed from the first signal and a resistance of the first resistor, to supply the first current as an additional current to the second signal traversing (or flowing) towards the interface. The second amplifier may be configured to generate a second current, based at least on a voltage sensed from the second signal and a resistance of the second resistor, to supply the second current as an additional current to the second signal traversing (or flowing) towards the interface.”
In other words, the first and second amplifiers set their output currents due to the resistances of the first and second resistors, respectively, and therefore the first and second resistors of paragraph 15 of the instant specification correspond to resistors 563 and 573 of Fig. 5A. See also Paragraph 51 of the instant specification describing resistors 563 and 573 of Fig. 5A: “The first amplifier 560 may be configured to generate a current 565 (Iout1), based at least on a voltage sensed from the first signal 562 (Si) and a resistance of the first resistor 563, to supply an additional current to the second signal572 (S2) traversing (or flowing) towards the interface 540. The second amplifier 570 may be configured to generate a current 575 (Iout2), based at least on a voltage sensed from the second signal572 (S2) and a resistance of the second resistor 573, to supply an additional current to the second signal 572 (S2) traversing (or flowing) towards the interface 540.”
This clearly shows that the first and second resistors of paragraph 15 have functions corresponding to resistors 563 and 573 of Fig. 5A, and therefore paragraph 15 refers to the resistors coupled between the outputs of the line driver and the inputs of the first and second amplifiers. While this does correspond to the first and second resistors as claimed in claim 15, claims 1 and 7 refer to resistors 531 and 532 of Fig. 5A as the first and second resistors, as both claims describe the first and second resistors being respectively coupled between the first and second output terminals of the line driver and the second and first amplifiers. See claim 1, lines 13-20 (and claimed analogously in claim 7): “the first amplifier is configured to generate a first current at the second end of the second resistor, based at least on a voltage sensed from the first signal, and to supply the first current as an additional current to the second signal traversing the second resistor towards the interface and the second amplifier is configured to generate a second current at the second end of the first resistor, based at least on a voltage sensed from the second signal, and to supply the second current as an additional current to the first signal traversing the first resistor towards the interface.”
In other words, the first resistor is coupled between the first output terminal of the line driver (with the input of the first amplifier) and the output current from the second amplifier, and the second resistor is coupled between the second output terminal of the line driver (with the input of the second amplifier) and the output current from the first amplifier. Therefore, the first and second resistors, as claimed in claims 1 and 7, correspond to resistors 531 and 532 of Fig. 5A of the instant specification. However, resistors 531 and 532 (and other analogous resistors from other embodiments) are never described as being programmable or variable resistors, and the figures show the resistors as being fixed resistors. Therefore, the claim limitations “wherein the first resistor is a programmable or variable resistor” and “wherein the second resistor is a programmable or variable resistor” are new matter and should be removed from claims 1 and 7. Claims 2-6 and 8-14 are likewise rejected under this logic by virtue of their dependencies on claims 1 and 7, respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Seth et al. (Patent Publication Number US 2019/0173429 A1), as cited by applicant, hereafter referred to as Seth, in view of Mu.
Regarding claim 1, Seth discloses:
A system (Seth, Figs. 2-3) comprising: a first amplifier (Figs. 2-3, 222a and path of 210 from 212a to 222a) and a second amplifier (Fig. 2, 222b and path of 210 from 212b to 222b), wherein the first amplifier and a first end of a first resistor are coupled to a first output terminal of a line driver to receive a first signal (Fig. 2, see connection between 212a, resistor 208b, and output 206b of line driver 202), the second amplifier and a first end of a second resistor are coupled to a second output terminal of the line driver to receive a second signal (Fig. 2, see connection between 212b, resistor 208a and output 206a of line driver 202), a second end of the second resistor and an output terminal of the first amplifier are connected to an interface to a physical medium (Fig. 2, see connection between 222a, 208b, and interface 110), a second end of the first resistor and an output terminal of the second amplifier are connected to the interface (Fig. 2, see connection between 222b, 208a, and interface 110), the first amplifier is configured to generate a first current at the second end of the second resistor (Fig. 2, see current IOUT2 provided from 222a), based at least on a voltage sensed from the first signal (Fig. 2, consider positive voltage VOUT1 at terminal 206a, and connection to IOUT2 via 210/222a), and to supply the first current as an additional current to the second signal traversing the second resistor towards the interface (Fig. 2, consider that output of 222a is coupled to signal output from resistor 208b and interface 110), and the second amplifier is configured to generate a second current at the second end of the first resistor (Fig. 2, see current IOUT2 provided from 222b), based at least on a voltage sensed from the second signal (Fig. 2, consider negative voltage VOUT1 at terminal 206b, and connection to IOUT2 via 210/222b), and to supply the second current as an additional current to the first signal traversing the first resistor towards the interface (Fig. 2, consider that output of 222b is coupled to signal output from resistor 208a and interface 110), but fails to disclose wherein the first resistor is a programmable or variable resistor, wherein the second resistor is a programmable or variable resistor.
However, Mu teaches wherein the first resistor is a programmable or variable resistor (Mu, Fig. 8, 400), wherein the second resistor is a programmable or variable resistor (Fig. 8, 400).
Seth and Mu are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Seth to incorporate the teachings of Mu to implement the resistors of Seth as variable resistors, which would have the effect of enabling optimization of the resistance values of the resistors of Seth (Mu, Paragraph 38, lines 1-9).
Regarding claim 2, Seth further discloses:
wherein each of the first amplifier and the second amplifier is a transconductance amplifier (Seth, Paragraph 16, lines 10-12).
Regarding claim 3, Seth further discloses:
wherein each of the first amplifier and the second amplifier comprises one or more common-gate transistors in an input stage (Seth, Fig. 3, consider common gate transistors MP1a and MN1a for the first amplifier and MP1b and MN1b for the second amplifier) and one or more common-gate transistors in an output stage (Fig. 3, consider common gate transistors MP2a and MN2a for the first amplifier and MP2b and MN2b for the second amplifier).
Regarding claim 4, Seth further discloses:
wherein each of the first amplifier and the second amplifier comprises a current mirror circuit configured to output a respective current in an output stage (Seth, Paragraph 23, lines 15-21 [consider IOUT2 as output current of the current mirror circuit shown in detail in Fig. 3]).
Regarding claim 5, Seth further discloses:
wherein at least one of the first amplifier or the second amplifier is a class AB amplifier (Seth, Paragraph 22, lines 1-6).
Regarding claim 6, Seth further discloses:
wherein each of the first resistor and the second resistor is coupled at an end of a respective transmission line coupled to the interface (Seth, Fig. 2, see connection between resistors 208a-b and interface 110, see also Paragraph 13, lines 4-9).
Regarding claim 7, Seth discloses:
A system (Seth, Figs. 2-3) comprising: a first amplifier (Figs. 2-3, 222a and path of 210 from 212a to 222a) and a first resistor (Fig. 2, 214a) coupled to an input terminal of the first amplifier (Fig. 2, see connection between 214a and 212a); and a second amplifier (Fig. 2, 222b and path of 210 from 212b to 222b) and a second resistor (Fig. 2, 214b) coupled to an input terminal of the second amplifier (Fig. 2, see connection between 214b and 212b), wherein a first end of the first resistor is coupled to a first output terminal of a line driver to receive a first signal (Fig. 2, see connection between 206a and 214a), a first end of the second resistor is coupled to a second output terminal of the line driver to receive a second signal (Fig. 2, see connection between 206b and 214b), an output terminal of the second amplifier is coupled to a first terminal of an interface to a physical medium (Fig. 2, see connection between 222b and 110), an output terminal of the first amplifier is coupled to a second terminal of the interface (Fig. 2, see connection between 222a and 110), the first amplifier is configured to generate a first current (Fig. 2, see current IOUT2 provided from 222a), based at least on a voltage sensed from the first signal (Fig. 2, consider positive voltage VOUT1 at terminal 206a, and connection to IOUT2 via 210/222a) and a resistance of the first resistor (Paragraph 26, lines 1-7), and to supply the first current as an additional current to the second signal flowing towards the interface (Fig. 2, consider that output of 222a is coupled to signal output from resistor 208b and interface 110), and the second amplifier is configured to generate a second current (Fig. 2, see current IOUT2 provided from 222b), based at least on a voltage sensed from the second signal (Fig. 2, consider negative voltage VOUT1 at terminal 206b, and connection to IOUT2 via 210/222b) and a resistance of the second resistor (Paragraph 26, lines 1-7), and to supply the second current as an additional current to the second signal flowing towards the interface (Fig. 2, consider that output of 222b is coupled to signal output from resistor 208a and interface 110), but fails to disclose wherein the first resistor is a programmable or variable resistor, wherein the second resistor is a programmable or variable resistor.
However, Mu teaches wherein the first resistor is a programmable or variable resistor (Mu, Fig. 8, 400), wherein the second resistor is a programmable or variable resistor (Fig. 8, 400).
Seth and Mu are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Seth to incorporate the teachings of Mu to implement the resistors of Seth as variable resistors, which would have the effect of enabling optimization of the resistance values of the resistors of Seth (Mu, Paragraph 38, lines 1-9).
Regarding claim 8, Seth further discloses:
wherein resistance of at least one of the first resistor or the second resistor is set such that the first amplifier and the second amplifier output a particular range of output voltages based at least on a voltage sensed from at least one of the first signal or the second signal (Paragraph 26, lines 1-7).
Regarding claim 9, Seth further discloses:
wherein each of the first amplifier and the second amplifier is a transconductance amplifier (Seth, Paragraph 16, lines 10-12).
Regarding claim 10, Seth further discloses:
wherein each of the first amplifier and the second amplifier comprises one or more common-gate transistors in an input stage (Seth, Fig. 3, consider common gate transistors MP1a and MN1a for the first amplifier and MP1b and MN1b for the second amplifier) and one or more common-gate transistors in an output stage (Fig. 3, consider common gate transistors MP2a and MN2a for the first amplifier and MP2b and MN2b for the second amplifier).
Regarding claim 11, Seth further discloses:
wherein each of the first amplifier and the second amplifier comprises a current mirror circuit configured to output a respective current in an output stage (Seth, Paragraph 23, lines 15-21 [consider IOUT2 as output current of the current mirror circuit shown in detail in Fig. 3]).
Regarding claim 12, Seth further discloses:
wherein at least one of the first amplifier or the second amplifier is a class AB amplifier (Seth, Paragraph 22, lines 1-6).
Regarding claim 13, Seth further discloses:
wherein a first end of a third resistor is coupled to the first output terminal of the line driver (Seth, Fig. 2, see connection between 208a and 206a), a first end of a fourth resistor is coupled to the second output terminal of the line driver (Fig. 2, see connection between 208b and 206b), a second end of the fourth resistor and the output terminal of the first amplifier are coupled to the interface (Fig. 2, see connection between 208b, 222a, and 110), and a second end of the third resistor and the output terminal of the second amplifier are coupled to the interface (Fig. 2, see connection between 208a, 222b, and 110).
Regarding claim 14, Seth further discloses:
wherein each of the third resistor and the fourth resistor is coupled at an end of a respective transmission line coupled to the interface (Seth, Fig. 2, see connection between resistors 208a-b and interface 110, see also Paragraph 13, lines 4-9).
Regarding claim 15, Seth further discloses:
A system (Seth, Figs. 2-3) comprising: circuitry configured to couple a first end of a first resistor to a first input terminal of a line driver (Fig. 2, see connection between 214a and input terminal 212a of 210), and couple a first end of a second resistor to a second input terminal of the line driver (Fig. 2, see connection between 214b and input terminal 212b of 210), wherein the circuitry is configured to receive, at a second end of the first resistor, a first signal (Fig. 2, see connection between 214a and signal 206a), receive, at a second end of the second resistor, a second signal (Fig. 2, see connection between 214b and signal 206b), and set resistance of at least one of the first resistor or the second resistor such that the line driver outputs a predetermined range of output voltages based at least on a voltage sensed from at least one of the first signal or the second signal (Paragraph 26, lines 1-7), but fails to disclose wherein the first resistor is a programmable or variable resistor, wherein the second resistor is a programmable or variable resistor.
However, Mu teaches wherein the first resistor is a programmable or variable resistor (Mu, Fig. 8, 400), wherein the second resistor is a programmable or variable resistor (Fig. 8, 400).
Seth and Mu are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Seth to incorporate the teachings of Mu to implement the resistors of Seth as variable resistors, which would have the effect of enabling optimization of the resistance values of the resistors of Seth (Mu, Paragraph 38, lines 1-9).
Regarding claim 16, Seth further discloses:
wherein the line driver includes at least one of a class AB line driver or a class B line driver (Seth, Paragraph 22, lines 1-6 [driver is class AB]).
Regarding claim 17, Seth further discloses:
wherein the second end of the first resistor is coupled to a first output terminal of another line driver (Fig. 2, see connection between 214a and positive output of 202), and the second end of the second resistor is coupled to a second output terminal of the another line driver (Fig. 2, see connection between 214b and negative output of 202).
Regarding claim 18, Seth further discloses:
wherein a first end of a third resistor and a first output terminal of the line driver are coupled to an interface to a physical medium (Seth, Fig. 2, see connection between 222a, 208b, and 110), a first end of a fourth resistor and a second output terminal of the line driver are coupled to the interface (Fig. 2, see connection between 222b, 208a, and 110), a second end of the fourth resistor is coupled to the second end of the first resistor (Fig. 2, see connection between 208a and 214a), and a second end of the third resistor is coupled to the second end of the second resistor (Fig. 2, see connection between 208b and 214b).
Regarding claim 19, Seth further discloses:
wherein each of the third resistor and the fourth resistor is coupled at an end of a respective transmission line coupled to the interface (Seth, Fig. 2, see connection between resistors 208a-b and interface 110, see also Paragraph 13, lines 4-9).
Regarding claim 20, Seth further discloses:
wherein the line driver is configured to generate a first current (Fig. 2, see current IOUT2 provided from 222a), based at least on (1) a voltage sensed from at least the first signal or the second signal (Fig. 2, consider positive voltage VOUT1 at terminal 206a, and connection to IOUT2 via 210/222a) and (2) at least one of a resistance of the first resistor or a resistance of the second resistor (Paragraph 26, lines 1-7), and to supply the first current as an additional current to at least one of the first signal or the second signal (Fig. 2, consider that output of 222a is coupled to signal output from resistor 208b and interface 110).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yu et al. (Patent Publication Number US 2024/0146263 A1) discloses (Fig. 5) a transconductance amplifier with common-gate and current mirror transistors.
Ito et al. (Patent Publication Number US 2007/0210869 A1) discloses (Fig. 4) an amplifier with common-gate and current mirror transistors.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843