DETAILED ACTION
1. Claims 1-35 have been examined and are pending.
Response to Arguments
2. Applicant's arguments filed 7/28/2026 have been fully considered but they are not persuasive. Examiner addresses each of Applicant’s concerns in the following response.
A. Pralea does disclose or suggest “receiving input data containing preamble samples from a user equipment via a communication network” (See Remarks, pages 12-14). In support of this argument, Applicant alleges that the mere introduction of PRACH structures is not sufficient to read on the limitation. Applicant includes the Figures 2 and 3, along with paragraphs [0030].
B. Examiner’s response to A above
Examiner respectfully disagrees. Applicant, although including paragraphs [0026-0030], does not include all portions of the above paragraphs. [0028] also states, “The receiver in the base station therefore continuously monitors the random access channels and search the signals received on the random access channels for predetermined sequences of symbols (sometimes referred to as the RACH preamble) in random access messages transmitted by a mobile equipment.”. In [0030], Pralea further states, “According to TS 36.211 (v12.5.0), LTE uses four different preamble formats for FDD operation and one for TDD operation; cf. table 5.7.1-1.”. Examiner notes both are sufficient to read on “receiving input data containing preamble samples from a user equipment via a communication network”.
C. Pralea does not disclose or suggest “generating downsampled data based on the first portion of the input data containing preamble information retrieved from the buffer via detector utilizing parameters stored in a parameter database” (See Remarks, pages 14-17). In support of his argument, Applicant contends the portions cited from Pralea do not disclose the above limitation, particular to Figures 3-4 and [0010-0011]. Applicant further responds to the arguments submitted in the action mailed 4/29/2026 by contending that Pralea does not disclose partitioning a PRACH signal.
D. Examiner’s response to C above
Examiner respectfully disagrees. Pralea expressly discloses that the function of generating downsampled data in accordance with the input data via a detector utilizing parameters stored in a parameter database is performed by a decimator component, 200 of Figure 5 with corresponding description in [0037-0040]. A decimator, along with downsampling described by Pralea (along with low-pass filtering), operates to reduce a sampling rate, and therefore may act (in concert with downsampling) as a sample rate converter.). One of ordinary skill in the art is aware that before downsampled data is generated, an input signal must first be partitioned and processed as sample data. Official Notice is not required to contend this feature, since partitioning input data at a digital signal receiver is so well-known. This feature is further disclosed with respect to [0046-0049], which explicitly discloses receiving a PRACH sample, partitioning the sample, and decimating, or downsampling, the sample. It is unknown the depth or the number of samples required to be defined as a “small number” of input samples. Therefore, Pralea discloses “generating downsampled data based on a small number of the input data containing preamble information stored in a buffer via a detector utilizing parameters stored in a parameter database”. Adequate support for this conclusion, that input data may be downsampled in a digital receiver, is described by US PGPub 2006/0274843 A1 to Koo et al. at [0063-0064], US PGPub 2011/0150157 A1 to Lee at [0030-0031], and US PGPub 2014/0169501 A1 to Nazarathy et al. at [0012-0013], all of which have been previously-supplied to the Applicant in the PTO-892 mailed on 11/16/2023.
E. Budampati does not disclose or suggest “buffering a first portion of the input data in a buffer having a storage capacity less than storing entire input data” and “buffering a second portion of the input data to the buffer for subsequent downsampled data generation” (See Remarks, pages 17-20). In support of this argument, Applicant contends that Budampati utilizes multiple buffers whereas the claimed invention uses one, singular buffer. Applicant further contends Budampati does not disclose storing a second portion and therefore cannot be considered, alone or in combination, to teach the features as cited by Budampati (Remarks, pages 19-20).
F. Examiner’s response to E above
Examiner respectfully disagrees. Budampati discloses buffering a first portion of the input data in a buffer having a storage capacity less than storing entire input data (Interpreted as buffering data before a maximum capacity is reached, and is disclosed by Budampati in at least [0079], wherein the size of the buffer may be sufficient to store a preamble.), Budampati further discloses and buffering a second portion of the input data in the buffer (Budampati: [0080-0081] for subsequent downsampled data generation [Interpreted as an intended use from buffering data and considered not to be required to be disclosed by the prior art of record. However, since Pralea discloses storing for the purposes of downsampling, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to buffer samples per a threshold buffer size, in view of Budampati and to buffer for an intended purpose, for example downsampling, in an effort to reduce the amount of data lost between buffering of samples (Budampati:[0122]). Examiner notes, as described in [0079], “Incoming data signal samples of this length are acquired and stored in the first buffer” which suggests that the input samples are plural, i.e., multiple preambles that have a length suitable for storage in this first buffer. In citing [0080-0081], Examiner suggests that the portions/samples of the plurality of preambles in the first buffer may be stored in another buffer for downsampled data generation, but this is NOT required to be disclosed by the prior art of record, since the limitation “for subsequent downsampled data generation” is considered an intended result for storing multiple preambles. It is Examiner’s position that input samples (preambles) of Budampati are stored in a first buffer, which necessarily includes first portions (first preambles) and second portions (second preambles).
Examiner respectfully maintains the rejections.
Claim Rejections - 35 USC § 103
3. The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
4. Claims 1-5, 10, 11, 15-18, and 23-33 are rejected under 35 U.S.C. 103 as being unpatentable over United States Patent Application Publication 2016/0373222 A1 to Pralea (hereinafter “Pralea”) in view of United States Patent Application Publication 2010/0075611 A1 to Budampati et al. (hereinafter “Budampati”).
Regarding Claim 1, Pralea discloses a method for identifying preamble information in a communication network, comprising:
receiving input data containing preamble samples from a user equipment via a communication network (Pralea: Figures 2-4 and [0026-0030] – corresponds to a base station receiving one or more uplink transmissions/frames/sub-frames/PRACH preambles from a UE.);
generating downsampled data based on a first portion of the input data containing preamble information retrieved from a buffer via a detector utilizing parameters stored in a parameter database (Pralea: [0046-0049] – corresponds to decimator/downsampler downsampling an input PRACH signal according to an initial sample and partitioning width configuration(s) retrieved from a look-up table which is arranged to store a set of configuration records each including initial sample and partitioning width configuration for a respective PRACH format, this PRACH format includes a preamble (see Pralea at Figures 3 and 4 with [0010] and [0011], respectively, and further with respect [0030-0032], [0036-0038], [0058], which corresponds to input data stored in a buffer. See also [0037-0038] with Figure 5. See also [0099] describing the decimation/downsampling includes a decimation factor as a configuration/parameter. Pralea discloses that the function of generating downsampled data in accordance with the input data via a detector utilizing parameters stored in a parameter database is performed by a decimator component, 200 of Figure 5 with corresponding description in [0037-0040]. A decimator, along with downsampling described by Pralea (along with low-pass filtering), operates to reduce a sampling rate, and therefore may act (in concert with downsampling) as a sample rate converter.);
generating a correlated output via operation of correlating selected amount of downsampled data in response to a signature sequence generated by a signature sequence generator (Pralea: [0030-0034] – a PRACH preamble includes a signature or sequence part, also defined as a Zadoff-Chu (ZC) sequence, adapted as preambles (this feature is known). See also [0043-0044] – “The root sequence resampling component 150 is arranged to generate a u-th Zadoff-Chu (ZC) root sequence x.sub.u(n) with length N.sub.ZC=839 in time domain using the PRACH root index u, which has been broadcast to the user equipment by the serving base station. The generated u-th Zadoff-Chu (ZC) root sequence x.sub.u(n) is supplied to the frequency-domain transform component DFT 151, which is arranged to convert the u-th Zadoff-Chu (ZC) root sequence x.sub.u(n) into a set of pilot frequency tones X.sub.u(k)=FFT(x.sub.u(n), 839).” Pralea discloses that the function of generating a correlated output via operation of correlating selected amount(s) of downsampled data is performed by a root sequence resampling component, 150, that takes as input from a reference sequence generator, 155, a Zadoff-Chu root sequence, which by its very design, includes sequences having constant amplitude and zero autocorrelation (CAZAC) sequences (Pralea: [0032], [0040-0043]). In [0044], Pralea further discloses that after multiplying by a complex conjugation for the extracted PRACH sequence, the frequency tones are converted into a number of samples. Then in [0050], Pralea discloses “The frequency shifter component 220 may apply a complex multiplication on the samples of the input signal blocks. The frequency shift configuration 222 may comprise a number of complex shift values equal to the number of samples of an input signal block. Each samples is complex multiplied with a respective one of the complex shift values. The complex shift values to be applied to obtain a desired frequency shift of the input signal blocks may be pre-calculated and stored in the look-up table 211 for being retrieved therefrom based on the required frequency shift to be applied to the input signal blocks.”, which necessarily suggests the function(s) of correlating selected amounts of downsampled data.); and
providing a preamble output in accordance with the correlated output through a performance of peak detection (Pralea: [0030-0034], [0044], [0098], [0109] – “The energy detection component 180 is coupled to the time-domain transform component (iFFT) 170 and arranged to identify received preamble sequences by detecting the time of peak correlation between received schedule request signal and preamble root sequence x.sub.u(n). The pattern detection component 190 is further configured to perform a pattern detection based on cross-correlation values in frequency domain between the output sequence and predefined patterns.” Pralea discloses “generating output samples representing a preamble output” in at least [0044] – “The energy detection component 180 is coupled to the time-domain transform component (iFFT) 170 and arranged to identify received preamble sequences by detecting the time of peak correlation between received schedule request signal and preamble root sequence x.sub.u(n).” Here, Pralea discloses a detector is operative to identify preamble sequences, which are output from the iFFT component.).
Although Pralea discloses buffering (storing) different portions of preamble data (Pralea at Figures 3 and 4 with [0010] and [0011], respectively, and further with respect [0030-0032], [0036-0038], [0058], which corresponds to input data stored in a buffer. See also [0037-0038] with Figure 5.), and further discloses buffering (storing sample) for the purposes of downsampling (Pralea: [0049-0050], [0053]), Pralea does not expressly disclose buffering a first portion of the input data in a buffer having a storage capacity less than storing entire input data and buffering a second portion of the input data in the buffer for subsequent…data generation.
However, these features cannot be considered new or novel in the presence of Budampati. Budampati is similarly concerned with wireless signal transmission and reception in a process control system (Budampati: [0002], [0004-0005]). Budampati further discloses buffering a first portion of the input data in a buffer having a storage capacity less than storing entire input data (Interpreted as buffering data before a maximum capacity is reached, and is disclosed by Budampati in at least [0079], wherein the size of the buffer may be sufficient to store a preamble.), and buffering a second portion of the input data in the buffer (Budampati: [0080-0081] for subsequent downsampled data generation [Interpreted as an intended use from buffering data and considered not to be required to be disclosed by the prior art of record. However, since Pralea discloses storing for the purposes of downsampling, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to buffer samples per a threshold buffer size, in view of Budampati and to buffer for an intended purpose, for example downsampling, in an effort to reduce the amount of data lost between buffering of samples (Budampati: [0122]).
Regarding Claim 2, the combination of Pralea and Budampati discloses the method of claim 1, wherein Pralea further discloses obtaining the signature sequence from a signature sequence generator (Pralea: [0098-0101] – corresponds to generating an output sequence that represents a decimated sequence from a frequency-domain decimator component. See also [0108-0111].).
Regarding Claim 3, the combination of Pralea and Budampati discloses the method of claim 1, wherein Pralea further discloses retrieving one or more parameters from the parameter database to a frequency shifter (Pralea: Figure 5 with [0049-0050] – corresponds to frequency shifter retrieving a frequency shifting configuration from a look-up table.).
Regarding Claim 4, the combination of Pralea and Budampati discloses the method of claim 1, wherein Pralea further discloses storing at least a portion of an uplink transmission in a buffer of preamble data for sampling (Pralea: [0049] – initial samples of the received PRACH signal is stored (buffer) as part of configuration data.).
Regarding Claim 5, the combination of Pralea and Budampati discloses the method of claim 1, wherein Pralea further discloses generating frequency shifted data via operation of frequency shifting of buffered preamble data based on one or more parameters (Pralea: [0038], [0050] – “An initial phase and the frequency shift configuration 222 to be applied by the frequency shifter component 220 on the inputted PRACH signal may be retrieved from a look-up table 222, which is arranged to store a set of configuration records each including initial phase and the frequency shift configuration for a respective PRACH. The frequency shifter component 220 may apply a complex multiplication on the samples of the input signal blocks. The frequency shift configuration 222 may comprise a number of complex shift values equal to the number of samples of an input signal block. Each samples is complex multiplied with a respective one of the complex shift values. The complex shift values to be applied to obtain a desired frequency shift of the input signal blocks may be pre-calculated and stored in the look-up table 211 for being retrieved therefrom based on the required frequency shift to be applied to the input signal blocks.”).
Regarding Claim 10, the combination of Pralea and Budampati discloses the method of claim 1, wherein Pralea further discloses identifying the signature sequence via a matrix of preamble formats (Pralea: Figure 8 with [0075] – PRACH signal with a preamble format. Pralea further discloses operating the invention for preamble/pattern (sequence) detection using Discrete Fourier Transform Spread Orthogonal Frequency Division Multiple (DFTS-OFDM) Access (also known as DFT-S-OFDM; see Pralea at [0001], [0048-0055], [0062-0063], [0068]) which necessarily uses DFT matrices to spread symbols in the frequency domain across a plurality of subcarriers, wherein the row of the matrix comprise particular subcarriers, and the columns comprise a specific frequency component. This is known and therefore disclosed by Pralea.).
Regarding Claim 11, the combination of Pralea and Budampati discloses the method of claim 1, wherein Pralea further discloses identifying an accumulated phase value for frequency shifting from the parameters (Pralea: [0046-0050] – for each received PRACH input signal, a set of configuration records each include an initial phase and frequency shift, which is a plurality of phase values corresponding to each received PRACH input signal.).
Regarding Claim 15, Pralea discloses a method for detecting preambles in a communication network, comprising:
storing a small number of received input samples containing preamble information in a local buffer (Pralea further discloses “receiving input samples” in at least Figures 2-4 and [0026-0030] – corresponds to a base station receiving one or more uplink transmissions/frames/sub-frames/PRACH preambles from a UE. [0046-0049] – corresponds to decimator/downsampler downsampling an input PRACH signal according to an initial sample and partitioning width configuration(s) retrieved from a look-up table which is arranged to store a set of configuration records each including initial sample and partitioning width configuration for a respective PRACH format, this PRACH format includes a preamble (see Pralea at Figures 3 and 4 with [0010] and [0011], respectively, and further with respect [0030-0032], [0036-0038], [0058]), which corresponds to input data stored in a buffer. See also [0037-0038] with Figure 5. See also [0099] describing the decimation/downsampling includes a decimation factor as a configuration/parameter.);
retrieving one or more parameters from a parameter database (Pralea: [0046-0049] – corresponds to decimator/downsampler downsampling an input PRACH signal according to an initial sample and partitioning width configuration(s) retrieved from a look-up table. See also [0037-0038] with Figure 5. See also [0099] describing the decimation/downsampling includes a decimation factor as a configuration/parameter.) and storing the parameters in an accumulated phase value storage in a frequency shifter (Pralea: [0038], [0050] – “An initial phase and the frequency shift configuration 222 to be applied by the frequency shifter component 220 on the inputted PRACH signal may be retrieved from a look-up table 222, which is arranged to store a set of configuration records each including initial phase and the frequency shift configuration for a respective PRACH. The frequency shifter component 220 may apply a complex multiplication on the samples of the input signal blocks. The frequency shift configuration 222 may comprise a number of complex shift values equal to the number of samples of an input signal block. Each samples is complex multiplied with a respective one of the complex shift values. The complex shift values to be applied to obtain a desired frequency shift of the input signal blocks may be pre-calculated and stored in the look-up table 211 for being retrieved therefrom based on the required frequency shift to be applied to the input signal blocks.” See also [0046-0050] – for each received PRACH input signal, a set of configuration records each include an initial phase and frequency shift, which is a plurality of phase values corresponding to each received PRACH input signal.);
receiving a frequency shift input generated by an external controller indicating an amount of frequency shift to be applied (Pralea: [0050] – “The frequency shifter component 220 is provided to apply a 7.5 kHz frequency shift to compensate the 12.5 sub-carrier guard and/or the frequency shift depending on the used frequency allocation to shift the inputted PRACH signal to zero center frequency. The frequency shifter component 220 is arranged to shift the frequency of the input signal blocks by a predefined frequency shift value.” The frequency shift may be pre-calculated and retrieved external from the frequency shifter component.);
generating an input via adding the frequency shift input and the parameters (Pralea: [0050] – “An initial phase and the frequency shift configuration 222 to be applied by the frequency shifter component 220 on the inputted PRACH signal may be retrieved from a look-up table 222, which is arranged to store a set of configuration records each including initial phase and the frequency shift configuration for a respective PRACH. The frequency shifter component 220 may apply a complex multiplication on the samples of the input signal blocks. The frequency shift configuration 222 may comprise a number of complex shift values equal to the number of samples of an input signal block. Each samples is complex multiplied with a respective one of the complex shift values. The complex shift values to be applied to obtain a desired frequency shift of the input signal blocks may be pre-calculated and stored in the look-up table 211 for being retrieved therefrom based on the required frequency shift to be applied to the input signal blocks.”); and
generating a frequency shifted data in response to the input and an input data retrieved from the local buffer (Pralea: [0038], [0050] – “An initial phase and the frequency shift configuration 222 to be applied by the frequency shifter component 220 on the inputted PRACH signal may be retrieved from a look-up table 222, which is arranged to store a set of configuration records each including initial phase and the frequency shift configuration for a respective PRACH. The frequency shifter component 220 may apply a complex multiplication on the samples of the input signal blocks. The frequency shift configuration 222 may comprise a number of complex shift values equal to the number of samples of an input signal block. Each samples is complex multiplied with a respective one of the complex shift values. The complex shift values to be applied to obtain a desired frequency shift of the input signal blocks may be pre-calculated and stored in the look-up table 211 for being retrieved therefrom based on the required frequency shift to be applied to the input signal blocks.”).
Although Pralea discloses buffering (storing) different portions of preamble data (Pralea at Figures 3 and 4 with [0010] and [0011], respectively, and further with respect [0030-0032], [0036-0038], [0058], which corresponds to input data stored in a buffer. See also [0037-0038] with Figure 5.), and further discloses buffering (storing sample) for the purposes of downsampling (Pralea: [0049-0050], [0053]), Pralea does not expressly disclose a buffer having a storage capacity less than storing entire input data.
However, these features cannot be considered new or novel in the presence of Budampati. Budampati is similarly concerned with wireless signal transmission and reception in a process control system (Budampati: [0002], [0004-0005]). Budampati further discloses a buffer having a storage capacity less than storing entire input data (Interpreted as buffering data before a maximum capacity is reached, and is disclosed by Budampati in at least [0079], wherein the size of the buffer may be sufficient to store a preamble.). However, since Pralea discloses storing for the purposes of downsampling, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to buffer samples per a threshold buffer size, in view of Budampati, in an effort to reduce the amount of data lost between buffering of samples (Budampati: [0122]).
Regarding Claim 16, the combination of Pralea and Budampati discloses the method of claim 15, wherein Pralea further discloses determining a phase value based on the input by a phase computation circuit (Pralea: [0050] – “An initial phase and the frequency shift configuration 222 to be applied by the frequency shifter component 220 on the inputted PRACH signal may be retrieved from a look-up table 222, which is arranged to store a set of configuration records each including initial phase and the frequency shift configuration for a respective PRACH.”).
Regarding Claim 17, the combination of Pralea and Budampati discloses the method of claim 16, wherein Pralea further discloses generating a complex sinusoid value based on the phase value via a phase conversion circuit (Pralea: [0050] – “An initial phase and the frequency shift configuration 222 to be applied by the frequency shifter component 220 on the inputted PRACH signal may be retrieved from a look-up table 222, which is arranged to store a set of configuration records each including initial phase and the frequency shift configuration for a respective PRACH. The frequency shifter component 220 may apply a complex multiplication on the samples of the input signal blocks. The frequency shift configuration 222 may comprise a number of complex shift values equal to the number of samples of an input signal block. Each samples is complex multiplied with a respective one of the complex shift values.”).
Regarding Claim 18, the combination of Pralea and Budampati discloses the method of claim 15, wherein Pralea further discloses generating a frequency shifted data includes multiplying the input data with a complex sinusoid value generated by a phase conversion circuit (Pralea: [0050] – “An initial phase and the frequency shift configuration 222 to be applied by the frequency shifter component 220 on the inputted PRACH signal may be retrieved from a look-up table 222, which is arranged to store a set of configuration records each including initial phase and the frequency shift configuration for a respective PRACH. The frequency shifter component 220 may apply a complex multiplication on the samples of the input signal blocks. The frequency shift configuration 222 may comprise a number of complex shift values equal to the number of samples of an input signal block. Each samples is complex multiplied with a respective one of the complex shift values.”).
Regarding Claim 23, the combination of Pralea and Budampati discloses the method of claim 15, wherein Pralea further discloses correlating selected amount of preamble samples with a signature sequence to generate a correlated output (Pralea: [0044] – “The correlated time signal samples z.sub.u(l) contains concatenated power delay profiles of the cyclic shift replicas of the preamble root sequence x.sub.u(n). The energy detection component 180 is coupled to the time-domain transform component (iFFT) 170 and arranged to identify received preamble sequences by detecting the time of peak correlation between received schedule request signal and preamble root sequence x.sub.u(n).”).
Regarding Claim 24, the combination of Pralea and Budampati discloses the method of claim 23, wherein Pralea further discloses performing peak detection on the correlated output to detect a transmitted preamble (Pralea: [0044] – “The correlated time signal samples z.sub.u(l) contains concatenated power delay profiles of the cyclic shift replicas of the preamble root sequence x.sub.u(n). The energy detection component 180 is coupled to the time-domain transform component (iFFT) 170 and arranged to identify received preamble sequences by detecting the time of peak correlation between received schedule request signal and preamble root sequence x.sub.u(n).”).
Regarding Claim 25, the combination of Pralea and Budampati discloses the method of claim 23, wherein Pralea further discloses identifying the signature sequence via a matrix of preamble formats (Pralea: Figure 8 with [0075] – PRACH signal with a preamble format. Pralea further discloses operating the invention for preamble/pattern (sequence) detection using Discrete Fourier Transform Spread Orthogonal Frequency Division Multiple (DFTS-OFDM) Access (also known as DFT-S-OFDM; see Pralea at [0001], [0048-0055], [0062-0063], [0068]) which necessarily uses DFT matrices to spread symbols in the frequency domain across a plurality of subcarriers, wherein the row of the matrix comprise particular subcarriers, and the columns comprise a specific frequency component. This is known and therefore disclosed by Pralea.).
Claims 26-29, directed to an apparatus comprising means-plus-function language, recite similar features as claims 1-4, respectively, and are therefore rejected upon the same grounds as claims 1-4. Please see above rejections of claims 1-4. Pralea further discloses the apparatus in at least Figures 5 and 12.
Claims 30-33, directed to an apparatus comprising means-plus-function language, recite similar features as claims 15-18, respectively, and are therefore rejected upon the same grounds as claims 15-18. Please see above rejections of claims 15-18. Pralea further discloses the apparatus in at least Figures 5 and 12.
5. Claims 6, 13, 19, and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Pralea and Budampati, and further in view of United States Patent 10,804,957 B1 to Rey et al. (hereinafter “Rey”).
Regarding Claim 6, the combination of Pralea and Budampati discloses the method of claim 1, wherein Pralea further discloses generating frequency shifted data via operation of frequency shifting of buffered preamble data based on one or more parameters (Pralea: [0038], [0050] – “An initial phase and the frequency shift configuration 222 to be applied by the frequency shifter component 220 on the inputted PRACH signal may be retrieved from a look-up table 222, which is arranged to store a set of configuration records each including initial phase and the frequency shift configuration for a respective PRACH. The frequency shifter component 220 may apply a complex multiplication on the samples of the input signal blocks. The frequency shift configuration 222 may comprise a number of complex shift values equal to the number of samples of an input signal block. Each samples is complex multiplied with a respective one of the complex shift values. The complex shift values to be applied to obtain a desired frequency shift of the input signal blocks may be pre-calculated and stored in the look-up table 211 for being retrieved therefrom based on the required frequency shift to be applied to the input signal blocks.”).
Pralea does not expressly disclose generating oversampled data through operation of oversampling frequency shifted data.
However, the concept of oversampling input signals to determine a PRACH/preamble is not new or novel given the presence of Rey. Rey is similarly concerned with preamble detection of frequency shifting signals (Rey: col. 1, line 63 through col. 2, line 20). Rey discloses generating oversampled data through operation of oversampling frequency shifted data (Rey: col. 3, lines 1-24 disclosing the preamble detection and generation of detectable preamble signals may be employed on a plurality of frequency shifting modulation techniques; col. 4, line 59 through col. 5, line 6 discloses applying oversampling to frequency domain samples converted from the phase domain (thus a frequency shift). See also Figure 5 with col. 6, line 55 through col. 7, line 7.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the preamble detection method of the combination in view of the preamble detection method of Rey to oversample input signals from the frequency domain (having been converted from the phase domain) for the reasons of increasing early packet detection (Rey: col. 2, lines 4-20).
Regarding Claim 13, the combination of Pralea and Budampati discloses the method of claim 1, but does not expressly disclose performing sample copying for an operation of oversampling.
However, Rey, similarly concerned with preamble detection (Rey: col. 1, line 63 through col. 2, line 20), discloses performing sample copying for an operation of oversampling (Rey: col. 7, lines 32-47 – part of the oversampling process includes repetition of the preamble pattern.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the preamble detection method of the combination in view of the preamble detection method of Rey to oversample input signals from the frequency domain (having been converted from the phase domain) for the reasons of increasing early packet detection (Rey: col. 2, lines 4-20).
Regarding Claim 19, the combination of Pralea and Budampati discloses the method of claim 15, wherein Pralea further discloses generating frequency shifted data via operation of frequency shifting of buffered preamble data based on one or more parameters (Pralea: [0038], [0050] – “An initial phase and the frequency shift configuration 222 to be applied by the frequency shifter component 220 on the inputted PRACH signal may be retrieved from a look-up table 222, which is arranged to store a set of configuration records each including initial phase and the frequency shift configuration for a respective PRACH. The frequency shifter component 220 may apply a complex multiplication on the samples of the input signal blocks. The frequency shift configuration 222 may comprise a number of complex shift values equal to the number of samples of an input signal block. Each samples is complex multiplied with a respective one of the complex shift values. The complex shift values to be applied to obtain a desired frequency shift of the input signal blocks may be pre-calculated and stored in the look-up table 211 for being retrieved therefrom based on the required frequency shift to be applied to the input signal blocks.”).
Pralea does not expressly disclose generating oversampled data through operation of oversampling frequency shifted data.
However, the concept of oversampling input signals to determine a PRACH/preamble is not new or novel given the presence of Rey. Rey is similarly concerned with preamble detection of frequency shifting signals (Rey: col. 1, line 63 through col. 2, line 20). Rey discloses generating oversampled data through operation of oversampling frequency shifted data (Rey: col. 3, lines 1-24 disclosing the preamble detection and generation of detectable preamble signals may be employed on a plurality of frequency shifting modulation techniques; col. 4, line 59 through col. 5, line 6 discloses applying oversampling to frequency domain samples converted from the phase domain (thus a frequency shift). See also Figure 5 with col. 6, line 55 through col. 7, line 7.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the preamble detection method of the combination in view of the preamble detection method of Rey to oversample input signals from the frequency domain (having been converted from the phase domain) for the reasons of increasing early packet detection (Rey: col. 2, lines 4-20).
Claim 34, dependent upon claim 30, recites similar features as claim 19 and is therefore rejected upon the same grounds as claim 19. Please see above rejection of claim 19.
6. Claims 7, 20, and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Pralea and Budampati, and further in view of United States Patent Application Publication 2011/0150157 A1 to Lee (hereinafter “Lee”).
Regarding Claim 7, the combination of Pralea and Budampati discloses the method of claim 1, wherein Pralea further discloses generating preamble samples via operation of downsampling…data based on one or more parameters (Pralea: [0046-0049] – corresponds to decimator/downsampler downsampling an input PRACH signal according to an initial sample and partitioning width configuration retrieved from a look-up table. See also [0037-0038] with Figure 5. See also [0099] describing the decimation/downsampling includes a decimation factor as a configuration/parameter.), but the combination does not expressly disclose generating preamble samples via operation of downsampling oversampled data based on one or more parameters.
However, this feature cannot be considered new or novel in the presence of Lee. Lee is similarly concerned with generating preamble sampling signals based on a sampled preamble signal (Lee: [0009]). Lee discloses generating preamble samples via operation of downsampling oversampled data based on one or more parameters (Lee: [0010-0012], [0028-0031], [0050-0053] – corresponds to generating a downsampled preamble signal by downsampling an oversampled preamble signal based on a symbol speed.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the preamble detection method of the combination in view of the preamble sampling method of Lee to downsample oversampled data for the reasons of estimating symbol timing of a preamble sample without the need for costly hardware implementations (Lee: [0007-0008]).
Regarding Claim 20, the combination of Pralea and Budampati discloses the method of claim 15, wherein Pralea further discloses generating preamble samples via operation of downsampling…data based on one or more parameters (Pralea: [0046-0049] – corresponds to decimator/downsampler downsampling an input PRACH signal according to an initial sample and partitioning width configuration retrieved from a look-up table. See also [0037-0038] with Figure 5. See also [0099] describing the decimation/downsampling includes a decimation factor as a configuration/parameter.), but the combination does not expressly disclose generating preamble samples via operation of downsampling oversampled data based on one or more parameters.
However, this feature cannot be considered new or novel in the presence of Lee. Lee is similarly concerned with generating preamble sampling signals based on a sampled preamble signal (Lee: [0009]). Lee discloses generating preamble samples via operation of downsampling oversampled data based on one or more parameters (Lee: [0010-0012], [0028-0031], [0050-0053] – corresponds to generating a downsampled preamble signal by downsampling an oversampled preamble signal based on a symbol speed.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the preamble detection method of the combination in view of the preamble sampling method of Lee to downsample oversampled data for the reasons of estimating symbol timing of a preamble sample without the need for costly hardware implementations (Lee: [0007-0008]).
Claim 35, dependent upon claim 30, recites similar features as claims 7 and 20, and is therefore rejected upon the same grounds as claims 7 and 20. Please see above rejections of claims 7 and 20.
7. Claims 8, 9, 21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Pralea and Budampati, and further in view of United States Patent Application Publication 2020/0413239 A1 to Pu et al. (hereinafter “Pu”).
Regarding Claim 8, the combination of Pralea and Budampati discloses the method of claim 1, but the combination does not expressly disclose updating values of one or more parameters in response to sampling process and storing updated parameters in the parameter database.
However, this feature cannot be considered new or novel in the presence of Pu. Pu is similarly concerned with preamble detection (Pu: [0078-0079], [0102-0106]). Pu further discloses updating values of one or more parameters in response to sampling process and storing updated parameters in a parameter database (Pu: [0118], [0128-0129] – a parameter database for refining parameter estimations on a set (a plurality) of signal samples may be updated to include timing and peak candidates.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the preamble detection method of the combination in view of the preamble sampling method of Pu “to improve the likelihood of correctly detecting a discovery signal and/or to reduce the need for transmission repetitions that may come at a high power cost and/or that may increase connection setup delays” (Pu: [0129]).
Regarding Claim 9, the combination of Pralea and Budampati discloses the method of claim 1, but the combination does not expressly disclose repeating sampling operations until a selected amount of preamble samples is obtained.
However, Pu discloses, in a similar field of endeavor related to preamble detection (Pu: [0078-0079], [0102-0106]), repeating sampling operations until a selected amount of preamble samples is obtained (Pu: [0081] – a desired number of samples are collected to perform further iterations of the sampling process.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the preamble detection method of the combination in view of the preamble sampling method of Pu “to further improve the estimation accuracy” (Pu: [0081]).
Regarding Claim 21, the combination of Pralea and Budampati discloses the method of claim 15, but the combination does not expressly disclose updating values of one or more parameters in response to sampling process and storing updated parameters in the parameter database.
However, this feature cannot be considered new or novel in the presence of Pu. Pu is similarly concerned with preamble detection (Pu: [0078-0079], [0102-0106]). Pu further discloses updating values of one or more parameters in response to sampling process and storing updated parameters in a parameter database (Pu: [0118], [0128-0129] – a parameter database for refining parameter estimations on a set (a plurality) of signal samples may be updated to include timing and peak candidates.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the preamble detection method of the combination in view of the preamble sampling method of Pu “to improve the likelihood of correctly detecting a discovery signal and/or to reduce the need for transmission repetitions that may come at a high power cost and/or that may increase connection setup delays” (Pu: [0129]).
Regarding Claim 22, the combination of Pralea and Budampati discloses the method of claim 15, but the combination does not expressly disclose repeating sampling operations until a selected amount of preamble samples is obtained.
However, Pu discloses, in a similar field of endeavor related to preamble detection (Pu: [0078-0079], [0102-0106]), repeating sampling operations until a selected amount of preamble samples is obtained (Pu: [0081] – a desired number of samples are collected to perform further iterations of the sampling process.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the preamble detection method of the combination in view of the preamble sampling method of Pu “to further improve the estimation accuracy” (Pu: [0081]).
8. Claims 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Pralea and Budampati, and further in view of United States Patent Application Publication 2016/0337891 A1 to Seely (hereinafter “Seely”).
Regarding Claim 12, the combination of Pralea and Budampati discloses the method of claim 1, wherein Pralea further discloses identifying filter states represented by accumulator values…from one or more parameters (Pralea: [0038], [0046-0047], [0051-0052] – applying a filtering sequence to a number of PRACH samples (accumulated value) includes retrieving the filtering configuration (a state) from a look-up table (parameters).), but the combination does not expressly disclose this representation for all stages in a cascaded integrator comb (“CIC”) downsampler.
However, this feature cannot be considered new or novel in the presence of Seely. Seely is similarly concerned with determining a preamble based on one or more parameters (Seely: [0035]). Seely discloses identifying filter states for all stages in a cascaded integrator comb (“CIC”) downsampler (Seely: [0062-0063] – a CIC decimator includes at least an up-sampling stage and a down-sampling stage. [0078-0106] – the state includes a number of stages and the number of samples per stage, and a comb filter is applied at each stage. See also Figures 4 and 6, [0049], and [0152-0159] further disclosing detecting a preamble based on values for decoding from a down sampler.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the preamble detection method of the combination in view of the preamble detection method of Seely to include a cascaded integrator comb (CIC) to reduce noise and interference in preamble detection (Seely: [0035]).
Regarding Claim 14, the combination of Pralea and Budampati discloses the method of claim 1, but does not expressly disclose performing downsampling via a process of oversampled data with a cascaded integrator comb (“CIC”) downsampler.
However, Seely, similarly concerned with determining a preamble based on one or more parameters (Seely: [0035]), further discloses performing downsampling via a process of oversampled data with a cascaded integrator comb (“CIC”) downsampler (Seely: [0062-0063] – a CIC decimator includes at least an up-sampling stage and a down-sampling stage.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the preamble detection method of the combination in view of the preamble detection method of Seely to include a cascaded integrator comb (CIC) to reduce noise and interference in preamble detection (Seely: [0035]).
Conclusion
9. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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BENJAMIN H. ELLIOTT IV
Primary Examiner
Art Unit 2474
/BENJAMIN H ELLIOTT IV/Primary Examiner, Art Unit 2474 September 4, 2026
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