Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 1/12/2026 have been fully considered but they are not persuasive. Applicant amended the claims to include “configured to provide variable capacitance” in claim 1, “the providing of load modulation including providing variable capacitance” in claim 17, and “and configured to provide variable capacitance” in claim 28. However, Eplett discloses such added limitations as describes in rejection below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 5, 7, 10, 17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eplett (US 20130307624 A1).
Regarding Independent Claim 1, Eplett teaches,
A power amplifier circuit (Fig. 7, 704) comprising:
a power amplifier (Fig. 7, 700) having an input node (Fig. 7, input of amplifier 700) and an output node (Fig. 7, output of amplifier 700);
a load modulation circuit (Fig. 7, Impedance Transformation) coupled to the output node of the power amplifier (Fig. 7), the impedance transformation is coupled to the output node of amplifier 700) and configured to provide variable capacitance (“The first phase and amplitude control circuit 804 includes a capacitor 816, a variable or selectable blocking capacitor 818, a transistor 820, and a current source 822. The second phase and amplitude control circuit 806 includes two capacitors 824, 826, a variable or selectable blocking capacitor 828, and a programmable resistor 830.” [0034] Eplett);
a phase compensation circuit (Fig. 7, 712 and 716) implemented in the input node side of the power amplifier (Fig. 7, 702 is implemented on the input side of 700); and
a control circuit configured (Fig. 7, 714 and 718) to provide a control signal (Fig. 7, signal from 714 and 718) to the load modulation circuit [See paragraph [0029], “The amplitude control circuit 612 and the phase control circuit 614 produce a signal that is received by the second detection circuit 610 input so that the detection circuit 610 produces an output signal that is proportional to the forward power output of the power amplifier 600”] based on a first current representative of a tunable reference current (Fig. 7, current from 712 and 714) and a second current representative of a saturation detection current (Fig. 7, current from 716 and 718) [See paragraph [0032], “the signal produced by the first phase and amplitude control circuits 712, 714 and the signal produced by the second phase and amplitude control circuits 716, 718 are summed in the detection circuit 710 to produce a summed RF signal.”].
Regarding claim 2,
The power amplifier circuit of claim 1
wherein the control circuit (Fig. 7, 714 and 718) includes a translinear multiplier circuit (Fig. 7, 702) configured to generate the control signal that is proportional to the first current and the second current [See paragraph [0034], “Referring now to FIG. 8, an example summing detection circuit is disclosed that illustrates the detector shown in FIG. 7.” And paragraph [0035], “The detection circuit creates a direct current (DC) voltage that is proportional to the amplitude of the RF signal at the summing node 808. The DC voltage produced by the detection circuit 702 is also proportional to the voltage associated with the power of the signal output from the power amplifier.”].
Regarding claim 4,
The power amplifier circuit of claim 1
wherein the control circuit (Fig. 7, 714 and 718) is further configured to provide a control signal (Fig. 7, signal from 714 and 718) to the phase compensation circuit (Fig. 7, 712 and 716) based on a third current (Fig. 8, current from 822. [See paragraph [0034, “Referring now to FIG. 8, an example summing detection circuit is disclosed that illustrates the detector shown in FIG. 7.”]) representative of a tunable reference current and the second current [See paragraph [0035], “The detection circuit creates a direct current (DC) voltage that is proportional to the amplitude of the RF signal at the summing node 808. The DC voltage produced by the detection circuit 702 is also proportional to the voltage associated with the power of the signal output from the power amplifier.”].
Regarding claim 5,
The power amplifier circuit of claim 4 wherein the control circuit (Fig. 7, 714 and 718) includes a translinear multiplier circuit (Fig. 7, 702) configured to generate the control signal that is proportional to the third current and the second current.
Regarding claim 7,
The power amplifier circuit of claim 1
wherein the power amplifier (Fig. 7, 700) includes an input stage (Fig. 7, input of 700) and an output stage (Fig. 7, 706).
Regarding claim 10,
The power amplifier of claim 9 wherein the input stage is implemented as a driver stage (Fig. 7, the amplifiers coupled to 706 are part of the input stage and function as drivers), and the output stage is implemented as a final stage [See paragraph [0031], “a final gain stage 706 of the power amplifier 700 has an input and an output and a feedback loop 708 coupled between the input and output.”].
Regarding independent claim 17,
A method for amplifying a radio-frequency signal (Fig. 7, 704), the method comprising:
receiving a signal (Fig. 7, signal received at input of 700) at an input node (Fig. 7, input of 700);
providing a phase shift (Fig. 7, 712 and 716 perform a phase shift) for the signal with a phase shifting circuit (Fig. 7, 712 and 716);
amplifying (Fig. 7, 700) the phase shifted signal; and
providing load modulation (Fig. 7, Impedance Transformation) for the amplified signal by providing a control voltage (Fig. 7, voltage from 714 and 718) that is based on a first current representative of a tunable reference current (Fig. 7, current from 712 and 714), the providing of load modulation including providing variable capacitance (“The first phase and amplitude control circuit 804 includes a capacitor 816, a variable or selectable blocking capacitor 818, a transistor 820, and a current source 822. The second phase and amplitude control circuit 806 includes two capacitors 824, 826, a variable or selectable blocking capacitor 828, and a programmable resistor 830.” [0034] Eplett) and a second current representative of a saturation detection current (Fig. 7, current from 716 and 718) [See paragraph [0032], “the signal produced by the first phase and amplitude control circuits 712, 714 and the signal produced by the second phase and amplitude control circuits 716, 718 are summed in the detection circuit 710 to produce a summed RF signal.”].
Regarding claim 19,
The method of claim 17 wherein the phase shift is provided by a control signal from the control circuit (Fig. 7, signal from 714 and 718) based on a third current representative of a tunable reference current and the second current [See paragraph [0034], “Referring now to FIG. 8, an example summing detection circuit is disclosed that illustrates the detector shown in FIG. 7.” And paragraph [0035], “The detection circuit creates a direct current (DC) voltage that is proportional to the amplitude of the RF signal at the summing node 808. The DC voltage produced by the detection circuit 702 is also proportional to the voltage associated with the power of the signal output from the power amplifier.”].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 6, 8, 9, 11, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Eplett in view of Chen et al. (US 20200266768 A1), hereinafter Chen.
Regarding claim 3, Eplett is silent regarding:
The power amplifier circuit of claim 2 wherein the first current includes an AMAM current.
Chen discloses:
wherein the first current includes an AMAM current [See paragraph [0160], “The AM-AM and AM-PM transfer function of the PA were measured by sweeping the amplitude codes (FIG. 20). The AM-AM performance of the PA was found to be superior because of the custom-designed precision of the MIM capacitors. Note that the AM-PM characteristic showed a few ripples between codes 85 and 169. This effect was caused by changing supplies and input-switching frequencies simultaneously between the second- and third-efficiency peaks (−3.5- to −9.5-dB PBO), which agrees well with the correct operation. The AM-AM and AM-PM characteristics were used to generate the LUTs for PA pre-distortion.”].
Eplett and Chen are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include an AM-AM current in Eplett’s design in order to increase the performance of the amplifier due to the custom-designed precision of the MIM capacitors in accordance with Chen’s design.
Regarding claim 6, Eplett is silent regarding:
The power amplifier circuit of claim 2 wherein the third current includes an AMPM current.
Chen discloses:
wherein the third current includes an AMPM current [See paragraph [0160], “The AM-AM and AM-PM transfer function of the PA were measured by sweeping the amplitude codes (FIG. 20). The AM-AM performance of the PA was found to be superior because of the custom-designed precision of the MIM capacitors. Note that the AM-PM characteristic showed a few ripples between codes 85 and 169. This effect was caused by changing supplies and input-switching frequencies simultaneously between the second- and third-efficiency peaks (−3.5- to −9.5-dB PBO), which agrees well with the correct operation. The AM-AM and AM-PM characteristics were used to generate the LUTs for PA pre-distortion.”].
Eplett and Chen are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include an AM-PM current in Eplett’s design in order to increase the performance of the amplifier due to the non-linearity from the different PBO region of the PA operation, which matches the hybrid operation in accordance with Chen’s design.
Regarding claim 8, Eplett discloses:
The power amplifier circuit of claim 8 wherein the saturation detection current is obtained based on detection of saturation at an input of the output stage (Fig. 7, the detection circuit 710 has an input coupled to the stage 706 and detects a signal from stage 706 and feedback 708).
Regarding claim 9, Eplett discloses:
The power amplifier circuit of claim 8 wherein the phase compensation circuit (Fig. 7, 712 and 716) is implemented at an input of the input stage (Fig. 7, 712 is coupled to the input stage of 700).
Regarding claim 11, Eplett discloses:
The power amplifier circuit of claim 10 wherein the driver stage (Fig. 7, the amplifiers coupled to 706 are part of the input stage and function as drivers) is implemented as a cascode driver stage (Fig. 7, the amplifiers coupled to 706 are implemented in a cascode configuration).
Regarding claim 18, Eplett is silent regarding:
The method of claim 17 wherein the first current includes an AMAM current.
Chen discloses:
wherein the first current includes an AMAM current [See paragraph [0160], “The AM-AM and AM-PM transfer function of the PA were measured by sweeping the amplitude codes (FIG. 20). The AM-AM performance of the PA was found to be superior because of the custom-designed precision of the MIM capacitors. Note that the AM-PM characteristic showed a few ripples between codes 85 and 169. This effect was caused by changing supplies and input-switching frequencies simultaneously between the second- and third-efficiency peaks (−3.5- to −9.5-dB PBO), which agrees well with the correct operation. The AM-AM and AM-PM characteristics were used to generate the LUTs for PA pre-distortion.”].
Eplett and Chen are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include an AM-AM current in Eplett’s design in order to increase the performance of the amplifier due to the custom-designed precision of the MIM capacitors in accordance with Chen’s design.
Claims 12 – 16 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Eplett in view of Beltran et al. (US 20160164474 A1), hereinafter Beltran.
Regarding claim 12, Eplett is silent regarding:
The power amplifier of claim 11 wherein the cascode driver stage is configured to operate with a Class AB bias.
Beltran discloses:
wherein the cascode driver stage is configured to operate with a Class AB bias [See paragraph [0049], “Further, linearity achieved by the PA 100 of FIGS. 2 and 7 (without the digital pre-distortion) can be similar to linearity performance associated with a class-AB single-ended amplifier.”].
Eplett and Beltran are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a driver stage is configured to operate with a Class AB bias in Eplett’s design in order to offer a practical balance of high fidelity and good efficiency, eliminating the crossover distortion in accordance with Beltran’s design.
Regarding claim 13, Eplett is silent regarding:
The power amplifier circuit of claim 8 wherein the final stage is implemented as a push-pull amplifier [See paragraph [0011], “the peaking amplifier can be further configured to operate in a similar manner as a push-pull amplifier where an RF current from the carrier amplifier is influenced by an RF current from the peaking amplifier.”].
Eplett and Beltran are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a push-pull amplifier in Eplett’s design in order to reduce even-harmonics thereby improving linearity in accordance with Beltran’s design.
Regarding claim 14, Eplett is silent regarding:
The power amplifier of claim 13 wherein the push-pull amplifier includes a splitter having an input and a pair of outputs, each output coupled to an input of a respective amplifier, the push-pull amplifier further including a combining circuit that combines outputs of the pair of amplifiers.
Beltran discloses:
wherein the push-pull amplifier includes a splitter (Fig. 2 and 3, divider 104) having an input (Fig. 3, 150) and a pair of outputs (Fig. 3, 162 and 168), each output coupled to an input of a respective amplifier (Fig. 2, 162 is coupled to the carrier amplifier and 168 is coupled to the peaking amplifier), the push-pull amplifier further including a combining circuit (Fig. 2, combiner 144) that combines outputs of the pair of amplifiers.
Eplett and Beltran are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a push-pull amplifier comprising a splitter and a combiner in Eplett’s design in order to split the input between the amplifiers and then combine the output of the amplifiers in accordance with Beltran’s design.
Regarding claim 15, Eplett is silent regarding:
The power amplifier of claim 14 wherein each of the pair of amplifiers is configured to operate with a Class AB bias.
Beltran discloses:
wherein each of the pair of amplifiers is configured to operate with a Class AB bias [See paragraph [0049], “Further, linearity achieved by the PA 100 of FIGS. 2 and 7 (without the digital pre-distortion) can be similar to linearity performance associated with a class-AB single-ended amplifier.”].
Eplett and Beltran are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a driver stage is configured to operate with a Class AB bias in Eplett’s design in order to offer a practical balance of high fidelity and good efficiency, eliminating the crossover distortion in accordance with Beltran’s design.
Regarding claim 16, Eplett is silent regarding:
The power amplifier of claim 14 wherein the combining circuit includes a transformer circuit having a primary with first and second nodes coupled to the outputs of the pair of amplifiers, and a secondary with first and second nodes, the first node coupled to an output node and the second node coupled to ground through the load modulator.
Beltran discloses:
wherein the combining circuit (Fig. 2, combiner 144) includes a transformer circuit [See paragraph [0050], “the combiner 144 of FIG. 2 can be implemented as or similar to a lumped-element balanced to unbalanced (BALUN) transformer.”] having a primary with first and second nodes coupled to the outputs of the pair of amplifiers (Fig. 2, combiner 144 is coupled to the output of the pair of amplifiers), and a secondary with first and second nodes (Fig. 2, output nodes of combiner 144), the first node coupled to an output node (Fig. 2, a node from combiner 144 is coupled to the output) and the second node coupled to ground through the load modulator [See paragraph [0012], “the LC BALUN transformer can include a first path that couples an output of the carrier amplifier to an output node, and a second path that couples an output of the peaking amplifier to the output node. In some embodiments, each of the first path and the second path can include a harmonic trap. In some embodiments, the harmonic trap can include a second harmonic trap having an LC shunt to ground and a series inductance.”].
Eplett and Beltran are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a transformer circuit in Eplett’s design in order to provide voltage regulation in accordance with Beltran’s design.
Regarding independent claim 28, Eplett discloses:
A wireless device comprising:
an antenna; and
an amplifier circuit (Fig. 7, 704) configured to amplify a radio-frequency signal associated with the antenna, the amplifier circuit including an amplifier (Fig. 7, 700), a load modulation circuit (Fig. 7, Impedance Transformation) coupled to an output of the amplifier (Fig. 7, the impedance transformation is coupled to the output node of amplifier 700), and configured to provide variable capacitance (“The first phase and amplitude control circuit 804 includes a capacitor 816, a variable or selectable blocking capacitor 818, a transistor 820, and a current source 822. The second phase and amplitude control circuit 806 includes two capacitors 824, 826, a variable or selectable blocking capacitor 828, and a programmable resistor 830.” [0034] Eplett), and a phase compensation circuit (Fig. 7, 712 and 716) implemented on an input side of the amplifier (Fig. 7, 702 is implemented on the input side of 700), the amplifier circuit further including a control circuit (Fig. 7, 714 and 718) configured to provide a control signal (Fig. 7, signal from 714 and 718) to the load modulation circuit based on a first current representative of a tunable reference current (Fig. 7, current from 712 and 714) and a second current representative of a saturation detection current (Fig. 7, current from 716 and 718) [See paragraph [0032], “the signal produced by the first phase and amplitude control circuits 712, 714 and the signal produced by the second phase and amplitude control circuits 716, 718 are summed in the detection circuit 710 to produce a summed RF signal.”].
Eplett is silent regarding:
A wireless device comprising:
an antenna.
Beltran discloses:
A wireless device (Fig. 11, 400) comprising:
an antenna (Fig. 11, 416);
Eplett and Beltran are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include an antenna in Eplett’s design in order to be able to transfer signals in accordance with Beltran’s design.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE E PINERO whose telephone number is (703)756-4746. The examiner can normally be reached M-F 8:00 AM - 5:00 PM (ET).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached on (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSE E PINERO/Examiner, Art Unit 2843
/JOHN W POOS/Primary Examiner, Art Unit 2843
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