Prosecution Insights
Last updated: April 19, 2026
Application No. 18/142,482

USING MACHINE TRAINED NETWORK DURING ROUTING TO PERFORM PARASITIC EXTRACTION FOR AN IC DESIGN

Non-Final OA §102
Filed
May 02, 2023
Examiner
ALAM, MOHAMMED
Art Unit
2851
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
D2S Inc.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
2y 2m
To Grant
99%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allow Rate
763 granted / 828 resolved
+24.1% vs TC avg
Moderate +7% lift
Without
With
+6.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
20 currently pending
Career history
848
Total Applications
across all art units

Statute-Specific Performance

§101
16.2%
-23.8% vs TC avg
§103
9.3%
-30.7% vs TC avg
§102
49.5%
+9.5% vs TC avg
§112
21.6%
-18.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 828 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Non-Final Office Action DETAILED ACTION Examiner’s Notes (a) Claim date: 05/02/23. (b) Priority date: 05/02/22. (c) Invention: EDA tool using Machine learning for parasitic based routing optimization. Claim Rejections - 35 USC 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless: (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 , 4-7, 11, 14-20 , are rejected under 35 U.S.C. 102(a)(1) as being anticipated by the prior art of record “ LIN ” < US- 20190114381 >. (As to claim 1, 11, LIN discloses): 1. A method of performing routing to define a plurality of routes for a plurality of nets in an integrated circuit (IC) design layout, the method comprising [0027: “ layout generation by integrating placement, routing ”] : performing a first routing operation to define a first set of one or more routes for a first set of one or more nets [007: “ routing patterns of a plural of nets in a capacitor network”] ; supplying the first set of routes to a machine-trained network (MTN) to identify a group of one or more parasitic couplings on a group of one or more routes in the set of routes [0036: “capacitor sizing and parasitic matching sequence (CP-sequence) is introduced, which represents the unit capacitor size, routing topology, and routing patterns. Based on the CP-sequence, the genetic algorithm (D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning ”] ; based on the identified parasitic effect, discarding one or more routes in the first set of routes [ Refer to Fig. 1 along with Para 34 and35. Please note that based on the identified parasitic effect (106), acceptance (1114, Yes) or rejection (114, No) of routing is taking place . The “No” branch of 114 continues until optimized routing (i.e. having right parasitic) is obtained . Note: claim limitation “rout” is interpreted as a pre-defined path having predefined parasitic. Once the parasitic change, the rout is considered to be no longer the same even though it may follow the same tracking path (i.e. any change in the rout property makes an existing rout to become a new rout). ] ; and performing a second routing operation to define a new route for any net that had a route discarded from the first set of routes [ Fig. 1, 116 ] [Fig. 2a..2c further depicts how routing algorithm helps becoming selective based on the parasites] . (As to claim 4, 14, LIN discloses): 4. The method of claim 1, wherein the MTN is trained to output a set of parasitic coupling values for at least one route in the first set of routes [0036: “Based on the CP-sequence, the genetic algorithm (D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning ”] [0048: ““ Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits,” IEEE Trans. Comput.-Aided Design”] . (As to claim 5, 15, 17, LIN discloses): 5. The method of claim 4, wherein the set of parasitic coupling values comprise a set of parasitic capacitance values [0048: ““ Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits,” IEEE Trans. Comput.-Aided Design Integr”] . (As to claim 6, 16, LIN discloses): 6. The method of claim 1, wherein the MTN is trained to output a set of parasitic parameters, the method further comprising supplying the parasitic parameters to a solver to compute the set of parasitic coupling values for at least one route in the first set of routes [0036: “Based on the CP-sequence, the genetic algorithm (D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning ”] [0048: ““ Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits,” IEEE Trans. Comput er .-Aided Design”] . (As to claim 7, LIN discloses): 7. The method of claim 6, wherein the set of parasitic coupling values comprise a set of parasitic capacitance values [0048: ““ Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits,” IEEE Trans. Comput er -Aided Design”] . (As to claim 18, LIN discloses): 18. The non-transitory machine readable medium of claim 17, wherein the set of parasitic coupling values comprises for at least one particular net's route an overall parasitic coupling value representing parasitic coupling on the particular net's route from a plurality of components that neighbor that particular net's route [0048: “ Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits,” IEEE Trans. Comput.-Aided Design”] [Note: Coupling always happens among neighboring routs] . (As to claim 19, LIN discloses): 19. The non-transitory machine readable medium of claim 11, wherein the set of instructions for supplying the first set of routes to the MTN comprises set of instructions for converting an IC design layout portion that contains the first set of routes from a geometric domain definition to a pixel domain definition, and supplying the pixel-domain definition to the MTN [0036: “Based on the CP-sequence, the genetic algorithm (D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning ”] [0048: ““ Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits,” IEEE Trans. Comput er -Aided Design”][Note: Pixel-domain is reasonably and broadly interpreted as an algorithm residing under digital-domain, wherein, all modern computer computations are performed under digital domain (i.e. binary).] . (As to claim 20, LIN discloses): 20. The non-transitory machine - readable medium of claim 11, wherein the MTN is a neural network [0036: “Based on the CP-sequence, the genetic algorithm (D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning ”. Note: neural network is a well-known algorithm withing the art of machine learning] . Allowable Subject Matter The following claims would be allowable if all rejections/objections cited in this office action (if any) are overcome and rewritten to include all of the limitations of the base claim and any intervening claims. The reason for this allowance is: the claimed subject matter could not have been anticipated or obviated using any prior arts. Allowable claims are: 2-3, 8-10, 12-13, Conclusion The prior art made of record in the form PTO-892 are not relied upon is considered pertinent to applicant's disclosure. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Contact information: Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED ALAM whose telephone number is (571) 270-1507, email address: [mohammed.alam@uspto.gov] and fax number (571) 270-2507. The examiner can normally be reached on 10AM to 4PM (EST), Monday to Friday. If attempts to reach the examiner by telephone are unsuccessful, the Examiner's Supervisor, JACK CHIANG can be reached on (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. /Mohammed Alam/ Primary Examiner, Art Unit 2851
Read full office action

Prosecution Timeline

May 02, 2023
Application Filed
May 08, 2024
Response after Non-Final Action
Mar 27, 2026
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
99%
With Interview (+6.6%)
2y 2m
Median Time to Grant
Low
PTA Risk
Based on 828 resolved cases by this examiner. Grant probability derived from career allow rate.

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