Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action responds to the Application filed on 5/02/2023 and IDS filed on 11/20/2023 and 5/07/2024.
Claims 1-20 are pending.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 2-4 and 12-14 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 and similarly claim 12 recited “using a plurality of predicted
manufactured shapes of a plurality of components that form the particular via to identifying a minimum overlap shape for the particular via; and determining to insert the set of redundant vias based on a size of the minimum overlap shape”, however it is not apparent what the minimum overlap shape for the particular via represent. It is not apparent what is overlap in the overlap shape of the particular via in order to determine the minimum amount.
As per claims 2, 3, 13, and 14 are rejected to for incorporating the above limitations into the claims by dependency.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
6. Claim(s) 1, 5-9, 11, and 15-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (U.S. Pub. No. 2020/0159884 A1).
As per claim 1, Kim discloses:
A method of performing routing to define a plurality of routes for a plurality of nets in an integrated circuit (IC) design layout, the method comprising:
performing a first routing operation to define a first set of one or more routes for a first set of one or more nets in a portion of the IC design layout (See Para [0036], i.e. selection of the target pattern from the target design layout, See Para [0036]-[0041], i.e. database maybe provided…first semiconductor device SD1…second semiconductor device SD2, See Para [0046], i.e. wiring in the target design layout…interconnections, routings, and metal lines in the target design layout, See Para [0045], i.e. first target net 110 and second target vias 112 and 112….first and second crossing nets 210 and 220, See Figure 3B –[prior art operate on layout that include nets with vias, therefore including the routing as cited above])
the first set of routes comprises at least a multi-layer particular route that uses at least one particular via to traverse two different layers of the IC design layout (See Para [0036]-[0041], i.e. database maybe provided…first semiconductor device SD1…second semiconductor device SD2, See Para [0045], i.e. first target net 110 and second target vias 112 and 112….first and second crossing nets 210 and 220, See Figure 3B, i.e. 110 , 112, 114, 210, 220 –[prior art directed to layout having nets and vias is considered as the multi-layer route as cited above] );
supplying the IC design layout to a machine-trained network (MTN) to produce a modified IC design layout portion comprising predicted manufactures shapes for the first set of routes including the particular via (See Para [0039], i.e. information defining a bad pattern based on experimental values obtained under the process conditions, and simulation information regarding the process conditions, See Para [0042]-[0043], i.e. prediction model PM, which predicts a defective pattern of a semiconductor device, may be generated using machine learning based on the feature set FS… target pattern may be selected from the target design layout using the prediction model –[prior art use prediction model to predict bad pattern is considered as the supplying to produce the modified IC design layout as cited above]);
analyzing predicted manufactured shape of the particular via to determine that a set of one or more additional redundant vias need to be inserted in the IC design layout for the particular via (See Figure 1, i.e. 20, i.e. generate redundancy net and redundancy vias in the target pattern, See Para [0045], i.e. analyzing first and second peripheral nets 120 and 130 adjacent to the first target net 110 (Block 1220), and forming (e.g., generating) a redundant net and redundant vias corresponding to the first target net 110 and the target vias 112 and 114, See Para [0046]-[0064], See Figure 7, i.e. 1232b generate redundancy vias which connect redundancy nets and crossing nets & Figure 8, See Figures 9-18 & ;Para [0085]-[0142] –[prior art insert Vias into target layout, such as Figure 8, i.e. 114R & 112R, considered as the additional vias need to be inserted]) and
inserting the set of redundant vias in the IC design layout (See Figure 1, i.e. 20, i.e. generate redundancy net and redundancy vias in the target pattern, See Para [0045], i.e. analyzing first and second peripheral nets 120 and 130 adjacent to the first target net 110 (Block 1220), and forming (e.g., generating) a redundant net and redundant vias corresponding to the first target net 110 and the target vias 112 and 114, See Para [0046]-[0064], See Figure 7, i.e. 1232b generate redundancy vias which connect redundancy nets and crossing nets & Figure 8, See Figures 9-18 & ;Para [0085]-[0142] - [prior art insert Vias into target layout, such as Figure 8, i.e. 114R & 112R]).
As per claim 5, Kim discloses all of the features of claim 1 as discloses above wherein Kim also discloses wherein the MTN is a first MTN, and analyzing predicted manufactured shape comprising supplying the modified IC design layout portion to a second MTN to identify any set of redundant vias that need to be inserted in the IC design layout (See Figure 1, i.e. 20, i.e. generate redundancy net and redundancy vias in the target pattern, See Para [0045], i.e. analyzing first and second peripheral nets 120 and 130 adjacent to the first target net 110 (Block 1220), and forming (e.g., generating) a redundant net and redundant vias corresponding to the first target net 110 and the target vias 112 and 114, See Para [0046]-[0064], See Figure 7, i.e. 1232b generate redundancy vias which connect redundancy nets and crossing nets & Figure 8, See Figures 9-18 & ;Para [0085]-[0142]).
As per claim 6, Kim discloses all of the features of claim 5 as discloses above wherein Kim also discloses wherein said inserting comprises using the second MTN to insert any set of redundant vias identified by the second MTN (See Figure 1, i.e. 20, i.e. generate redundancy net and redundancy vias in the target pattern, See Para [0045], i.e. analyzing first and second peripheral nets 120 and 130 adjacent to the first target net 110 (Block 1220), and forming (e.g., generating) a redundant net and redundant vias corresponding to the first target net 110 and the target vias 112 and 114, See Para [0046]-[0064], See Figure 7, i.e. 1232b generate redundancy vias which connect redundancy nets and crossing nets & Figure 8, See Figures 9-18 & ;Para [0085]-[0142]).
As per claim 7, Kim discloses all of the features of claim 5 as discloses above wherein Kim also discloses wherein said inserting comprises using a via-insertion process to select any specific redundant via in the identified set of redundant vias and to insert in the IC design layout any selected redundant via (See Figure 1, i.e. 20, i.e. generate redundancy net and redundancy vias in the target pattern, See Para [0045], i.e. analyzing first and second peripheral nets 120 and 130 adjacent to the first target net 110 (Block 1220), and forming (e.g., generating) a redundant net and redundant vias corresponding to the first target net 110 and the target vias 112 and 114, See Para [0046]-[0064], See Figure 7, i.e. 1232b generate redundancy vias which connect redundancy nets and crossing nets & Figure 8, See Figures 9-18 & ;Para [0085]-[0142]).
As per claim 8, Kim discloses all of the features of claim 1 as discloses above wherein Kim also discloses wherein the particular via is a first via, the method further comprising analyzing predicted manufactured shape of a second via to determine that the second via has to be moved to another location on a route in the IC design layout (See Figure 1, i.e. 20, i.e. generate redundancy net and redundancy vias in the target pattern, See Para [0045], i.e. analyzing first and second peripheral nets 120 and 130 adjacent to the first target net 110 (Block 1220), and forming (e.g., generating) a redundant net and redundant vias corresponding to the first target net 110 and the target vias 112 and 114, See Para [0046]-[0064], See Figure 7, i.e. 1232b generate redundancy vias which connect redundancy nets and crossing nets & Figure 8, See Figures 9-18 & ;Para [0085]-[0142] –[prior art in Figure 5, the via 112R and 114R is modified / moved to be closer to net 130]).
As per claim 9, Kim discloses all of the features of claim 8 as discloses above wherein Kim also discloses wherein the second via is moved to another location by discarding the second via and inserting a third via at the other location on the route in the IC design layout (See Figure 1, i.e. 20, i.e. generate redundancy net and redundancy vias in the target pattern, See Para [0045], i.e. analyzing first and second peripheral nets 120 and 130 adjacent to the first target net 110 (Block 1220), and forming (e.g., generating) a redundant net and redundant vias corresponding to the first target net 110 and the target vias 112 and 114, See Para [0046]-[0064], See Figure 7, i.e. 1232b generate redundancy vias which connect redundancy nets and crossing nets & Figure 8, See Figures 9-18 & ;Para [0085]-[0142] –[prior art in Figure 5, the via 112R and 114R is modified / moved to be closer to net 130, 112R and 114R replace via 114 and 112 from original layout]).
As per claim 11, Kim discloses:
A non-transitory machine readable medium storing a program which when executed by at least one processing unit performs routing to define a plurality of routes for a plurality of nets in an integrated circuit (IC) design layout, the program comprising sets of instructions (See Figure 19, i.e. processor and storage 2000) for:
performing a first routing operation to define a first set of one or more routes for a first set of one or more nets in a portion of the IC design layout (See Para [0036], i.e. selection of the target pattern from the target design layout, See Para [0036]-[0041], i.e. database maybe provided…first semiconductor device SD1…second semiconductor device SD2, See Para [0046], i.e. wiring in the target design layout…interconnections, routings, and metal lines in the target design layout, See Para [0045], i.e. first target net 110 and second target vias 112 and 112….first and second crossing nets 210 and 220, See Figure 3B –[prior art operate on layout that include nets with vias, therefore including the routing as cited above]),
the first set of routes comprises at least a multi-layer particular route that uses at least one particular via to traverse two different layers of the IC design layout (See Para [0036]-[0041], i.e. database maybe provided…first semiconductor device SD1…second semiconductor device SD2, See Para [0045], i.e. first target net 110 and second target vias 112 and 112….first and second crossing nets 210 and 220, See Figure 3B, i.e. 110 , 112, 114, 210, 220 –[prior art directed to layout having nets and vias is considered as the multi-layer route as cited above] );
supplying the IC design layout to a machine-trained network (MTN) to produce a modified IC design layout portion comprising predicted manufactures shapes for the first set of routes including the particular via (See Para [0039], i.e. information defining a bad pattern based on experimental values obtained under the process conditions, and simulation information regarding the process conditions, See Para [0042]-[0043], i.e. prediction model PM, which predicts a defective pattern of a semiconductor device, may be generated using machine learning based on the feature set FS… target pattern may be selected from the target design layout using the prediction model –[prior art use prediction model to predict bad pattern is considered as the supplying to produce the modified IC design layout as cited above]);
analyzing predicted manufactured shape of the particular via to determine that a set of one or more additional redundant vias need to be inserted in the IC design layout for the particular via (See Figure 1, i.e. 20, i.e. generate redundancy net and redundancy vias in the target pattern, See Para [0045], i.e. analyzing first and second peripheral nets 120 and 130 adjacent to the first target net 110 (Block 1220), and forming (e.g., generating) a redundant net and redundant vias corresponding to the first target net 110 and the target vias 112 and 114, See Para [0046]-[0064], See Figure 7, i.e. 1232b generate redundancy vias which connect redundancy nets and crossing nets & Figure 8, See Figures 9-18 & ;Para [0085]-[0142] –[prior art insert Vias into target layout, such as Figure 8, i.e. 114R & 112R, considered as the additional vias need to be inserted]); and
inserting the set of redundant vias in the IC design layout (See Figure 1, i.e. 20, i.e. generate redundancy net and redundancy vias in the target pattern, See Para [0045], i.e. analyzing first and second peripheral nets 120 and 130 adjacent to the first target net 110 (Block 1220), and forming (e.g., generating) a redundant net and redundant vias corresponding to the first target net 110 and the target vias 112 and 114, See Para [0046]-[0064], See Figure 7, i.e. 1232b generate redundancy vias which connect redundancy nets and crossing nets & Figure 8, See Figures 9-18 & ;Para [0085]-[0142] - [prior art insert Vias into target layout, such as Figure 8, i.e. 114R & 112R]).
As per claim 15, Kim discloses all of the features of claim 11 as discloses above wherein Kim also discloses wherein the MTN is a first MTN, and the set of instructions for analyzing predicted manufactured shape comprises a set of instructions for supplying the modified IC design layout portion to a second MTN to identify any set of redundant vias that need to be inserted in the IC design layout (See Figure 1, i.e. 20, i.e. generate redundancy net and redundancy vias in the target pattern, See Para [0045], i.e. analyzing first and second peripheral nets 120 and 130 adjacent to the first target net 110 (Block 1220), and forming (e.g., generating) a redundant net and redundant vias corresponding to the first target net 110 and the target vias 112 and 114, See Para [0046]-[0064], See Figure 7, i.e. 1232b generate redundancy vias which connect redundancy nets and crossing nets & Figure 8, See Figures 9-18 & ;Para [0085]-[0142]).
As per claim 16, Kim discloses all of the features of claim 15 as discloses above wherein Kim also discloses wherein the set of instructions for said inserting comprises a set of instructions for using the second MTN to insert any set of redundant vias identified by the second MTN (See Figure 1, i.e. 20, i.e. generate redundancy net and redundancy vias in the target pattern, See Para [0045], i.e. analyzing first and second peripheral nets 120 and 130 adjacent to the first target net 110 (Block 1220), and forming (e.g., generating) a redundant net and redundant vias corresponding to the first target net 110 and the target vias 112 and 114, See Para [0046]-[0064], See Figure 7, i.e. 1232b generate redundancy vias which connect redundancy nets and crossing nets & Figure 8, See Figures 9-18 & ;Para [0085]-[0142]).
As per claim 17, Kim discloses all of the features of claim 15 as discloses above wherein Kim also discloses wherein the set of instructions for said inserting comprises a set of instructions for using a via-insertion process to select any specific redundant via in the identified set of redundant vias and to insert in the IC design layout any selected redundant via (See Figure 1, i.e. 20, i.e. generate redundancy net and redundancy vias in the target pattern, See Para [0045], i.e. analyzing first and second peripheral nets 120 and 130 adjacent to the first target net 110 (Block 1220), and forming (e.g., generating) a redundant net and redundant vias corresponding to the first target net 110 and the target vias 112 and 114, See Para [0046]-[0064], See Figure 7, i.e. 1232b generate redundancy vias which connect redundancy nets and crossing nets & Figure 8, See Figures 9-18 & ;Para [0085]-[0142]).
As per claim 18, Kim discloses all of the features of claim 11 as discloses above wherein Kim also discloses wherein the particular via is a first via, the program further comprises a set of instructions for analyzing predicted manufactured shape of a second via to determine that the second via has to be moved to another location on a route in the IC design layout (See Figure 1, i.e. 20, i.e. generate redundancy net and redundancy vias in the target pattern, See Para [0045], i.e. analyzing first and second peripheral nets 120 and 130 adjacent to the first target net 110 (Block 1220), and forming (e.g., generating) a redundant net and redundant vias corresponding to the first target net 110 and the target vias 112 and 114, See Para [0046]-[0064], See Figure 7, i.e. 1232b generate redundancy vias which connect redundancy nets and crossing nets & Figure 8, See Figures 9-18 & ;Para [0085]-[0142] –[prior art in Figure 5, the via 112R and 114R is modified / moved to be closer to net 130]).
As per claim 19, Kim discloses all of the features of claim 18 as discloses above wherein Kim also discloses wherein the second via is moved to another location by discarding the second via and inserting a third via at the other location on the route in the IC design layout (See Figure 1, i.e. 20, i.e. generate redundancy net and redundancy vias in the target pattern, See Para [0045], i.e. analyzing first and second peripheral nets 120 and 130 adjacent to the first target net 110 (Block 1220), and forming (e.g., generating) a redundant net and redundant vias corresponding to the first target net 110 and the target vias 112 and 114, See Para [0046]-[0064], See Figure 7, i.e. 1232b generate redundancy vias which connect redundancy nets and crossing nets & Figure 8, See Figures 9-18 & ;Para [0085]-[0142] –[prior art in Figure 5, the via 112R and 114R is modified / moved to be closer to net 130, 112R and 114R replace via 114 and 112 from original layout]).
Allowable Subject Matter
7. Claims 2-4 and 12-14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
8. Claims 10 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
9. The following is a statement of reasons for the indication of allowable subject matter: With respect to claims 2-4 and 12-14, the prior art does not teach the limitations of claims 2 and 12, wherein claims 3 and 4 depend on claim 2 – wherein claims 13 and 14 depend on claim 12.
With respect to claims 10 and 20, the prior art does not teach the limitations of
claims 10 and 20.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM.
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/NHA T NGUYEN/Primary Examiner, Art Unit 2851