Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
For reissue applications filed on or after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions.
NONFINAL OFFICE ACTION
This Office Action addresses U.S. Patent Application No. 18/142,665, which is filed as a reissue of U.S. Patent Application No. 15/218,336 (hereinafter, the '336 application), entitled, “INTEGRATED MEMORY DEVICE AND METHOD OF OPERATING SAME”, which issued as U.S. Patent No. 10,998,030 (hereinafter, the '030 patent).
Claims 1-7, 10-14 and 16-40 are pending.
Claims 1-7, 10-14 and 16-28 were issued in the '030 patent.
Claims 29-40 are newly presented with this reissue application.
PRIOR OR CONCURRENT PROCEEDINGS
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which the patent is or was involved. These proceedings would include interferences, reissues, reexaminations, and litigation. Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application.
These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
In accordance with MPEP § 1406, the examiner has reviewed and considered the prior art made of record during the prosecution of the original patent. Such prior art need not be resubmitted in this reissue application unless applicant desires the information to be printed on a patent issuing from this reissue application.
APPLICATION DATA SHEET
The Application Data Sheet (ADS) filed January 21, 2026 is objected to because on page 5, in the Applicant Information section, no applicant has been listed to replace the crossed out data.
CONSENT
The requirement for the written Consent of all assignees owning an undivided interest in the patent has been satisfied. Note MPEP 1410.02(I):
“The consent of assignee must be signed by a party authorized to act on behalf of the assignee. For applications filed on or after September 16, 2012, the consent may be signed by the assignee or a patent practitioner of record.”
Although not identified by registration number on the Consent, the attorney of record signing the Consent has been identified by registration number as a patent practitioner of record on the accompanying Application Data Sheet.
STATEMENT UNDER 37 CFR 3.73(c)
The statements under 37 CFR 3.73(c) (both copies) filed January 21, 2026 are objected to as they show Box B (page 1) unchecked, but the entries (reel number and frame number) are filled in. Box B must be checked on both copies.
Correction is required.
DRAWING OBJECTIONS
The drawings filed May 3, 2023 are objected to because:
(1) Figures 1 and 3-11 are not in accordance with 37 CFR 1.84(l), which states, “Every line, number, and letter must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined.”
In the drawings, all of the lines are sufficiently dense and dark, but none of the text (numbers and letters) is sufficiently dense and dark. For example:
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(2) Figures 1-4 and 7-11 are not in accordance with 37 CFR 1.84(u)(2), which states, “The view numbers must be larger than the numbers used for reference characters.”
(3) Figures 3 and 5 are not in accordance with 37 CFR 1.84(p)(3), which states, “Numbers, letters, and reference characters must measure at least .32 cm. (1/8 inch) in height.”
(4) Figures 5, 6, 8, 9 and 11 are not underlined in accordance with 37 CFR 1.84(p)(3), which states, “Numbers, letters, and reference characters … should not be placed upon hatched or shaded surfaces. When necessary, such as indicating a surface or cross section, a reference character may be underlined and a blank space may be left in the hatching or shading where the character occurs so that it appears distinct.”
(5) Figures 8, 9 and 11 not in accordance with 37 CFR 1.84(p)(3), which states, “Numbers, letters, and reference characters … should not be placed in the drawing so as to interfere with its comprehension. Therefore, they should not cross or mingle with the lines.” For example:
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56
44
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(6) Figures 8, 9 and 11 are not in accordance with 37 CFR 1.84(m), which states, “Solid black shading areas are not permitted, except when used to represent bar graphs or color.”
(7) Figure 2 should be designated by a legend such as --Prior Art— because, according to the discussion of Figure 2 in the Background section of the specification, only that which is old is illustrated. See MPEP § 608.02(g).
Corrected drawing sheets are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended.
Each amended drawing should be labeled “Amended”, for example:
FIG. 1
(Amended)
Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d).
If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Note 37 CFR 1.173 for reissue drawing amendments. Note also MPEP 1413.
SPECIFICATION
The disclosure is objected to because of the following informalities:
(1) The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The claims are directed to sensing the logic state of a memory by providing a charge on a bit line, etc.
(2) The brief description of the drawings should list Figure 2 as prior art because, according to the discussion of Figure 2 in the Background section of the specification, only that which is old is illustrated.
(3) The specification includes minor errors that should be corrected, for example:
(a) In column 5, line 33, “capacitor’s” should replace “capacitors”.
(b) In column 6, lines 6-7, a comma should appear after “Therefore”.
(c) In column 10, line 49, a comma should appear after “line”.
Appropriate correction is required.
RESTRICTION
Restriction to one of the following inventions is required under 35 U.S.C. 121:
I. Claims 1-7, 10-14 and 16-28, drawn to methods of reading the logic state of an
integrated circuit memory device, classified in G11C 11/2275.
II. Claims 29-40, drawn to the circuit layout of an integrated circuit memory device, classified in G11C 11/22.
Newly submitted claims 29-40 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
(1) Reissue may not be utilized to reclaim subject matter which was nonelected in the original application. The same or similar subject matter which was canceled in response to a restriction requirement during prosecution of the original patent – note the restriction requirement of April 6, 2017 in the '336 application. In re Orita, 193 USPQ 145, 148 (CCPA 1977), In re Watkinson, 14 USPQ2d 1407 (Fed. Cir. 1990).
(2) Inventions I and II are related as subcombinations disclosed as usable together in a single combination. The subcombinations are distinct if they do not overlap in scope and are not obvious variants, and if it is shown that at least one subcombination is separately usable. In the instant case, subcombination I has separate utility such as implementation without the specific circuit design required of subcombination I. See MPEP § 806.05(d).
Where claims to the elected subcombination are subsequently found allowable, any claim(s) depending from or otherwise requiring all the limitations of the allowable subcombination will be examined for patentability in accordance with 37 CFR 1.104. See MPEP § 821.04(a). Applicant is advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application.
For the reasons above, claims 1-7, 10-14 and 16-28 have been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 29-40 are withdrawn from consideration as being directed to a non-elected invention.
See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
CLAIM SUPPORT
Regarding the explanation of support in the disclosure of the patent for the changes made to the claims.
(1) The explanation of support must be on page(s) separate from the page(s) containing the amendment.
Pages 3-12 of the amendment list the claims followed by the explanation of support. The explanation of support should be separated and included as part of applicant’s remarks.
(2) The explanation of support includes the following language:
“Support for Amendments to claims 1-7, 10-14, and 16-28 can be found in original filed claims, issued claims and related text of the specification.”
This explanation does not show where each new limitation of each new claim may be found in the disclosure.
An explanation of support for each of limitations of the amended claims is required in response to this Office action.
Note MPEP 1411.02. Note also MPEP 1453(V)(D), which shows examples of proper support, wherein a separate citation is provided for each new limitation of each claim.
OBJECTIONS BASED ON DEFECTIVE OATH/DECLARATION
The declaration filed January 21, 2026 is missing an error statement. The declaration does appear to identify a claim:
“At least claim one and other claims as set forth in the preliminary amendment filed herewith.”
But does not clarify whether the error is meant to be broadening or narrowing, which is necessary since the preliminary amendment has both broadening and narrowing of limitations.
The reissue oath/declaration filed with this application is objected to as defective (see 37 CFR 1.175 and MPEP § 1414) because of the following:
(1) The reissue oath/declaration filed with this application is defective because it fails to identify at least one error which is relied upon to support the reissue application. See 37 CFR 1.175 and MPEP § 1414.
The declaration does not specifically identify an error as required by 37 CFR 1.175(a), i.e., “it is sufficient that the reissue oath/declaration identify the claim being broadened and a single word, phrase, or expression in the specification or in an original claim, and how it renders the original patent wholly or partly inoperative or invalid.” Note the sample error statement below:
“Applicant believes the original patent, U.S. Patent No. 10,998,030, to be wholly or partly inoperative by reason of claiming less than the applicant had a right to claim. Specifically, claim 1 of the patent includes the limitation “XYZ”, …” which applicant believes is not necessary for patentability. This error occurred without any deceptive intent. The applicant therefore seeks reissue of the patent to correct this error by amending claim 1 to remove the limitation “XYZ”.
(2) The declaration fails to specify a broadened claim. Note 37 CFR 1.175(b) and MPEP 1414.01: “If the reissue application seeks to enlarge the scope of the claims of the patent (a basis for the reissue is the patentee claiming less than the patentee had the right to claim in the patent), the inventor’s oath or declaration for a reissue application must identify a claim that the application seeks to broaden.”
REJECTIONS BASED ON DEFECTIVE OATH/DECLARATION
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. §251 that form the basis for the rejections under this section made in this Office action:
(a) IN GENERAL.—Whenever any patent is, through error, deemed wholly or partly inoperative or invalid, by reason of a defective specification or drawing, or by reason of the patentee claiming more or less than he had a right to claim in the patent, the Director shall, on the surrender of such patent and the payment of the fee required by law, reissue the patent for the invention disclosed in the original patent, and in accordance with a new and amended application, for the unexpired part of the term of the original patent. No new matter shall be introduced into the application for reissue.
Defective Reissue Declaration
Claims 1-7, 10-14 and 16-28 are rejected as being based upon a defective reissue declaration under 35 U.S.C. §251. The declaration is defective for all of the reasons set forth above with regard to the objections to the declaration. See 37 CFR 1.175.
Impermissible Recapture
Claims 1-7, 10-14 and 16-28 lack subject matter surrendered during the prosecution of the '336 application.
Claim 1 lacks the language of claim 60 (issued as claim 1 in the '030 patent) which was added and/or argued to overcome rejections based on the prior art during the prosecution of the '336 application. The surrendered subject matter of claim 1 as issued is shown below in bold:
1. A method of reading the logic state of an integrated circuit memory, including the steps of,
providing a first bit line,
connecting an amplifier having an offset voltage to said first bit line, and
providing a current [charge] from said amplifier to said first bit line that is a function of the offset voltage of said amplifier during the offset voltage nulling portion of a read cycle where the offset voltage nulling portion of the read cycle requires no switching of the bit lines to the amplifier.
Emphasis is added to the remarks below to show where surrendered subject matter was added and/or argued during prosecution:
In the remarks submitted with the amendment of March 6, 2018, page 12, applicant argued, “Neither the cited Figures of Seyyedy nor the cited portion of Seyyedy's specification teach the method of reading the logic state of an integrated circuit memory that is defined in claim 1 or new claims 44 and 57” and “The cited portions of Seyedy do not disclose the first limitation of claim 1, applying a first voltage to a first bit line. However, col. 9, lines 24-25 state "bit lines 150 and 152 are pulled low." This is a specific case of applying a first voltage to a first bit line.”
In the remarks submitted with the amendment of October 1, 2018, page 11, applicant explained the relationship between claim 60 and the original claim 1, arguing, “Notwithstanding Applicants' argument that withdrawal of claims 44-56, 4-9 & 17- 19 was improper and in error, Applicants have cancelled claims 44-47 and replaced them by new claims 60-64. New claim 60 distinguishes the current invention over prior art previously cited by the Examiner. The wording of new claims 61-64 is similar to that of original claims 1-3.”
In the amendment of April 4, 2019, the language “having an offset voltage” was added to claim 60.
In the remarks submitted with the amendment of April 4, 2019, page 10, applicant argued, “The error in the rejection is that Seyyedy does not disclose applying to said first bit line an additional charge that is a function of the offset voltage of said amplifier” and page 11, “Therefore, Seyyedy does not supply the teaching of each and every one of the steps of claim 60 necessary to qualify Seyyedy as an anticipating reference.”
In the amendment of December 20, 2019, the language “during a read cycle” was added to claim 60.
In the remarks submitted with the amendment of December 20, 2019, applicant argued “similarly the limitation of claim 60 specifies that the amplifier is a current mirror voltage amplifier to distinguish the current invention from Seo. The current mirror voltage amplifier allows the bit lines to be continuously connected to the amplifier during the read cycle without the bit lines floating during the sensing portion of the read cycle and does not require any switching of the bit lines to the amplifier. This is a significant improvement over Seo and would not be obvious to one skilled in the art.”
Further, in the above-cited amendments and remarks, several similar instances of surrender exist for dependent claims 2-7, 10-14 and 16-22.
Claim 23 lacks the language of claim 57 (issued as claim 23 in the '030 patent) which was added and/or argued to overcome rejections based on the prior art during the prosecution of the '336 application. The surrendered subject matter of claim 23 as issued is shown below in bold:
23. A method of reading the logic state of a ferroelectric integrated circuit memory that includes a sensing portion of a read cycle, comprising the steps of,
applying a voltage to a first bit line,
connecting a first charge source to said first bit line,
connecting to said first bit line a sense amplifier,
connecting to said first bit line a first memory cell comprising a ferroelectric capacitor having a coercive voltage,
applying a charge from said first charge source to said first bit line during the sensing portion of the read cycle prior to latching or powering the sense amplifier to provide a voltage on said first bit line of at least the coercive voltage of the ferroelectric capacitor in said first memory cell, and
sensing the logic state of said first memory cell.
In the remarks submitted with the amendment of March 6, 2018, page 12, applicant argued, “Neither the cited Figures of Seyyedy nor the cited portion of Seyyedy's specification teach the method of reading the logic state of an integrated circuit memory that is defined in claim 1 or new claims 44 and 57” and “The cited portions of Seyedy do not disclose the first limitation of claim 1, applying a first voltage to a first bit line. However, col. 9, lines 24-25 state "bit lines 150 and 152 are pulled low." This is a specific case of applying a first voltage to a first bit line” and “The foregoing arguments apply equally to new independent claims 44 and 57. Except for the specific case of precharging the bit lines, Seyyedy does not teach or disclose any of the other limitations of claim 44. With respect to claim 57 Seyyedy specifically does not teach connecting a first charge source to a first bit line.”
In the remarks submitted with the amendment of April 4, 2019, pages 11-12, applicant argues, “For reading the memory cell, Seyyedy's circuity does not apply a charge from said first charge source to said first bit line to provide a voltage on said first bit line of at least the coercive voltage of the ferroelectric capacitor in said first memory cell. … the aforesaid step of claim 57 applies the voltage to the bit line as a result of a first charge source being connected to the bit line. The voltage is applied to the opposite terminal of the ferroelectric capacitor that is not connected to the plate line in order to switch the polarization of the ferroelectric capacitor for the read operation (See applicant's paragraph [0079] and Fig. 7). This step of claim 57 applies an additional charge to the bit line of at least the coercive voltage of the ferroelectric capacitor in order to switch the ferroelectric capacitor. This step is not disclosed in Seyyedy. Note also that claim 57 specifies two voltages of at least the coercive voltage applied to the ferroelectric capacitor during the read/rewrite cycle, one to read the state of the memory cell and the second to rewrite the data into the memory cell after the destructive read. In claim 57, the second application of voltage for the rewrite occurs inherently during the step of sensing the logic state of said first memory cell, as is known to one skilled in the art. The second sentence of paragraph [0047] states “… of a latching sense amplifier that is powered at the end of the sensing portion of the read cycle …” and paragraph [0058] states "… allows the latching sense amplifiers to apply the proper voltages to the bit lines for the rewrite cycle at the end of the read cycle." Both voltages are applied to the bit line. … Seyyedy does not disclose each and every step of claim 57”.
In the amendment of December 20, 2019 the language, “that includes a sensing portion of a read cycle” and connecting “to said first bit line” a first memory cell “comprising a ferroelectric capacitor having a coercive voltage” and “during the sensing portion of the read cycle” was added to claim 57.
In the remarks submitted with the amendment of December 20, 2019, page 12, applicant argues, “Regarding claim 57, the phrase "during the sensing portion of the read cycle" has been added to claim 57 to make it patentably distinct from Seyyedy in that the claimed bit lines are not floating during the sensing portion of the read cycle (paragraphs [0055] and [0056]) as they are in Seyyedy. The bit lines do not float during the sensing portion of the read cycle as a result of a voltage being applied to the bit line by a charge source connected to the bit line … The limitations of claim 57 clearly patentably define over Seyyedy.”
In the amendment of February 19, 2021 the language, “connecting to said first bit line a sense amplifier” and “prior to latching or powering the sense amplifier” was added to claim 57.
In the remarks submitted with the amendment of February 19, 2021, applicant argues, “Claims 57 and 58 have been amended to make it clear that the charge applied to the bit lines is not the voltage (or charge) applied by the sense amplifier when the sense amplifier is powered, the data are latched in the sense amplifier and the write-back voltage is applied to the bit lines. Specifically, claims 57 and 58 include both a charge source and a memory cell attached to the bit lines (two sources of charge for the bit lines) during the sensing portion of the read cycle prior to powering or latching of the sense amplifier. Seyyedy does not disclose applying a charge to the bit line from a charge source separate from the memory cell during the sensing portion of the read cycle prior to powering or latching of Seyyedy's sense amplifier because Seyyedy's bit lines are floating … Because Seyyedy does not disclose each and every step of the amended claims 57 and 58, the previously alleged anticipation of the claims no longer exists.”
Further, in the above-cited amendments and remarks, similar instances of surrender exist for dependent claim 24 (claim 58 during prosecution). Note the remarks submitted with the amendment of December 20, 2019, “Regarding claim 58, the limitation of claim 58 specifies that the charge from the charge source is applied to the second bit line during the sensing portion of the read cycle. This is not taught by Seyyedy who applies a voltage to the plate line rather than the bit line during the sensing portion of the read cycle.”
Claim 25 lacks the language of claim 65 (issued as claim 25 in the '030 patent) which was added and/or argued to overcome rejections based on the prior art during the prosecution of the '336 application. The surrendered subject matter of claim 25 as issued is shown below in bold:
25. A method of reading the logic state of an integrated circuit memory that uses a destructive read cycle having a sensing portion of a read cycle, including the steps of,
providing a bit line,
providing a memory cell having a circuit element
providing an electrical charge to said bit line,
connecting an amplifier to said bit line, and
providing a current from said amplifier to said bit line without the bit lines floating during the sensing portion of a read cycle prior to the rewrite portion of the read cycle.
In the remarks submitted with the amendment of December 20, 2019, pages 14-15, applicant argues, “Regarding new claim 65, an important distinction of the current invention over the prior art is that the bit lines do not float during the sensing portion of the read cycle. This is not taught by either Seyyedy or Seo. While Seo does teach applying a voltage to the bit lines that is a function of the offset voltage of the sense amplifier (between t1 and t2 in Seo Fig. 14), this is added as a part of what is otherwise a conventional read cycle with floating bit lines during the sensing portion of the read cycle (between t2 and t3 in Seo Fig. 14 where LA and LAB, the power to the amplifier, are both at Vpre so the amplifier is not powered allowing the bit lines to float) … the method of claim 65, applying a voltage to the bit lines that is a function of the offset voltage is accomplished within the current mirror voltage amplifier without any need to switch the bit lines or float them. This distinction is made clear in new claim 65. Not floating the bit lines by having power applied to an amplifier connected to the bit lines during the sensing portion of the read cycle for a memory using a destructive read cycle is a new innovation that is significantly different from the prior art.”
The three step test for recapture:
Step 1 - Is There Broadening?
Are the reissue claims broader than the original patent claims in at least some respects? Yes, claims 1-7, 10-14 and 16-28 lack the above-cited language which is required of the claims of the '030 patent.
Step 2 - Does Any Broadening Aspect of the Reissued Claim Relate to Surrendered Subject Matter?
Substep 1 – Did applicant surrender any subject matter in the prosecution of the original application that became the patent to be reissued? Yes, the surrendered subject matter is noted above.
Substep 2 - Does the broadening in the reissue claims result from eliminating limitations surrendered in the original prosecution? Yes, at least independent claims 1, 23, and 25 omit limitations that the prosecution record shows as added and/or argued to overcome rejections based on prior art during the original prosecution.
Step 3 - Are the Reissue Claims Materially Narrowed in Other Respects, and Hence Avoid the Recapture Rule?
The reissue claims are not materially narrowed in other respects.
Thus, claims 1-7, 10-14 and 16-28 are rejected under 35 U.S.C. 251 as being an impermissible recapture of broadened claimed subject matter surrendered in the application for the patent upon which the present reissue is based. In re McDonald, 43 F.4th 1340, 1345, 2022 USPQ2d 745 (Fed. Cir. 2022); Greenliant Systems, Inc. et al v. Xicor LLC, 692 F.3d 1261, 103 USPQ2d 1951 (Fed. Cir. 2022); In re Youman, 679 F.3d 1335, 102 USPQ2d 1862 (Fed. Cir. 2012); In re Shahram Mostafazadeh and Joseph O. Smith, 643 F.3d 1353, 98 USPQ2d 1639 (Fed. Cir. 2011); North American Container, Inc. v. Plastipak Packaging, Inc., 415 F.3d 1335, 75 USPQ2d 1545 (Fed. Cir. 2005); Pannu v. Storz Instruments Inc., 258 F.3d 1366, 59 USPQ2d 1597 (Fed. Cir. 2001); Hester Industries, Inc. v. Stein, Inc., 142 F.3d 1472, 46 USPQ2d 1641 (Fed. Cir. 1998); In re Clement, 131 F.3d 1464, 45 USPQ2d 1161 (Fed. Cir. 1997); Ball Corp. v. United States, 729 F.2d 1429, 1436, 221 USPQ 289, 295 (Fed. Cir. 1984). The reissue application contains claim(s) that are broader than the issued patent claims. The record of the application for the patent family shows that the broadening aspect (in the reissue) relates to claimed subject matter that applicant previously surrendered during the prosecution of the application. Accordingly, the narrow scope of the claims in the patent was not an error within the meaning of 35 U.S.C. 251, and the broader scope of claim subject matter surrendered in the application for the patent cannot be recaptured by the filing of the present reissue application.
Original Patent Requirement
Claims 1-7, 10-14 and 16-22 and 25-28 are rejected as failing to satisfy the original patent requirement of 35 USC § 251.
The reissue claims must be for the same invention as that disclosed as being the invention in the original patent, as required by 35 U.S.C. 251. The entire disclosure, not just the claim(s), is considered in determining what the patentee objectively intended as the invention. The determination of the original patent requirement is “an essentially factual inquiry confined to the objective intent manifested by the original patent.” In re Amos, 953 F.2d 613, 618, 21 USPQ2d 1271, 1274 (Fed. Cir. 1991) (quoting In re Rowand, 526 F.2d 558, 560, 187 USPQ 487, 489 (CCPA 1975)) (emphasis added); See also In re Mead, 581 F.2d 251, 256, 198 USPQ 412, 417 (CCPA 1978).
The May 3, 2023 amendment to claim 1 removed “providing a first bit line, connecting an amplifier having an offset voltage to said first bit line” and providing a current from an amplifier “to said first bitline”.
The May 3, 2023 amendment to claim 25 removed “providing a bit line, providing a memory cell having a circuit element providing an electrical charge to said bit line, connecting an amplifier to said bit line”.
However, these amendments fail to satisfy the original patent requirement because the disclosure of the '030 patent does not support operation without an amplifier applying a charge to the bit line.
This is demonstrated by column 6, lines 12-17, which states, “it is an object of this invention to provide a new read method that increases the read signal margin by adding an additional step to the read cycle where additional charge is applied to the bit lines between the two steps of precharging the bit lines and transferring charge between the bit lines and the memory cells.”
The necessity of this limitation is further demonstrated in column 9, lines 12-15, “In summary, the preamplifier uses non-floating bit lines connected to it to provide relatively small charges on the bit lines that null out the offset in the preamplifier circuit prior to sensing the data state of a memory cell.”
Consequently, amended claims 1-7, 10-14 and 16-22 and 25-28, which lack the prior limitations directed to applying a charge to the bit lines, do not meet the original patent requirement of § 251.
Nonelected Subject Matter
Claims 1-7, 10-14 and 16-22 and 25-28 are rejected under 35 USC § 251 as long as withdrawn claims 29-40 are pending in this application, since claims 29-40 include the same or similar subject matter which was canceled in response to a restriction requirement during prosecution of the original patent – note the restriction requirement of April 6, 2017 in the '336 application. In re Orita, 193 USPQ 145, 148 (CCPA 1977), In re Watkinson, 14 USPQ2d 1407 (Fed. Cir. 1990).
Reissue may not be utilized to reclaim subject matter which was nonelected in the original application.
CLAIM INTERPRETATION
The claim limitations in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The claims do not invoke 35 U.S.C. § 112, 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph.
CLAIM REJECTIONS - 35 USC § 112, 1st PARAGRAPH
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-7, 10-14 and 16-22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
With regard to claims 1 and 3, the limitation “bit value” or “bit values” does not appear in the specification. There are five occurrences of the word “value” in the specification, none of which describe a particular bit. It is not clear from the disclosure what such a value is meant to represent.
Claims 2, 4-7, 10-14 and 16-22 are rejected as being dependent on rejected claim 1.
PRIOR ART
For at least the reasons explained above, claims 1-7, 10-14 and 16-28, as presently amended are ineligible for reissue under 35 USC § 251. Any search and consideration of the claimed subject matter in view of prior art would not be forehanded at this time.
CONCLUSION
Any inquiry concerning this communication or earlier communications from the examiner should be directed to B. James Peikari at telephone number 571-272-4185. The examiner can normally be reached on Mon-Fri from 8:30am to 5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Kosowski, SPE Art Unit 3992, can be reached at 571-272-3744.
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Any inquiry concerning this communication or earlier communications from the examiner, or as to the status of this proceeding, should be directed to the Central Reexamination Unit at telephone number (571) 272-7705.
/B. James Peikari/
Primary Examiner, Art Unit 3992
Conferees:
/RACHNA S DESAI/Primary Examiner, Art Unit 3992
/ALEXANDER J KOSOWSKI/Supervisory Patent Examiner, Art Unit 3992
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