DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Objections
Claim 1 is objected to because of the following informalities: the word “mode” appears to have been used in place of the word “node” in Line 8. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Application Publication Number 2014/0247355 to Ihlenburg (“Ihlenburg”) with evidence of inherency provided by “MIPI Alliance Specification for D-PHY” Version 1.00.00 (“MIPI D-PHY Specification”).
In reference to Claim 16, Ihlenburg discloses an image sensor comprising: a pixel array configured to generate electric charges in response to light (See Figure 2A ‘Imager’ and Paragraphs 24-27 [CMOS and CCD image sensors are a type of pixel array that generates electric charges in response to light]); a logic circuit configured to convert the electric charges into first image data (See Figure 2A ‘Logic’ and Paragraphs 20 and 24-27 [image processing circuitry]); and an interface circuit including a transmitter configured to transmit the first image data to an external processor (See Figure 2A ‘D-PHY’ and Paragraphs 19-21) via a first transfer pad connected to a first transmission line and a second transfer pad connected to a second transmission line (See Figure 2A STP/UTP Cable’ and Paragraphs 19-20 [differential MIPI D-PHY communication necessarily requires first and second transmission lines; the cable necessarily requires contact pads to connect the lines of the cable with the circuitry of the camera device]) in accordance with a MIPI D-PHY (See Paragraph 19), and a first receiver coupled to the first transfer pad and a second receiver coupled to the second transfer pad (See Figure 2A and Paragraph 19 [differential MIPI D-PHY communication necessarily requires a receiver for each signal]). Ihlenburg further discloses the use of a reception mode when the interface circuit receives image data from and does not transmit image data to the external processor via the first transmission line and the second transmission line, and a transmission mode when the interface circuit transmits image data different from the received image data to the external processor via the first transmission line and the second transmission line, wherein the received image data is not image data transmitted by the transmitter (See Paragraph 19 [interface is bidirectional; data received by the interface circuit is “image data” in accordance with the broadest reasonable interpretation of the term]). Ihlenburg further discloses that the interface utilizes the MIPI D-PHY Specification (See Paragraph 19). Therefore, Ihlenburg necessarily and inherently requires that the interface circuit includes a termination block connected between the first transfer pad and the second transfer pad and including a first low-power receiver connected to the first transfer pad and a second low-power receiver connected to the second transfer pad, wherein the termination block is configured to monitor the first transmission line and the second transmission line by detecting a low-power signal sequence indicative of the transmission of second image data, different from the first image data, via the first low-power receiver and the second low-power receiver, wherein the second image data is not image data transmitted by the transmitter, wherein the termination block is configured to connect the first transfer pad and the second transfer pad in response to detecting the low-power signal sequence indicative of the second image data to adjust an impedance of the first transmission line, wherein the termination block includes a first switch, a first resistor, a second resistor, and a second switch connected in series between the first transfer pad and the second transfer pad, and a common mode capacitor connected to a node between the first resistor and the second resistor, and wherein the termination block is configured to connect the first transfer pad to the second transfer pad by the first switch, the second switch, the first resistor, and the second resistor to adjust the impedance, when the low-power signal sequence indicative of the second image data is detected based on an output signal of the first low-power receiver and an output signal of the second low-power receiver and the transmitter does not communicate with the external processor, as these are required by the MIPI D-PHY Specification. As evidenced by the MIPI D-PHY Specification, a MIPI D-PHY interface circuit, such as that of Ihlenburg, includes a termination block (See Page 21 Figure 1 ‘RX’ and Page 80 Figure 47) connected between a first transfer pad (See Page 80 Figure 47 ‘Dp’) and a second transfer pad (See Page 80 Figure 47 ‘Dn’) and including a first low-power receiver connected to the first transfer pad (See Page 21 Figure 1 ‘LP-RX’ upper receiver connected to Dp [differential MIPI D-PHY communication necessarily requires a receiver for each signal]) and a second low-power receiver connected to the second transfer pad (See Page 21 Figure 1 ‘LP-RX’ lower receiver connected to Dn [differential MIPI D-PHY communication necessarily requires a receiver for each signal]), wherein the termination block is configured to monitor the first transmission line and the second transmission line by detecting a low-power signal sequence indicative of the transmission of second data, different from the first data, via the first low-power receiver and the second low-power receiver (See Pages 33-35 Sections 5.2 – 5.3), wherein the second data is not data transmitted by the transmitter (See Pages 33-35 Sections 5.2 – 5.3), wherein the termination block is configured to connect the first transfer pad and the second transfer pad in response to detecting the low-power signal sequence indicative of the second data to adjust an impedance of the first transmission line (See Page 81 Lines 1464-1470 [termination impedance connecting the transmission lines must be enabled in high speed mode, and disabled in low-power mode]), wherein the termination block includes a first switch (See Page 80 Figure 47 transistor connected to ‘Dp’), a first resistor (See Page 80 Figure 47 ‘ZID/2’ connected to ‘Dp’), a second resistor (See Page 80 Figure 47 ‘ZID/2’ connected to ‘Dn’), and a second switch (See Page 80 Figure 47 transistor connected to ‘Dn’) connected in series between the first transfer pad and the second transfer pad (See Page 80 Figure 47), and a common mode capacitor connected to a node between the first resistor and the second resistor (See Page 80 Figure 47 ‘CCM‘), and wherein the termination block is configured to connect the first transfer pad to the second transfer pad by the first switch, the second switch, the first resistor, and the second resistor to adjust the impedance (See Page 81 Lines 1464-1470 [termination impedance connecting the transmission lines must be enabled in high speed mode, and disabled in low-power mode]), when the low-power signal sequence indicative of the second data is detected based on an output signal of the first low-power receiver and an output signal of the second low-power receiver (See Pages 33-35 Sections 5.2 – 5.3 and Page 81 Lines 1464-1470) and the transmitter does not communicate with the external processor (See Page 22 Lines 508-529 [transmitter cannot communicate with external devices during reception mode]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-5, 9-11, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ihlenburg with evidence of inherency provided by MIPI D-PHY Specification.
In reference to Claim 1, Ihlenburg discloses an image sensor comprising: a pixel array configured to generate electric charges in response to light (See Figure 2A ‘Imager’ and Paragraphs 24-27 [CMOS and CCD image sensors are a type of pixel array that generates electric charges in response to light]); a logic circuit configured to convert the electric charges into first image data (See Figure 2A ‘Logic’ and Paragraphs 20 and 24-27 [image processing circuitry]); and an interface circuit including a transmitter configured to transmit the first image data to an external processor (See Figure 2A ‘D-PHY’ and Paragraphs 19-21) via a first transfer pad connected to a first transmission line and a second transfer pad connected to a second transmission line (See Figure 2A STP/UTP Cable’ and Paragraphs 19-20 [differential MIPI D-PHY communication necessarily requires first and second transmission lines; the cable necessarily requires contact pads to connect the lines of the cable with the circuitry of the camera device]); wherein the transmitter includes a first output node connected to the first transfer pad and a second output node connected to the second transfer pad and is configured to output a differential signal including the first image data via the first output node and the second output node (See Figure 2A and Paragraph 19 [differential MIPI D-PHY communication necessarily requires an output driver for each signal]); wherein the interface circuit is configured to transmit the first image data in accordance with a MIPI standard (See Paragraphs 19-21). Ihlenburg further discloses the use of a reception mode when the interface circuit does not transmit image data to the external processor and a transmission mode when the interface circuit transmits image data to the external processor (See Paragraph 19 [interface is bidirectional; data received by the interface circuit is “image data” in accordance with the broadest reasonable interpretation of the term]). Ihlenburg further discloses that the interface utilizes the MIPI D-PHY Specification (See Paragraph 19). Therefore, Ihlenburg necessarily and inherently requires that the interface circuit includes a termination block connected between the first transfer pad and the second transfer pad, wherein the termination block includes a first switch, a first resistor, a second resistor, and a second switch connected between the first transfer pad and the second transfer pad, a common mode capacitor connected to a node between the first resistor and the second resistor, a control logic, and a first low-power receiver connected between the control logic and the first transfer pad and a second low-power receiver connected between the control logic and the second transfer pad, wherein the termination block is connected to the first output node and the second output node, wherein the control logic is configured to monitor statuses of the first transmission line and the second transmission line by detecting a low-power signal sequence transmitted over the first transfer pad and second transfer pad and received by the first low-power receiver and the second low-power receiver, wherein the control logic is configured to detect the low-power signal sequence corresponding to a predefined pattern indicative of a high-speed data transmission mode or a low-power operation mode, and wherein the control logic is configured to connect the first transfer pad and the second transfer pad by turning on the first switch and the second switch when the low-power signal sequence corresponding to the predefined pattern indicative of the high speed data transmission is detected and the transmitter does not communicate with the external processor, as these are required by the MIPI D-PHY Specification. As evidenced by the MIPI D-PHY Specification, a MIPI D-PHY interface circuit, such as that of Ihlenburg, includes an interface circuit including a transmitter (See Page 21 Figure 1 ‘TX’) configured to transmit first data to an external processor (See Page 20 Section 3) via a first transfer pad connected to a first transmission line (See Page 21 Figure 1 ‘Dp’ and Page 80 Figure 47 ‘Dp’) and a second transfer pad connected to a second transmission line (See Page 21 Figure 1 ‘Dn’ and Page 80 Figure 47 ‘Dn’), a termination block (See Page 21 Figure 1 ‘RX’ and Page 80 Figure 47) connected between the first transfer pad (See Page 21 Figure 1 ‘Dp’ and Page 80 Figure 47 ‘Dp’) and the second transfer pad (See Page 21 Figure 1 ‘Dn’ and Page 80 Figure 47 ‘Dn’), wherein the termination block includes a first switch (See Page 80 Figure 47 transistor connected to ‘Dp’), a first resistor (See Page 80 Figure 47 ‘ZID/2’ connected to ‘Dp’), a second resistor (See Page 80 Figure 47 ‘ZID/2’ connected to ‘Dn’), and a second switch (See Page 80 Figure 47 transistor connected to ‘Dn’) connected in series between the first transfer pad and the second transfer pad (See Page 80 Figure 47), a common mode capacitor connected to a node between the first resistor and the second resistor (See Page 80 Figure 47 ‘CCM‘), a control logic (See Page 21 Figure 1 ‘Lane Control and Interface Logic’ and Page 80 Figure 47 logic connected to ‘Termination Enable’), and a first low-power receiver connected between the control logic and the first transfer pad (See Page 21 Figure 1 ‘LP-RX’ upper receiver connected to Dp [differential MIPI D-PHY communication necessarily requires a receiver for each signal]), and a second low-power receiver connected between the control logic and the second transfer pad (See Page 21 Figure 1 ‘LP-RX’ lower receiver connected to Dn [differential MIPI D-PHY communication necessarily requires a receiver for each signal]), wherein the termination block is connected to the first output node and the second output node (See Page 21 Figure 1 and Page 80 Figure 47), and wherein the control logic is configured to monitor statuses of the first transmission line and the second transmission line by detecting a low-power signal sequence transmitted over the first transfer pad and second transfer pad and received by the first low-power receiver and the second low-power receiver (See Pages 33-35 Sections 5.2 – 5.3 and Page 81 Lines 1464-1470), wherein the control logic is configured to detect the low-power signal sequence corresponding to a predefined pattern indicative of a high-speed data transmission mode (See Pages 33-35 Sections 5.2 – 5.4) or a low-power operation mode (See Pages 33-35 Sections 5.2 – 5.3, Pages 41-42 Section 5.6, and Page 43 Section 5.6.2), and wherein the control logic is configured to connect the first transfer pad and the second transfer pad by turning on the first switch and the second switch when the low-power signal sequence corresponding to the predefined pattern indicative of the high speed data transmission is detected (See Page 81 Lines 1464-1470 [termination impedance connecting the transmission lines must be enabled in high speed mode, and disabled in low-power mode]) and the transmitter does not communicate with the external device (See Page 22 Lines 508-529 [transmitter cannot communicate with external devices during reception mode]). Ihlenburg further discloses, as evidenced by the MIPI D-PHY Specification, that the first switch, the first resistor, the second resistor, and the second switch are connected in series in the order of the first resistor (See Page 80 Figure 47 ‘ZID/2’ connected to ‘Dp’), the first switch (See Page 80 Figure 47 transistor connected to ‘Dp’), the second switch (See Page 80 Figure 47 transistor connected to ‘Dn’), and the second resistor (See Page 80 Figure 47 ‘ZID/2’ connected to ‘Dn’). However, Ihlenburg does not explicitly disclose that that the first switch, the first resistor, the second resistor, and the second switch are connected in series in the order of the first switch, the first resistor, the second resistor, and the second switch. One of ordinary skill in the art would recognize that there are only a finite number of four possible orderings (resistor1-switch1-switch2-resistor2, switch1-resistor1-resistor2-switch2, resistor1-switch1-resistor2-switch2, and switch1-resistor1-switch2-resistor2) of the aforementioned switches and resistors between the first and second transmission lines. One of ordinary skill would further recognize that there is no functional difference in the serial order of switches and resistors in an electric circuit, and that changing the order of the switches and resistors in Ihlenburg would not change its operation.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Ihlenburg by trying the ordering of the switches and resistors in the order of the first switch, the first resistor, the second resistor, and the second switch in an effort to provide an improved construction of the device of Ihlenburg, resulting in the invention of Claim 1, because there are only a finite number of four possible orderings of the switches and resistors, there is no functional difference in the serial order of switches and resistors in an electric circuit, and one of ordinary skill in the art has good reason to pursue the known options within their technical grasp.
In reference to Claim 4, Ihlenburg discloses the limitations as applied to Claim 2 above. Ihlenburg further discloses that the MIPI standard is a MIPI D-PHY (See Paragraph 19).
In reference to Claim 5, Ihlenburg discloses the limitations as applied to Claim 4 above. Ihlenburg further discloses that the control logic is configured to connect the first transfer pad and the second transfer pad when the control logic detects transmission of second image data, different from the first image data, via the first transmission line and the second transmission line (See Paragraph 19 [data received by the interface circuit is “image data” in accordance with the broadest reasonable interpretation of the term; when the interface circuit detects that the first and second transmission lines are in a reception mode receiving image data, the switchable resistor termination is connected, and when the interface circuit detects that the first and second transmission lines are in a transmission mode transmitting image data, the switchable resistor termination is disconnected]). This is evidenced by the MIPI D-PHY Specification, which discloses that the control logic of a MIPI D-PHY interface circuit is configured to connect the first transfer pad and the second transfer pad when the control logic detects transmission of second data, different from the first data, via the first transmission line and the second transmission line (See Pages 80-81 Lines 1459-1467).
In reference to Claim 9, Ihlenburg discloses an image sensor comprising: a pixel array configured to generate electric charges in response to light (See Figure 2A ‘Imager’ and Paragraphs 24-27 [CMOS and CCD image sensors are a type of pixel array that generates electric charges in response to light]); a logic circuit configured to convert the electric charges into first image data (See Figure 2A ‘Logic’ and Paragraphs 20 and 24-27 [image processing circuitry]); and an interface circuit including a transmitter configured to transmit the first image data to an external processor (See Figure 2A ‘D-PHY’ and Paragraphs 19-21) via a first transfer pad connected to a first transmission line and a second transfer pad connected to a second transmission line (See Figure 2A STP/UTP Cable’ and Paragraphs 19-20 [differential MIPI D-PHY communication necessarily requires first and second transmission lines; the cable necessarily requires contact pads to connect the lines of the cable with the circuitry of the camera device]) in accordance with a MIPI D-PHY (See Paragraph 19). Ihlenburg further discloses the use of a reception mode when the interface circuit receives image data from and does not transmit image data to the external processor via the first transmission line and the second transmission line, and a transmission mode when the interface circuit transmits image data different from the received image data to the external processor via the first transmission line and the second transmission line (See Paragraph 19 [interface is bidirectional; data received by the interface circuit is “image data” in accordance with the broadest reasonable interpretation of the term]). Ihlenburg further discloses that the interface utilizes the MIPI D-PHY Specification (See Paragraph 19). Therefore, Ihlenburg necessarily and inherently requires that the interface circuit includes a termination block including a first switch, a first resistor, a second resistor, and a second switch connected between the first transfer pad and the second transfer pad in series, a common mode capacitor connected to a node between the first resistor and the second resistor, a first low-power receiver connected between the first transfer pad and a control logic of the termination block, and a second low-power receiver connected between the second transfer pad and the control logic of the termination block, wherein the termination block is configured to connect the first transfer pad and the second transfer pad by the first switch, the second switch, the first resistor, and the second resistor, when the transmitter does not communicate with the external processor and another image data different from the image data is transmitted via the first transmission line and the second transmission line, wherein the termination block is configured to monitor statuses of the first transmission line based on an output signal of the first low-power receiver and an output signal of the second low-power receiver, and wherein the termination block is configured to connect the first transmission line and the second transmission line based on a monitoring result, as these are required by the MIPI D-PHY Specification. As evidenced by the MIPI D-PHY Specification, a MIPI D-PHY interface circuit, such as that of Ihlenburg, includes an interface circuit including a transmitter (See Page 21 Figure 1 ‘TX’) configured to transmit data to an external processor (See Page 20 Section 3) via a first transfer pad connected to a first transmission line (See Page 21 Figure 1 ‘Dp’ and Page 80 Figure 47 ‘Dp’) and a second transfer pad connected to a second transmission line (See Page 21 Figure 1 ‘Dn’ and Page 80 Figure 47 ‘Dn’), a termination block (See Page 21 Figure 1 ‘RX’ and Page 80 Figure 47) including a first switch (See Page 80 Figure 47 transistor connected to ‘Dp’), a first resistor (See Page 80 Figure 47 ‘ZID/2’ connected to ‘Dp’), a second resistor (See Page 80 Figure 47 ‘ZID/2’ connected to ‘Dn’), and a second switch (See Page 80 Figure 47 transistor connected to ‘Dn’) connected in series between connected in series (See Page 80 Figure 47) between the first transfer pad (See Page 21 Figure 1 ‘Dp’ and Page 80 Figure 47 ‘Dp’) and the second transfer pad (See Page 21 Figure 1 ‘Dn’ and Page 80 Figure 47 ‘Dn’), a common mode capacitor connected to a node between the first resistor and the second resistor (See Page 80 Figure 47 ‘CCM‘), a first low-power receiver connected between the first transfer pad (See Page 21 Figure 1 ‘LP-RX’ upper receiver connected to Dp [differential MIPI D-PHY communication necessarily requires a receiver for each signal]) and a control logic of the termination block (See Page 21 Figure 1 ‘Lane Control and Interface Logic’ and Page 80 Figure 47 logic connected to ‘Termination Enable’), and a second low-power receiver connected between the second transfer pad and the control logic of the termination block (See Page 21 Figure 1 ‘LP-RX’ lower receiver connected to Dn [differential MIPI D-PHY communication necessarily requires a receiver for each signal]), wherein the termination block is configured to connect the first transfer pad and the second transfer pad by the first switch, the second switch, the first resistor, and the second resistor, when the transmitter does not communicate with the external processor (See Page 22 Lines 508-529 [transmitter cannot communicate with external devices during reception mode]) and another data different from the data is transmitted via the first transmission line and the second transmission line (See Page 81 Lines 1464-1470 [termination impedance connecting the transmission lines must be enabled in high speed mode, and disabled in low-power mode]), wherein the termination block is configured to monitor statuses of the first transmission line, based on an output signal of the first low-power receiver and output signal of the second low-power receiver (See Pages 33-35 Sections 5.2 – 5.3 and Page 81 Lines 1464-1470), and wherein the termination block is configured to connect the first transmission line and the second transmission line based on a monitoring result (See Page 81 Lines 1464-1470 [termination impedance connecting the transmission lines must be enabled in high speed mode, and disabled in low-power mode]). However, Ihlenburg does not explicitly disclose that that the first switch, the first resistor, the second resistor, and the second switch are connected in series in the order of the first switch, the first resistor, the second resistor, and the second switch. One of ordinary skill in the art would recognize that there are only a finite number of four possible orderings (resistor1-switch1-switch2-resistor2, switch1-resistor1-resistor2-switch2, resistor1-switch1-resistor2-switch2, and switch1-resistor1-switch2-resistor2) of the aforementioned switches and resistors between the first and second transmission lines. One of ordinary skill would further recognize that there is no functional difference in the serial order of switches and resistors in an electric circuit, and that changing the order of the switches and resistors in Ihlenburg would not change its operation.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Ihlenburg by trying the ordering of the switches and resistors in the order of the first switch, the first resistor, the second resistor, and the second switch in an effort to provide an improved construction of the device of Ihlenburg, resulting in the invention of Claim 9, because there are only a finite number of four possible orderings of the switches and resistors, there is no functional difference in the serial order of switches and resistors in an electric circuit, and one of ordinary skill in the art has good reason to pursue the known options within their technical grasp.
In reference to Claim 10, Ihlenburg discloses the limitations as applied to Claim 9 above. Ihlenburg further discloses that the transmitter is configured to transmit the image data as a frame unit or a line unit of the pixel array (See Page 2 Figure 1 ‘CMOS Image Sensor’ [a CMOS image sensor outputs frames of image data consisting of lines of image data]).
In reference to Claim 11, Ihlenburg discloses the limitations as applied to Claim 10 above. Ihlenburg, as evidenced by the MIPI D-PHYS Specification, necessarily and inherently requires that the termination block is configured to enable the resistor termination to connect the first transfer pad and the second transfer pad during a reception mode when the interface circuit does not transmit the first image data to the external processor and to disable the resistor termination to disconnect the first transmission line and the second transmission line during a transmission mode when the interface circuit transmits the first image data to the external processor (See Page 81 Lines 1464-1470).
In reference to Claim 19, Ihlenburg discloses the limitations as applied to Claim 1 above. Ihlenburg, as evidenced by MIPI D-PHY Specification, further discloses that the termination block further includes a first low-power receiver including an input node connected to the first transfer pad and an output node connected to the control logic (See Figure 2A of Ihlenburg and Page 21 Figure 1 ‘LP-RX’ and Page 80 Figure 47 of MIPI D-PHY Specification [differential MIPI D-PHY communication necessarily requires a receiver having an coupled to the transfer pad and an output coupled to the detection controller for each signal]), and a second low-power receiver including an input node connected to the second transfer pad and an output node connected to the control logic (See Figure 2A of Ihlenburg and Page 21 Figure 1 ‘LP-RX’ and Page 80 Figure 47 of MIPI D-PHY Specification [differential MIPI D-PHY communication necessarily requires a receiver having an coupled to the transfer pad and an output coupled to the detection controller for each signal]), and wherein the control logic is configured to detect the low-power sequence by using the output signal of the first low-power receiver and the output signal of the second low-power receiver (See Pages 33-35 Sections 5.2 – 5.3 and Page 81 Lines 1464-1470).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ihlenburg as applied to Claim 16 above.
In reference to Claim 20, Ihlenburg discloses the limitations as applied to Claim 16 above. However, Ihlenburg does not explicitly disclose that the first switch is directly connected to the first transfer pad and the second switch is directly connected to the second transfer pad. One of ordinary skill in the art would recognize that there are only a finite number of four possible orderings (resistor1-switch1-switch2-resistor2, switch1-resistor1-resistor2-switch2 [each switch being directly coupled to a transfer pad], resistor1-switch1-resistor2-switch2, and switch1-resistor1-switch2-resistor2) of the aforementioned switches and resistors between the first and second transfer pads. One of ordinary skill would further recognize that there is no functional difference in the serial order of switches and resistors in an electric circuit, and that changing the order of the switches and resistors in Ihlenburg would not change its operation.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Ihlenburg by trying the ordering of the switches and resistors in the order of the first switch, the first resistor, the second resistor, and the second switch (each switch directly coupled to a transfer pad) in an effort to provide an improved construction of the device of Ihlenburg, resulting in the invention of Claim 20, because there are only a finite number of four possible orderings of the switches and resistors, there is no functional difference in the serial order of switches and resistors in an electric circuit, and one of ordinary skill in the art has good reason to pursue the known options within their technical grasp.
Response to Arguments
Applicant's arguments filed 20 November 2025 have been fully considered but they are not persuasive.
Applicant has argued that the MIPI D-PHY Specification does not disclose the claimed first and second low-power receivers (See Page 8). In response, the Examiner notes that, as indicated in the above rejections, the MIPI D-PHY Specification discloses a first low-power receiver connected between the control logic and the first transfer pad (See Page 21 Figure 1 ‘LP-RX’ upper receiver connected to Dp [differential MIPI D-PHY communication necessarily requires a receiver for each signal]) and a second low-power receiver connected between the control logic and the second transfer pad (See Page 21 Figure 1 ‘LP-RX’ lower receiver connected to Dn [differential MIPI D-PHY communication necessarily requires a receiver for each signal]).
Applicant has argued that Ihlenburg and the MIPI D-PHY Specification do not disclose that and the control logic is configured to connect the first transfer pad and the second transfer pad by turning on the first switch and the second switch when the low-power signal sequence corresponding to the predefined pattern indicative of the high speed data transmission is detected and the transmitter does not communicate with the external device (See Pages 9-10). In response, the Examiner notes that, as indicated in the above rejections, the MIPI D-PHY Specification discloses that the control logic is configured to connect the first transfer pad and the second transfer pad by turning on the first switch and the second switch when the low-power signal sequence corresponding to the predefined pattern indicative of the high speed data transmission is detected (See Page 81 Lines 1464-1470 [termination impedance connecting the transmission lines must be enabled in high speed mode, and disabled in low-power mode]) and the transmitter does not communicate with the external device (See Page 22 Lines 508-529 [transmitter cannot communicate with external devices during reception mode]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS J CLEARY whose telephone number is (571)272-3624. The examiner can normally be reached Monday-Friday 8AM-5PM.
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/THOMAS J. CLEARY/Primary Examiner, Art Unit 2175
Prosecution Insights