Prosecution Insights
Last updated: May 29, 2026
Application No. 18/143,611

Printed Circuit Board Structure and Printed Circuit Board Detection Method

Non-Final OA §102§103
Filed
May 05, 2023
Priority
Apr 07, 2023 — TW 112113072
Examiner
NGUYEN, VINH P
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Acebiotek Co. Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
1176 granted / 1362 resolved
+18.3% vs TC avg
Strong +16% interview lift
Without
With
+16.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
17 currently pending
Career history
1380
Total Applications
across all art units

Statute-Specific Performance

§101
3.9%
-36.1% vs TC avg
§103
51.5%
+11.5% vs TC avg
§102
8.0%
-32.0% vs TC avg
§112
26.7%
-13.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1362 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions The restriction requirement mailed on 02/03/2026 is hereby withdrawn and all claims 1-12 are examined. Claim Rejections - 35 USC § 102 (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 1 is rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Liu et al (CN-115226289 A). PNG media_image1.png 461 975 media_image1.png Greyscale As to claim 1, Liu et al disclose a printed circuit board (100) as shown in figure 2 comprising: a plurality of interface layers (10,20,30,40) ; and a detection window (52, and corresponding detection pad 51) , disposed at a plurality of detection regions (101) corresponding to a projection position of a detection entrance ( inspection hole 53) in the plurality of interface layers 10,20,30,40) , wherein the detection window (window 52 and corresponding detection pad 51) is utilized to detect a plurality of characteristics (see page 6, paragraph 1; through the inspection hole 53 and the window 52, the light can be irradiated to the substrate 10 and through the substrate 10 to the detection pad 51, so as to observe the detection pad 51 and the first covering film 40 or the second covering film of the bonding area of the filling condition, so that judge the first circuit layer 20 and the second circuit layer 30 are respectively connected with the covering film 40 of the pressing condition of the plurality of interface layers (10,20,30,40). Claim 1 is rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kasashima et al (PG-pub# 20160192473). As to claim 1, Kasashima et al disclose a printed circuit board structure (10) as shown in figure 2 comprising: a plurality of interface layers L2-l5); and a detection window (a through hole (6b)) , disposed at a plurality of detection regions (areas in which the though hole (6b) cutting through the layers (L2-L5) corresponding to a projection position of a detection entrance in the plurality of interface layers (L2-L5). It is noted that the limitation of “wherein the detection window is utilized to detect a plurality of characteristics of the plurality of interface layers” is considered as “an intended use” and it is not given any patentable weight. Claim Rejections - 35 USC § 103 Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al (CN-115226289 A). As to claim 2, Liu et al disclose a printed circuit board (100) as mentioned in claim 1 but do not explicitly mention about a material of the plurality of detection regions is a bakelite, a glass, an epoxy resin or a plastic. However, it would have been obvious for one of ordinary skill in the art to recognize that the material for the detection region (101) is an insulator and the conductive detection pad (51) located within the detection region (101) and that the material for the insulator such as glass or epoxy resin or plastic is well known in the art. As to claim 3, Liu et al disclose a printed circuit board (100) as mentioned in claims 1 and 2 but do not explicitly mention about wherein at least one detection region of the plurality of detection regions is a metal, a heavily doped material or a highly reflective material. It would have been obvious for one of ordinary skill in the art to recognize that the detection pad (51) is located within the detection region (101), therefore this detection pad (51) is considered as at least one detection region and it is a metal (conductive material). As to claim 4, Liu et al disclose a printed circuit board (100) as mentioned in claim 1 but do not explicitly mention about wherein an area of the detection window is greater than or equal to 0.05 millimeters by 0.05 millimeters. However, the size of the window is considered as an obvious design choice sincet he size of the package were not sufficient to patentably distinguish over the prior art and it does not changed the operation of the printed circuit board (see In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955)). The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Allowable Subject Matter Claims 5-12 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art does not disclose A printed circuit board detection method having a combined method steps of disposing a detection window at a plurality of detection regions corresponding to a projection position of a detection entrance in a plurality of interface layers of a printed circuit board; and utilizing a first terahertz electromagnetic wave to pass through the detection window of the printed circuit board, to detect a plurality of characteristics of the plurality of interface layers of the printed circuit board as recited in claim 5. Claims 6-12 depend from allowed claim 5, they are also allowed accordingly. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kazama et al (Pat# 8,073,641) disclose Electromagnetic Field Distribution Measuring Method, Apparatus For The Method, Computer Program And Information Recording Medium. Narita et al (Pat# 7,952,365) disclose Resonator, Printed Board, And Method For Measuring Complex Dielectric Constant. Herman et al (Pat# 8,289,043) disclose Simulation Of Printed Circuit Board Impedance Variations And Crosstalk Effects. Van Mechelen et al (Pat# 9,304,046) disclose Sensor System And Method For Characterizing A Coated Body. Wallace et al (Pat# 11,300,505) disclose Terahertz-based Conveyor Belt Monitoring. Sheen et al (pat# 5,631,572) disclose Printed Circuit Board Tester Using Magnetic Induction. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINH P NGUYEN whose telephone number is (571)272-1964. The examiner can normally be reached M-F 6:00am-4:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Phan Huy can be reached on 571-272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VINH P NGUYEN/Primary Examiner, Art Unit 2858
Read full office action

Prosecution Timeline

May 05, 2023
Application Filed
May 07, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
99%
With Interview (+16.2%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1362 resolved cases by this examiner. Grant probability derived from career allowance rate.

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