DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "the output signal" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-8, 11-12, 16-17 and 20-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moehlmann et al (US 20220365173 A1) in view of Bereza et al (US 20080298476 A1).
As per claims 1 and 17, Moehlmann et al teaches a multi-device system, comprising: a plurality of devices, wherein the plurality of devices (see fig.4 elements TX, RX, Chirp, ADC and 401, 402 ) are configured to operate based on a first clock signal (see fig.4 element 403) supplied to the plurality of devices (see abstract for…… the leader module (401) comprising a first oscillator (403) configured to provide a first clock signal at a first frequency to each follower module (402) and para [0051] for…… The leader module 401 comprises a first oscillator 403, which provides a first clock signal at a first frequency. The first clock signal is provided via connection paths 404, 405 between the modules 401, 402 to each of the modules 401, 402); a plurality of clock dividers (see fig.4 elements 4061 and 4062 and abstract for….. each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator (300), the PLL clock signal generator (300) comprising a divide by n clock divider (304) ) configured to generate a second clock signal (see output of each CLOCKPLL) from the first clock signal (element 403 and para [0051] for… The first clock signal is provided via connection paths 404, 405 between the modules 401, 402 to each of the modules 401, 402) and provide the second clock signal to the plurality of devices (see para [0051] for….. The connection paths 404, 405 are configured to provide the first clock signal as an input to a PLL clock signal generator 4061, 4062 in each module. The clock signal generator 4061, 4062 in each module 401, 402 is of the form described above in relation to FIG. 3); and a delay circuit incur a specific delay (fig.7 element 701.sub.3-5) to the second clock signal such that a phase of the second clock signal is provided to the plurality of devices (see para [0118] for…. The divide-by-n clock divider may comprise a divider core configured to divide the second clock signal into an intermediate clock signal, a chain of flip-flops configured to receive alternating edges of the intermediate clock signal and a plurality of logic gates arranged to combine outputs from consecutive pairs of the chain of flip-flops to provide the output phase shifted clock signals and para [0057] for…. The final FF 601.sub.8 may be loaded by a dummy device to balance the load of the FFs and therefore the propagation delay of the clock phases and para [0058] for…… the divider core of the divider 700 consists of the first two FFs 701.sub.1,2 and the chain of FFs consists of FFs 701.sub.3-5.. In this case, care needs to be taken to ensure an equal load on each branch and to minimise any different delays of the AND and OR-gates to achieve proper phase- and duty-cycle alignment. If delays of AND- and OR-gates can be balanced. the circuit is advantageous compared to the implementation in FIG. 5 because it does not use inverters for creating the inverted signals Examiner Note: a chain of flip-flops is well known to one of ordinary skill in the art to be functionally equivalent to delay circuit or delay buffer).
However Moehlmann et al does not explicitly teach a delay circuit incur a specific delay to the second clock signal such that a phase of the second clock signal provided to the plurality of devices is spread over time.
Bereza et al teaches a delay circuit generating a specific delay to the second clock signal such that a phase of the second clock signal provided to the plurality of devices is spread over time (see fig.9 element 503 and para [0097] for…. Phase generating DLL circuit 503 adaptively spreads the multiple phases at outputs 515. Specifically, it uses phase detector 512 and digital loop filter 509 coupled in a feedback loop to control desired characteristics of programmable delay circuits 506A-506F and para [0102] for… Note that phase generating DLL circuit 503 may have associated with it a relatively large time constant. and para [0126] for….. coupling programmable delay circuits 506A-506N in a cascade configuration forces the generation of equally spaced phases across a single data unit interval (UI)).
It would have obvious to one of ordinary skill in the art, at the time of filing or before the effective filing date of the claimed invention, to modify Moehlmann to include a delay circuit generating a specific delay to the second clock signal such that a phase of the second clock signal provided to the plurality of devices is spread over time in order to achieve acquisition and recover the data and clock signal. Furthermore the delay circuit would facilitate the plurality of devices to obtain equally spaced alignment of the phases, as spaced according to the number of buffers used. Such modification would enhance the multi-channel devices in determining a level of performance through a variety of performance measures or criterion, such as bit error rate performance, and subsequently achieve the highest timing acquisition during the phase alignment.
As per claims 4 and 20, Moehlmann et al and Bereza in combination would teach wherein the phase of the second clock signal provided to the plurality of devices is spread evenly over time (Bereza para [0126] for….. coupling programmable delay circuits 506A-506N in a cascade configuration forces the generation of equally spaced phases across a single data unit interval (UI)) in order to achieve acquisition and recover the data and clock signal. Furthermore the delay circuit would facilitate the plurality of devices to obtain equally spaced alignment of the phases, as spaced according to the number of buffers used. Such modification would enhance the multi-channel devices in determining a level of performance through a variety of performance measures or criterion, such as bit error rate performance, and subsequently achieve the highest timing acquisition during the phase alignment.
As per claim 5, Moehlmann et al and Bereza in combination would teach wherein the phase of the second clock signal provided to a pair of adjacent devices is inverted (see Bereza and para [0117] for.. Programmable delay circuit 506N includes a pair of cascaded inverters, i.e., inverter 630 coupled to inverter 636 and para [0131] for…. the all-digital delay-locked loop (DLL) circuit comprises a plurality of controlled inverters) in order to achieve acquisition and recover the data and clock signal. Furthermore the delay circuit would facilitate the plurality of devices to obtain equally spaced alignment of the phases, as spaced according to the number of buffers used. Such modification would enhance the multi-channel devices in determining a level of performance through a variety of performance measures or criterion, such as bit error rate performance, and subsequently achieve the highest timing acquisition during the phase alignment.
As per claims 6 and 21, Moehlmann et al and Bereza in combination would teach wherein the delay circuit is configured to incur the specific delay on an output signal of each clock divider (see Moehlmann para [0058] for…… the divider core of the divider 700 consists of the first two FFs 701.sub.1,2 and the chain of FFs consists of FFs 701.sub.3-5.. In this case, care needs to be taken to ensure an equal load on each branch and to minimise any different delays of the AND and OR-gates to achieve proper phase- and duty-cycle alignment. If delays of AND- and OR-gates can be balanced,) in order to achieve acquisition and recover the data and clock signal. Furthermore the delay circuit would facilitate the plurality of devices to obtain equally spaced alignment of the phases, as spaced according to the number of buffers used. Such modification would enhance the multi-channel devices in determining a level of performance through a variety of performance measures or criterion, such as bit error rate performance, and subsequently achieve the highest timing acquisition during the phase alignment.
As per claim 7, Moehlmann et al and Bereza in combination would teach wherein the output signal is delayed by a multiple of a period of the first clock signal in order to achieve acquisition and recover the data and clock signal. Furthermore the delay circuit would facilitate the plurality of devices to obtain equally spaced alignment of the phases, as spaced according to the number of buffers used. Such modification would enhance the multi-channel devices in determining a level of performance through a variety of performance measures or criterion, such as bit error rate performance, and subsequently achieve the highest timing acquisition during the phase alignment.
As per claim 8, Moehlmann et al and Bereza in combination would teach The multi-device system of claim 1, wherein the delay circuit is a programmable delay circuit (see Bereza para [0097] for… Phase generating DLL circuit 503 adaptively spreads the multiple phases at outputs 515. Specifically, it uses phase detector 512 and digital loop filter 509 coupled in a feedback loop to control desired characteristics of programmable delay circuits 506A-506F (e.g., delay, speed).) in order to achieve acquisition and recover the data and clock signal. Furthermore the delay circuit would facilitate the plurality of devices to obtain equally spaced alignment of the phases, as spaced according to the number of buffers used. Such modification would enhance the multi-channel devices in determining a level of performance through a variety of performance measures or criterion, such as bit error rate performance, and subsequently achieve the highest timing acquisition during the phase alignment.
As per claim 11, Moehlmann et al and Bereza in combination would teach wherein the output signal is delayed by a multiple of a period of the first clock signal in order to achieve acquisition and recover the data and clock signal. Furthermore the delay circuit would facilitate the plurality of devices to obtain equally spaced alignment of the phases, as spaced according to the number of buffers used. Such modification would enhance the multi-channel devices in determining a level of performance through a variety of performance measures or criterion, such as bit error rate performance, and subsequently achieve the highest timing acquisition during the phase alignment.
As per claims 12 and 23, Moehlmann et al and Bereza in combination would teach wherein the specific delay depends on configuration (see Bereza fig.14 or 15 and para [0093] for…. a multi-stage DLL that includes programmable delay circuits 506A-506F (e.g., as implemented with multiplexers or other desired circuitry) coupled in a series or cascade configuration, known to persons of ordinary skill in the art who have the benefit of the description of the disclosed concepts. Note that one may use more buffers/delay elements to provide more resolution in the CDR system by decreasing the spacing between samples, as desired) of the plurality of devices in order to achieve acquisition and recover the data and clock signal. Furthermore the delay circuit would facilitate the plurality of devices to obtain equally spaced alignment of the phases, as spaced according to the number of buffers used. Such modification would enhance the multi-channel devices in determining a level of performance through a variety of performance measures or criterion, such as bit error rate performance, and subsequently achieve the highest timing acquisition during the phase alignment.
As per claim 16, Moehlmann et al and Bereza in combination would teach where the devices are transceivers (see Bereza fig.2 element 10 and para [0029] for…… FIG. 2 shows a simplified block diagram of an IC 10 with the order of transmitter 16 and serializer 20 reversed, and with the order of receiver 18 and de-serializer 22 reversed) in order to achieve acquisition and recover the data and clock signal. Furthermore the delay circuit would facilitate the plurality of devices to obtain equally spaced alignment of the phases, as spaced according to the number of buffers used. Such modification would enhance the multi-channel devices in determining a level of performance through a variety of performance measures or criterion, such as bit error rate performance, and subsequently achieve the highest timing acquisition during the phase alignment.
As per claim 22, Moehlmann et al and Bereza in combination would teach, wherein the specific delay is adaptively changed (see Bereza para [0097] for…Phase generating DLL circuit 503 adaptively spreads the multiple phases at outputs 515. Specifically, it uses phase detector 512 and digital loop filter 509 coupled in a feedback loop to control desired characteristics of programmable delay circuits 506A-506F and para [0109] for…. the digital loop filter 509 produced control words (Dcntl) that change the operating characteristics of programmable delay circuits 506A-506N) in order to achieve acquisition and recover the data and clock signal. Furthermore the delay circuit would facilitate the plurality of devices to obtain equally spaced alignment of the phases, as spaced according to the number of buffers used. Such modification would enhance the multi-channel devices in determining a level of performance through a variety of performance measures or criterion, such as bit error rate performance, and subsequently achieve the highest timing acquisition during the phase alignment.
-----Claim(s) 2-3 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moehlmann et al (US 20220365173 A1) in view of Bereza et al (US 20080298476 A1) and in further view of J et al (US 20230136353 A1)
As per claims 2 and 18, Moehlmann et al and Bereza in combination do not teach wherein each of the plurality of clock dividers is configured to be reset based on a reference clock signal provided to each clock divider, and the delay circuit is configured to incur the specific delay on the reference clock signal provided to each clock divider
J et al teach wherein each of the plurality of clock dividers (see fig.4 element 410-1 and 410-2 and para [0044] for… Each output-generator 480 receives PLL output fout on path 131, sync-2 on path 421 and generates divided signal on corresponding path 495 and para [0074] for…..the output-generators will wait for the common internally generated reference to start the output dividers (counters).) and is configured to be reset based on a reference clock signal (see J et al fig.4 element 131 and para [0025] for…. fout 131 is shown locked to fref 101 with a frequency of 10 times that of fref 101 for illustration.) provided to each clock divider, and the delay circuit is configured to incur the specific delay on the reference clock signal provided to each clock divider (see J et al and para [0060] for…. delay block 435-1 generates divider-reset on path 436-1 (not shown) to release counter 410-1 from reset).
It would have obvious to one of ordinary skill in the art, at the time of filing or before the effective filing date of the claimed invention, to modify Moehlmann et al and Bereza to include plurality of clock dividers is configured to be reset based on a reference clock signal provided to each clock divider in order to achieve acquisition and recover the data and clock signal. Furthermore the delay circuit would facilitate the plurality of devices to obtain equally spaced alignment of the phases, as spaced according to the number of buffers used. Such modification would enhance the multi-channel devices in determining a level of performance through a variety of performance measures or criterion, such as bit error rate performance, and subsequently achieve the highest timing acquisition during the phase alignment.
As per claims 3 and 19, Moehlmann et al, Bereza and J et al in combination would teach wherein the reference clock signal is delayed by a multiple of a period of the first clock signal in order to achieve acquisition and recover the data and clock signal. Furthermore the delay circuit would facilitate the plurality of devices to obtain equally spaced alignment of the phases, as spaced according to the number of buffers used. Such modification would enhance the multi-channel devices in determining a level of performance through a variety of performance measures or criterion, such as bit error rate performance, and subsequently achieve the highest timing acquisition during the phase alignment.
-----Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moehlmann et al (US 20220365173 A1) in view of Bereza et al (US 20080298476 A1) and in further view of Tada et al (US 20110204908 A1).
As per claim 9, Moehlmann et al and Bereza in combination do not teach wherein the delay circuit comprises a chain of multiple pairs of a shift register and a multiplexer coupled in series, wherein each shift register in the chain is configured to operate on the first clock signal, the reference clock signal is coupled to one input of the multiplexer, and an output of the multiplexer is coupled to an input of a subsequent shift register in the chain, and an output of the shift register is coupled to another input of the multiplexer.
Tada et al teaches the delay circuit (see fig.3) comprises a chain of multiple pairs of a shift register (element 302) and a multiplexer (see element 301) coupled in series, wherein each shift register in the chain is configured to operate on the first clock signal, the reference clock signal is coupled to one input of the multiplexer, and an output of the multiplexer is coupled to an input of a subsequent shift register in the chain, and an output of the shift register is coupled to another input of the multiplexer (see para [0027] for….As shown in FIG. 3, in the clock state storage circuit CLKST, a pair of a selector 301 and a flip-flop 302 is connected in series. A recording clock clk0 is input to each flip-flop 302).
It would have obvious to one of ordinary skill in the art, at the time of filing or before the effective filing date of the claimed invention, to modify Moehlmann et al and Bereza to include a chain of multiple pairs of a shift register and a multiplexer coupled in series, wherein each shift register in the chain is configured to operate on the first clock signal in order to achieve acquisition and recover the data and clock signal. Furthermore the delay circuit would facilitate the plurality of devices to obtain equally spaced alignment of the phases, as spaced according to the number of buffers used. Such modification would enhance the multi-channel devices in determining a level of performance through a variety of performance measures or criterion, such as bit error rate performance, and subsequently achieve the highest timing acquisition during the phase alignment.
------Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moehlmann et al (US 20220365173 A1) in view of Bereza et al (US 20080298476 A1) and in further view of Williams (US 20040041947 A1).
As per claim 10, Moehlmann et al and Bereza in combination do not teach wherein the delay circuit comprises a counter and a comparator, wherein the counter is configured to increment by the first clock signal and reset by the second clock signal, and the comparator is configured to compare an output of the counter to a threshold, wherein the second clock signal is output based on an output of the comparator.
Williams teaches a delay circuit (see fig.5 element 80) comprises a counter (see element 100) and a comparator (see element 102) wherein the counter is configured to increment by the first clock signal (see element 32) and reset (see element 114), by the second clock signal (see element 112 ), and the comparator is configured to compare an output of the counter to a threshold (see element 38), wherein the second clock signal is output based on an output of the comparator (see fig.5 and para [0021] for…. The up/down counter 100 may be clocked by the first control signal 32, and the count direction may be controlled by a sign "bit" 108 of the control signal 38 from the control system 30. The comparator 102 may receive the control signal 38 and a count output 110 from the up/down counter 100, and may compare these two values. Each time that the count value may reach the value defined by the control signal 38, the comparator may assert an output 112 indicative that the tap position of the first delay line 54 should be moved (e.g., either to increase the delay, or to decrease the delay). The output 112 may be fed back to a reset input 114 of the up/down counter 100 to reset the count value.).
It would have obvious to one of ordinary skill in the art, at the time of filing or before the effective filing date of the claimed invention, to modify Moehlmann et al and Bereza to include a counter and a comparator, wherein the counter is configured to increment by the first clock signal and reset by the second clock signal in order to achieve acquisition and recover the data and clock signal. The predetermined prescaler value stored in the predetermined prescaler value unit would be preprogrammed so that first clock synchronize with the second clock in term of phase and frequency. Furthermore the delay circuit would facilitate the plurality of devices to obtain equally spaced alignment of the phases, as spaced according to the number of buffers used. Such modification would enhance the multi-channel devices in determining a level of performance through a variety of performance measures or criterion, such as bit error rate performance, and subsequently achieve the highest timing acquisition during the phase alignment.
------Claim(s) 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moehlmann et al (US 20220365173 A1) in view of Bereza et al (US 20080298476 A1) and in further view Kundu et al (US 12556192 B2).
As per claim 13, Moehlmann et al and Bereza in combination do not teach comprising a calibration circuit configured to change the specific delay incurred by the delay circuit.
Kundu et al teaches comprising a calibration circuit (see fig.2 element 230) configured to change the specific delay incurred by the delay circuit (see fig.2 element 270 and col.9, lines 36-44 for…. The calibration circuit 230 may further be configured to calibrate the ADC 200 by delaying at least one of the first and the second clock signal 260-1, 260-2 based on the first and the second mismatch, e.g., by controlling the delay circuit 270 accordingly.).
It would have obvious to one of ordinary skill in the art, at the time of filing or before the effective filing date of the claimed invention, to modify Moehlmann et al and Bereza to include a calibration circuit configured to change the specific delay incurred by the delay circuit in order to achieve acquisition and recover the data and clock signal. The predetermined prescaler value stored in the predetermined prescaler value unit would be preprogrammed so that first clock synchronize with the second clock in term of phase and frequency. Furthermore the delay circuit would facilitate the plurality of devices to obtain equally spaced alignment of the phases, as spaced according to the number of buffers used. Such modification would enhance the multi-channel devices in determining a level of performance through a variety of performance measures or criterion, such as bit error rate performance, and subsequently achieve the highest timing acquisition during the phase alignment.
As per claim 14, Moehlmann et al, Bereza and Kundu in combination would teach wherein the calibration circuit (See Kundu fig.2 element 230) includes a controller (see Kundu fig.2 element 236) configured to set the specific delay based on measurements on outputs of the devices (see Kundu elements 210s and col.8, lines 10-15 for…. The calibration circuit 230 further comprises a second logical circuit 236 …..the first logical circuit 232 may process a signal received from the sub-ADCs 210 or the detection circuit 220, upstream to the second logical circuit 236.) and) in order to achieve acquisition and recover the data and clock signal. The predetermined prescaler value stored in the predetermined prescaler value unit would be preprogrammed so that first clock synchronize with the second clock in term of phase and frequency. Furthermore the delay circuit would facilitate the plurality of devices to obtain equally spaced alignment of the phases, as spaced according to the number of buffers used. Such modification would enhance the multi-channel devices in determining a level of performance through a variety of performance measures or criterion, such as bit error rate performance, and subsequently achieve the highest timing acquisition during the phase alignment.
As per claim 15, Moehlmann et al, Bereza and Kundu in combination would teach, wherein the calibration circuit (See Kundu fig.2 element 230) includes a controller (see Kundu element 236) configured to set the specific delay based on spectrum analysis (see Kundu element 220 and col.9, lines 25-30 for….. The ring oscillator 250 may, for example, generate the calibration clock signal such that a frequency of the calibration signal and/or the second calibration signal is uncorrelated to the frequency of the first and second clock signal 260-1, 260-2 (irrational f.sub.in/f.sub.s). The calibration clock signal may be input to the bias node 245 of the input buffer circuit 240 to support foreground calibration or to the detection circuit 220 to support background calibration.) on outputs of the devices (see Kundu elements 210s) in order to achieve acquisition and recover the data and clock signal. The predetermined prescaler value stored in the predetermined prescaler value unit would be preprogrammed so that first clock synchronize with the second clock in term of phase and frequency. Furthermore the delay circuit would facilitate the plurality of devices to obtain equally spaced alignment of the phases, as spaced according to the number of buffers used. Such modification would enhance the multi-channel devices in determining a level of performance through a variety of performance measures or criterion, such as bit error rate performance, and subsequently achieve the highest timing acquisition during the phase alignment.
-----Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moehlmann et al (US 20220365173 A1) in view of Bereza et al (US 20080298476 A1) and in further view of DOROSENCO et al (US 20210044472 A1).
As per claim 24, Moehlmann et al and Bereza in combination do not teach a non-transitory machine-readable medium including code, when executed, to cause a machine to perform the method of claim.
DOROSENCO et al teaches a non-transitory machine-readable medium including code, when executed, to cause a machine (see para [0059] for…If implemented in firmware and/or software, the functions performed may be stored as one or more instructions or code on a non-transitory computer-readable storage medium. Examples of storage media include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program).
It would have obvious to one of ordinary skill in the art, at the time of filing or before the effective filing date of the claimed invention, to modify Moehlmann and Bereza to include a non-transitory machine-readable medium including code in order to store desired program code in the form of instructions or data structures, achieve acquisition and recover the data and clock signal. Furthermore the delay circuit would facilitate the plurality of devices to obtain equally spaced alignment of the phases, as spaced according to the number of buffers used. Such modification would enhance the multi-channel devices in determining a level of performance through a variety of performance measures or criterion, such as bit error rate performance, and subsequently achieve the highest timing acquisition during the phase alignment.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20190103956 A1 or US 20120076176 A1 or US 20120195400 A1 or US 11469765 B1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMMANUEL BAYARD whose telephone number is (571)272-3016. The examiner can normally be reached 6-9.
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/EMMANUEL BAYARD/Primary Examiner, Art Unit 2633