DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 12, 2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5, 7-9, 12, 21-26, 29-31, 33-34 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Yokoyama (US 2007/0129041) in view of Alpman (US 10,111,173).
As to claim 1, Yokoyama discloses a wireless receiver comprising: a mixer 3 (see at least figure 2); a filter 6B (see figure 2) that is coupled to an output of the mixer 3 and that includes switching circuitry (see paragraphs [0065], [0066]).
Yokoyama fails to disclose that the mixer 3 includes a first transistor having a first gate terminal and that includes a second transistor having a second gate terminal; wherein the filter 6B includes a first capacitor coupled between a first output terminal of the mixer and a second output terminal of the mixer, the first transistor is coupled between an input of the mixer and the first output terminal, and the second transistor is coupled between the input of the mixer and the second output terminal. Alpman discloses a mixer 702 (see at least figure 7) that includes a first transistor MN1 having a first gate terminal and that includes a second transistor MN2 having a second gate terminal; a first capacitor C3 coupled between a first output terminal of the mixer 702 and a second output terminal of the mixer 702; wherein the first transistor MN1 is coupled between an input of the mixer 702 and the first output terminal, and the second transistor MN2 is coupled between the input of the mixer 702 and the second output terminal. Therefore, it would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to provide the above teaching of Alpman to Yokoyama, in order to yield predictable results such as better DC signal isolation, and lowering cost of the mixer.
As to claim 2, the combination of Yokoyama and Alpman discloses the switching circuitry having a plurality of states selectable based on a control signal (see Yokoyama, paragraphs [0065], [0066]); wherein the wireless receiver further comprising clocking circuitry 4 (see Yokoyama, figure 2) configured to provide a first clocking signal to the first gate terminal (see the gate terminal of the first transistor MN1 in figure 7 of Alpman), to provide a second clocking signal to the second gate terminal (see the gate terminal of the second transistor MN2 in figure 7 of Alpman), and to synchronize the control signal with the first and second clocking signal (see Yokoyama, paragraphs [0065], [0066]).
As to claim 3, the combination of Yokoyama and Alpman discloses that a first clocking signal LO+ (Alpman, figure 7) has a period (inherently present in the first clocking signal LO+), and the second clocking signal LO- (Alpman, figure 7) has the period (inherently present in the clocking signal LO-), and the second clocking signal is offset in time with respect to the first clocking signal (because the first clocking signal LO+ and the second clocking signal LO- are out-of-phase).
The combination of Yokoyama and Alpman fails to disclose that the clocking circuitry 4 (see Yokoyama, figure 2) is configured to place the switching circuitry 6B in each state of the plurality of states for a duration equal to the period.
As to claim 4, the combination of Yokoyama and Alpman fails to disclose that the clocking circuitry 4 (see Yokoyama, figure 2) is configured to pulse the first clocking signal LO+ (see Alpman, figure 7) once during each state of the plurality of states and is configured to pulse the second clocking signal LO- (see Alpman, figure 7) once during each state of the plurality of states.
As to claim 5, the combination of Yokoyama and Alpman fails to disclose that the second clocking signal is offset in time with respect to the first clocking signal by half the period.
Those skilled in the art would recognize that these claimed limitations in claims 3-5 do not involve any inventive concept. They merely depend on arbitrary characteristics of the clocking circuitry 4. In addition, the specification of the instant application fails to disclose any unexpected results obtained from having characteristics of the clocking circuitry as in claims 3-5. Therefore, it would have been obvious, before the effective filling date of the claimed invention, to one of ordinary skill in the art to modify the combination of Yokoyama and Alpman as claimed, in order to yield predictable results such as providing clocking signals having characteristics as desired by the users/circuit designers.
As to claim 21, the combination of Yokoyama and Alpman discloses that the second clocking signal is offset in time with respect to the first clocking signal (because the first clocking signal LO+ and the second clocking signal LO- are out-of-phase as taught by Alpman).
As to claim 22, the combination of Yokoyama and Alpman discloses that the mixer 3 (see Yokoyama, figure 2) comprises an input coupled to a radio-frequency transmission line path (see a radio-frequency transmission line path connected between amplifier 2 and mixer 3); but fails to disclose that the mixer 3 (see Yokoyama, figure 2) comprises a passive voltage mode mixer. The examiner, however, takes Official Notice that such a passive voltage mode mixer is known in the art. Therefore, it would have been obvious, before the effective filling date of the claimed invention, to one of ordinary skill in the art to modify the combination of Yokoyama and Alpman as claimed, in order to yield predictable results such as lower noise figure, low flicker noise, and power efficiency.
As to claim 23, the combination of Yokoyama and Alpman discloses that the filter 6B (see Yokoyama, figure 2) comprises a passive switched-capacitive filter having an input coupled to the output of the mixer 3 (see paragraph [0065]); but fails to disclose that the filter 6B comprises a second-or-higher order filter. The examiner, however, takes Official Notice that such a second-or-higher order filter is known in the art. Therefore, it would have been obvious, before the effective filling date of the claimed invention, to one of ordinary skill in the art to modify the combination of Yokoyama and Alpman as claimed, in order to yield predictable results such as steeper roll-off rates, leading to more effective attenuation of unwanted frequencies compared to first-order filter.
Claims 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Yokoyama (US 2007/0129041) in view of Alpman (US 10,111,173) as applied to claim 23 above, and further in view of Mu (US 2009/0213770).
As to claim 24, the combination of Yokoyama, Alpman fails to disclose that the output of the mixer includes a first output terminal and a second output terminal, the mixer comprising: a first capacitor coupled between the first output terminal and a reference potential; and a second capacitor coupled between the second output terminal and the reference potential. Mu discloses that output of a mixer 190 (see at least figure 2) includes a first output terminal (see output terminal of TM1) and a second output terminal (see output terminal of TM2), the mixer 190 comprising: a first capacitor C1 coupled between the first output terminal and a reference potential; and a second capacitor C2 coupled between the second output terminal and the reference potential. Therefore, it would have been obvious, before the effective filling date of the claimed invention, to one of ordinary skill in the art to provide the above teaching of Mu to the combination of Yokoyama and Alpman, in order to smooth the high frequency ripples from the mixer output.
As to claim 25, the combination of Yokoyama, Alpman and Mu discloses that the second-or-higher order switched-capacitor filter comprises: a first line coupled to the first output terminal; a second line coupled to the second output terminal; and a third capacitor C3 (or C6; see Alpman, figure 7) coupled between the first line and the second line.
Claims 12, 29-31, 33-34 are rejected under 35 U.S.C. 103 as being unpatentable over Yokoyama (US 2007/0129041) in view of Alpman (US 10,111,173), and JP2016163297A (English translation also provided, hereinafter simply referred to as document’297).
As to claim 12, Yokoyama discloses a wireless receiver comprising: a mixer 3 (see at least figure 2); a filter 6B that is coupled to an output of the mixer 3. Yokoyama fails to disclose that the mixer 3 includes a first transistor having a first gate terminal and that includes a second transistor having a second gate terminal. Alpman discloses a mixer 702 (see at least figure 7) that includes a first transistor MN1 having a first gate terminal and that includes a second transistor MN2 having a second gate terminal. Therefore, it would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to provide the above teaching of Alpman to Yokoyama, in order to yield predictable results such as lowering cost of the mixer.
The combination of Yokoyama and Alpman further discloses that the filter 6B (see Yokoyama, figure 2) includes a first line coupled to a first output terminal of the mixer 3, a second line coupled to a second output terminal of the mixer 3; but fails to disclose that the filter 6B comprises a butterfly switch disposed on the first and second lines. Document’297 discloses that a filter 1 (see at least figure 1(a); paragraph [0052]) includes a butterfly switch (see paragraph [0052]). Therefore, it would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to provide the above teaching of document’297 to the above combination of Yokoyama and Alpman, in order to yield predictable results such as efficiency, and cost management.
As to claim 29, the combination of Yokoyama, Alpman, and document’297 discloses that the filter 1 (see document’297, figure 1(a)) further comprises: at least two additional butterfly switches SW1-SW4 disposed on the first and second lines.
As to claim 30, the combination of Yokoyama, Alpman, and document’297 discloses that the filter 1 (see document’297, figure 1(a)) further comprises: at least three capacitors SW1-SW4 coupled between the first and second lines.
As to claim 31, the combination of Yokoyama and Alpman discloses that the mixer is a passive mixer (see Alpman, column 9 line 35), the switching circuitry having a plurality of states selectable based on a control signal (see Yokoyama, paragraphs [0065], [0066]); wherein the wireless receiver further comprising clocking circuitry 4 (see Yokoyama, figure 2) configured to provide a first clocking signal to the first gate terminal (see the gate terminal of the first transistor MN1 in figure 7 of Alpman), to provide a second clocking signal to the second gate terminal (see the gate terminal of the second transistor MN2 in figure 7 of Alpman), and to synchronize the control signal with the first and second clocking signal (see Yokoyama, paragraphs [0065], [0066]).
As to claim 33, it is rejected for similar reasons with respect to independent claim 12 as set forth above. In addition, the combination of Yokoyama, Alpman, and document’297 discloses that the filter 6B (see Yokoyama, figure 2) includes a first line coupled to a first output terminal of the mixer 3, a second line coupled to a second output terminal of the mixer 3, a set of switches SW1-SW4 (see document’297, figure 1(a)) disposed on the first and second lines, and a set of capacitors Cs, Cp, Cl coupled between the first and second lines and interspersed with the set of switches SW1-SW4.
As to claim 34, the combination of Yokoyama and Alpman discloses that the set of switches has a plurality of states selectable based on a control signal (see Yokoyama, paragraphs [0065], [0066]); wherein the wireless receiver further comprising clocking circuitry 4 (see Yokoyama, figure 2) configured to provide a first clocking signal to the first gate terminal (see the gate terminal of the first transistor MN1 in figure 7 of Alpman), to provide a second clocking signal to the second gate terminal (see the gate terminal of the second transistor MN2 in figure 7 of Alpman), and to synchronize the control signal with the first and second clocking signal (see Yokoyama, paragraphs [0065], [0066]).
Allowable Subject Matter
Claims 7-9, 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claims 7-9, the prior art of record fail to anticipate, or render obvious, that the switching circuitry comprises: a first switch having a first terminal communicatively coupled to the first output terminal, a second terminal communicatively coupled to the second output terminal, a third terminal, and a fourth terminal; and a second switch having a fifth terminal coupled to the third terminal, a sixth terminal coupled to the fourth terminal, a seventh terminal communicatively coupled to an output of the filter, and an eighth terminal communicatively coupled to the output of the filter.
As to claim 26, the prior art of record fail to anticipate, or render obvious, that the second-or-higher order switched-capacitor filter further comprises: a first butterfly switch disposed on the first and second lines and having a first terminal coupled to the first output terminal and the third capacitor, a second terminal coupled to the second output terminal and the third capacitor, a third terminal on the first line, and a fourth terminal on the second line; a second butterfly switch disposed on the first and second lines and having a fifth terminal coupled to the third terminal, a sixth terminal coupled to the fourth terminal, a seventh terminal on the first line, and an eighth terminal on the second line; a fourth capacitor coupled between the first and second lines between the first and second butterfly switches; and a fifth capacitor coupled between the first and second lines and between the seventh and eighth terminals.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN THANH VO whose telephone number is (571)272-7901. The examiner can normally be reached Mon-Fri 8-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeanette J Parker can be reached at (571) 270-3647. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NGUYEN T VO/Primary Examiner, Art Unit 2646
Prosecution Insights