DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-3, 13 and 18-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 13 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kalifa et al. (US PG Pub 2020/0358253 A1) in view of WONG et al. (US PG Pub 2018/0241177 A1).
Regarding claim 1, Kalifa discloses a semiconductor light-emitting element (a VCSEL 100, FIG. 1A, [0019]) having a structure in which a substrate (110, FIG. 1A, [0019]), a first reflector (130, FIG. 1A, [0019]), a resonator cavity (140, FIG. 1A, [0019]) including an active layer, a second reflector (150, FIG. 1A, [0019]) and a tunnel junction portion (145, FIG. 1A, [0019]), comprising: a first current constriction portion (FIG. 1A) configured with an oxidation constriction layer (160, FIG. 1A, [0028]); and a second current constriction portion (FIG. 1A) including the tunnel junction portion, wherein a width d2 of the second current constriction portion is smaller than a width d1 of the first current constriction portion (d2<d1, FIG. 1A, see annotated FIG. 1A below).
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Kalifa does not disclose the stacking sequence that the tunnel junction portion is on the second reflector.
WONG discloses a semiconductor light-emitting element (a VCSEL 40, FIG. 3, [0029]) having a structure in which a substrate (42, FIG. 3, [0029]), a first reflector (44, FIG. 3, [0029]), a resonator cavity (48, FIG. 3, [0029]) including an active layer, a second reflector (46, FIG. 3, [0029]) and a tunnel junction portion (49, FIG. 3, [0030]) are stacked in this sequence (“A tunnel junction 49 may be formed on the DBR 46,” [0031]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the VCSEL of Kalifa with placing the tunnel junction on the second reflector forming the claimed stacking sequence as taught by WONG in order to obtain desired current confinement effect.
Regarding claim 2, Kalifa, as modified, discloses the tunnel junction portion is disposed on a part of an upper face of the second reflector (“A tunnel junction 49 may be formed on the DBR 46,” [0031] of WONG), and wherein a width of the tunnel junction portion is the width d2 of the second current constriction portion (d2, see annotated FIG. 1A of above).
Regarding claim 3, Kalifa discloses the tunnel junction portion is included in a non-oxidized portion on the inner side of the oxidation constriction layer in the first current constriction portion in the planar view (d2 is fully overlapped with d1 vertically, see annotated FIG. 1A of above).
Regarding claim 13, the combination has disclosed the semiconductor light-emitting element outlined in the rejection to claim 2 above except the width d1 of the first current constriction portion satisfies 30 μm≤d1≤70 μm. However, it’s known in the art that a size of an oxide aperture determines an output power and an output mode of a VCSEL. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to optimize d1 of the combination with 30 μm≤d1≤70 μm in order to obtain desired output power and output mode, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 MPEP 2144.05 (II-A)
Regarding claim 18, Kalifa discloses the second reflector is a p-type semiconductor ([0023]).
Regarding claim 19, the combination has disclosed the semiconductor light-emitting element outlined in the rejection to claim 1 above except the thickness t of the tunnel junction portion satisfies 10 nm≤t≤440 nm. However, it’s known in the art that a tunnel junction layer requires to have a sufficient thickness to improve the reliability and stability of the tunnel junction. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to optimize the thickness t of the tunnel junction portion of the combination with 10 nm≤t≤440 nm in order to improve the reliability and stability of the tunnel junction, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 MPEP 2144.05 (II-A)
Regarding claim 20, the combination has disclosed the semiconductor light-emitting element outlined in the rejection to claim 1 above except a light-emitting device comprising a plurality of the semiconductor light-emitting elements. However, it’s known in the art that a laser array outputs a higher power. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to duplicate the semiconductor light-emitting element to form an array in order to obtain desired output power, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Kalifa et al. and WONG et al. as applied to claim 1 above, and further in view of WO 2019087524A1 (hereafter WO’524).
Regarding claim 21, the combination has disclosed the semiconductor light-emitting element outlined in the rejection to claim 1 above except a ranging device comprising: a sensor that detects reflected light of light generated by the light source; and a processing unit that acquires distance information based on a detection timing to detect the reflected light. WO’524 discloses a ranging device (500, FIG. 15) comprising: a light source (501, FIG. 15) including a semiconductor light-emitting element; a sensor (502, FIG. 15) that detects reflected light of light generated by the light source; and a processing unit (507, FIG. 15) that acquires distance information based on a detection timing to detect the reflected light. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor light-emitting element of the combination with the range device comprising the sensor and the processing unit as taught by WO’524 in order to obtain desired LIDAR application.
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUANDA ZHANG whose telephone number is (571)270-1439. The examiner can normally be reached M-F 10:30 AM - 6:30 PM.
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/YUANDA ZHANG/Primary Examiner, Art Unit 2828
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