DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figure 4 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). See page 15 lines 4-21 which discloses in part “Various known techniques may be used for the determination of denormal conditions (second denormal condition) on an expected FMA output based on input FP operands. An example of such techniques is shown in FIG. 4, wherein three mutually exclusive cases are considered for different range of d …”.
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because it contains more than 150 words or more than 15 lines of text. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Objections
Claims 14-19 are objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected.
A. In claim 14 line 19, “executing a denormal handling instruction:” should read “executing a denormal handling instruction to:” instead for better clarity. Claims 15-19 inherit the same deficiency as claim 14 by reason of dependence.
Claim Interpretation
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B. See MPEP 2111.04, II for more information.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “said instruction decoder” in line 6. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this is interpreted as “said instruction decode circuitry” instead. Claims 14 and 20 recite a similar limitation and are rejected for the same reason. Claims 2-13 inherit the same deficiency as claim 1 by reason of dependence. Claims 15-19 inherit the same deficiency as claim 14 by reason of dependence.
Claim 6 recites “the sum” in line 6. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this is interpreted as “a sum” instead.
Claim 6 recites “based on of” in line 13. This limitation is unclear because it is grammatically incorrect and there appears to be missing limitations between the words “on” and “of”. For purposes of examination, this is interpreted as “based on the sum of” based on the reference to ea + eb in the next line.
Claim 7 recites “an "ldexp" operation” in line 15. It is unclear what the word “ldexp” means, therefore, it is unclear how “ldexp” is supposed to be interpreted. Further, clarification is required. For purposes of examination, any operation that generates a shifted first, second or third floating-point operand is an "ldexp" operation. Claim 18 recites a similar limitation and is rejected for the same reason.
Claim 14 recites “A computer-implemented method comprising: instruction decode circuitry decoding instructions; processing circuitry executing said instructions decoded by said instruction decode circuitry, said processing circuitry comprising fused-multiply-accumulate, FMA, circuitry to respond to a fused-multiply-accumulate, FMA, instruction decoded by said instruction decoder, said FMA instruction specifying a first floating-point operand (a), a second floating-point operand (b) and a third floating-point operand (c); and an operand storage module storing said first floating-point operand, said second floating-point operand, and said third floating-point operand, the method further comprising …”. This limitation is unclear because a process claim is a series of acts or steps. See MPEP 2106.03, I. However, the claim recites that the method comprises circuitry and modules in such a way consistent with a machine type claim instead of the steps of the method. For purposes of examination, this is interpreted as “A computer-implemented method performed by a data processing apparatus, the data processing apparatus comprising: instruction decode circuitry decoding instructions; processing circuitry executing said instructions decoded by said instruction decode circuitry, said processing circuitry comprising fused-multiply-accumulate, FMA, circuitry to respond to a fused-multiply-accumulate, FMA, instruction decoded by said instruction decoder, said FMA instruction specifying a first floating-point operand (a), a second floating-point operand (b) and a third floating-point operand (c); and an operand storage module storing said first floating-point operand, said second floating-point operand, and said third floating-point operand, the method comprising: …” instead. Claims 15-19 inherit the same deficiency as claim 14 by reason of dependence.
Claim 19 recites “said third integer” in line 6. There is insufficient antecedent basis for this limitation in the claim. A third integer is recited in claim 18, however, claim 19 does not depend on claim 18. For purposes of examination, claim 19 is interpreted to depend on claim 18 instead.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lutz et al. (US 20150199173 A1), hereinafter Lutz, in view of Trong et al. (US 20060184601 A1), hereinafter Trong, and Rubanovich et al. (US 20180088940 A1), hereinafter Rubanovich.
Regarding claim 14, Lutz teaches a computer-implemented method comprising:
processing circuitry executing said instructions (Lutz Figs. 1-4 and paragraphs [0027, 0039, 0041, 0045] processing circuitry – FP pipeline 18/ multiply add circuitry 24; fused-multiply-accumulate, FMA, circuitry - multiply add circuitry 24; a – B; b- C; c – A); and
the method further comprising,
responsive to said FMA instruction, said FMA circuitry:
performing denormal detection on said first floating-point operand, said second floating-point operand (Lutz Figs. 3, 5 and paragraph [0043] first denormal condition – whether B or C is a subnormal number (CLZ > 0));
(This is a contingent limitation that is not required to be performed if the none of the operands meets the first denormal condition):
(This is a contingent limitation that is not required to be performed if the none of the operands meets the first denormal condition);
(This is a contingent limitation that is not required to be performed if the none of the operands meets the first denormal condition); and
(This is a contingent limitation that is not required to be performed if the none of the operands meets the first denormal condition).
Lutz does not explicitly teach instruction decode circuitry decoding instructions; processing circuitry executing said instructions decoded by said instruction decode circuitry, said processing circuitry comprising fused-multiply-accumulate, FMA, circuitry to respond to a fused-multiply-accumulate, FMA, instruction decoded by said instruction decoder; an operand storage module storing said first floating-point operand, said second floating-point operand, and said third floating-point operand; and performing denormal detection on said first floating-point operand, said second floating-point operand and said third floating-point operand to determine if one or more of said first floating-point operand, said second floating-point operand or said third floating-point operand meets a first denormal condition.
However, on the same field of endeavor, Trong discloses performing denormal detection on a third floating-point operand of a fused multiply-add operation to determine if the third floating-point operand meets a first denormal condition (Trong Fig. 3; abstract and paragraphs [0048, 0053] third floating-point operand – addend operand b).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Lutz using Trong and configure the FMA circuitry to also perform denormal detection on the third floating-point operand A in addition to performing denormal detection on the first floating-point operand B and the second floating-point operand V to determine if one or more of said first floating-point operand, said second floating-point operand or said third floating-point operand meets a first denormal condition in order to provide a Floating Point Unit with fused multiply add capable of handling denormal multiplicand and addend operands (Trong paragraph [0001, 0004, 0042, 0048]).
Therefore, the combination of Lutz as modified in view of Trong teaches performing denormal detection on said first floating-point operand, said second floating-point operand and said third floating-point operand to determine if one or more of said first floating-point operand, said second floating-point operand or said third floating-point operand meets a first denormal condition.
Lutz as modified in view of Trong does not explicitly teach instruction decode circuitry decoding instructions; processing circuitry executing said instructions decoded by said instruction decode circuitry, said processing circuitry comprising fused-multiply-accumulate, FMA, circuitry to respond to a fused-multiply-accumulate, FMA, instruction decoded by said instruction decoder; an operand storage module storing said first floating-point operand, said second floating-point operand, and said third floating-point operand.
However, on the same field of endeavor, Rubanovich discloses instruction decode circuitry decoding instructions; processing circuitry executing said instructions decoded by said instruction decode circuitry; and an operand storage module storing operands (Rubanovich abstract; Figs. 1A-2, 4A-4B; paragraphs [0064, 0067, 0070, 0083-0084; instruction decode circuitry – decoder; operand storage module – register file).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Lutz using Rubanovich and include an instruction decode circuitry decoding instructions; and an operand storage module for storing the operands for the FMA instruction as these steps are normally part of a processor pipeline (Rubanovich paragraph [0064, 0080] and Figs. 2 and 4A-4B). Furthermore, one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. The predictable result is a processor pipeline including instruction decode circuitry decoding instructions; processing circuitry executing said instructions; and an operand storage module for storing instruction operands. See also MPEP 2141, III(A).
Therefore, the combination of Lutz as modified in view of Trong and Rubanovich teaches instruction decode circuitry decoding instructions; processing circuitry executing said instructions decoded by said instruction decode circuitry, said processing circuitry comprising fused-multiply-accumulate, FMA, circuitry to respond to a fused-multiply-accumulate, FMA, instruction decoded by said instruction decoder; an operand storage module storing said first floating-point operand, said second floating-point operand, and said third floating-point operand.
Regarding claim 15, Lutz as modified in view of Trong and Rubanovich teaches all the limitations of claim 14 as stated above. Further, Lutz as modified in view of Trong and Rubanovich teaches further comprising said FMA circuitry, upon determining that none of said first floating-point operand, said second floating- point operand, and said third floating-point operand meets said first denormal condition, executing said FMA instruction using said first floating-point operand, said second floating-point operand, and said third floating-point operand to generate an FMA output (Lutz Figs. 2-5 and paragraphs [0044, 0049, 0054]; Trong Fig. 3).
Regarding claim 18, Lutz as modified in view of Trong and Rubanovich teaches all the limitations of claim 14 as stated above. Further, Lutz as modified in view of Trong and Rubanovich teaches (This is a contingent limitation that is not required to be performed if the none of the operands meets the first denormal condition):
(This is a contingent limitation that is not required to be performed if the none of the operands meets the first denormal condition);
(This is a contingent limitation that is not required to be performed if the none of the operands meets the first denormal condition);
(This is a contingent limitation that is not required to be performed if the none of the operands meets the first denormal condition),
(This limitation is further limiting a contingent limitation that is not required to be performed if the none of the operands meets the first denormal condition),
(This limitation is further limiting a contingent limitation that is not required to be performed if the none of the operands meets the first denormal condition).
Claims 16-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lutz in view of Trong and Rubanovich as applied to claim 14 above, and further in view of Drane (US 20230205489 A1).
Regarding claim 16, Lutz as modified in view of Trong and Rubanovich teaches all the limitations of claim 14 as stated above.
Lutz does not explicitly teach further comprising said FMA circuitry performing said denormal detection on said first floating-point operand, said second floating- point operand and said third floating-point operand to determine if an expected FMA output based on said first floating-point operand, said second floating-point operand and said third floating-point operand meets a second denormal condition.
However, on the same field of endeavor, Drane discloses determining if an expected FMA output based on a first floating-point operand, a second floating-point operand and a third floating-point operand meets a second denormal condition (Drane Figs. 28, 31 and paragraphs [0379-3288, 0399-0401] second denormal condition – at least case A or B).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Lutz using Drane and determine if an expected FMA output based on the first floating-point operand, the second floating-point operand and the third floating-point operand meets a second denormal condition in order to optimize and/or simplify the FMA calculation by (Drane paragraph [0372, 0399-0401]).
Therefore, the combination of Lutz as modified in view of Trong, Rubanovich and Drane teaches further comprising said FMA circuitry performing said denormal detection on said first floating-point operand, said second floating- point operand and said third floating-point operand to determine if an expected FMA output based on said first floating-point operand, said second floating-point operand and said third floating-point operand meets a second denormal condition.
Regarding claim 17, Lutz as modified in view of Trong, Rubanovich and Drane teaches all the limitations of claim 16 as stated above. Further, Lutz as modified in view of Trong, Rubanovich and Drane teaches further comprising said FMA circuitry: upon determining that said FMA output meets said second denormal condition, executing said denormal handling instruction (This is a contingent limitation that is not required to be performed if the second denormal condition is not met); or
upon determining that said expected FMA output does not meet said second denormal condition, omit said denormal handling instruction and execute said FMA instruction using said first floating-point operand, said second floating-point operand, and said third floating-point operand to generate an FMA output (Drane Fig. 33 step 3320 and paragraph [0406]). The motivation to combine is the same as claim 16.
Regarding claim 19, Lutz as modified in view of Trong, Rubanovich and Drane teaches all the limitations of claim 17 as stated above. Further, Lutz as modified in view of Trong, Rubanovich and Drane teaches wherein said FMA circuitry executes said denormal handling instruction by: writing said shifted FMA output to said auxiliary storage of said operand storage module; and generating an FMA output based on said shifted FMA output by subtracting said third integer from an exponent of said shifted FMA output (This limitation is further limiting a contingent limitation that is not required to be performed if the first denormal condition and/or the second denormal condition is not met).
Allowable Subject Matter
Claims 1-13 and 20 would be allowable if rewritten to overcome the 35 U.S.C. 112(b) rejection discussed above.
The following is a statement of reasons for the indication of allowable subject matter:
None of the prior art references cited explicitly teach or suggest the features of upon determining that at least one of said first floating-point operand, said second floating-point operand or said third floating-point operand meets said first denormal condition, executing a denormal handling instruction to: generate a shifted first floating-point operand (ta) based on said first floating-point operand, a shifted second floating-point operand (tb) based on said second floating-point operand, and a shifted third floating-point operand (tc) based on said third floating-point operand; write said shifted first floating-point operand, said shifted second floating- point operand and said shifted third floating-point operand to auxiliary storage of said operand storage module, said auxiliary storage being temporary storage configured within said operand storage module and assigned to said denormal handling instruction; and execute said FMA instruction using said shifted first floating-point operand, said shifted second floating-point operand and said shifted third floating-point operand to generate a shifted FMA output as recited in claims 1 and 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Goveas et al. (US 20140136587 A1), Elmer (US 20180095749 A1) and Green et al. (US 6801924 B1) generally related to a floating point multiply-add unit supporting denormal numbers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
Prosecution Insights