DETAILED ACTION
Status of Application
Claims 1-23 are pending in the present application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 7, 9-10, 12-13, and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hughes et al (hereinafter Hughes), US 10572260 B2, in view of Vasudevan et al (hereinafter Vasudevan), US 20210049102 A1, and further in view of Saripalli, US 20110252168 A1.
Referring to claims 1, 12, and 18, taking claim 1 as exemplary, Hughes discloses an apparatus comprising:
a clustered processing architecture including a plurality of clusters [fig. 2, core cluster 202; fig. 3, clusters 374], each of the clusters including one or more processing resources and a cache [fig. 2, see processing resources and cache 208]; and
one or more memory elements [fig. 2, element 214], including a first memory element containing a home agent [fig. 2, HA 222], wherein the apparatus is to:
receive, at a first caching agent [fig. 3, see 399 which is part of cluster 374 (see 399A)] for a first cluster of the plurality of clusters, a request for performance of an atomic operation [col. 17, lines 57-59, “processing a received remote atomic operation instruction, according to some embodiments. After starting, at 502, enqueue circuitry receives an instruction comprising an opcode, a destination identifier, and source data”], the atomic operation requiring a data stored in a cacheline at a memory address associated with the home agent [col. 17, lines 34-41, “Each queue entry includes an RAO instruction addressed to a particular cache line element. In some embodiments, each element includes a memory address”].
Hughes does not explicitly disclose evaluate one or more factors regarding atomic performance, the one or factors including a current ownership of the memory address.
However, Vasudevan discloses evaluate one or more factors regarding atomic performance, the one or factors including a current ownership of the memory address [paragraph 41, “Home agent 202 may include or have access to a directory that tracks ownership and/or status of each cache line”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Vasudevan in the apparatus of Hughes to implement, evaluate one or more factors regarding atomic performance, the one or factors including a current ownership of the memory address, in order to address performance limiting issues, high energy consumption worries, and other bottlenecks [Vasudevan, paragraph3].
The modified Hughes does not explicitly disclose based at least in part on the one or more factors, determine whether to perform the atomic operation at the first caching agent or to forward the atomic operation to the home agent for performance of the atomic operation.
However, Saripalli discloses based at least in part on the one or more factors, determine whether to perform the atomic operation at the first caching agent or to forward the atomic operation to the home agent for performance of the atomic operation [paragraph 31, “forward the request onto an owner of the requested memory location to enable the operation to be directly performed locally to the memory location (i.e., by the owner agent of the memory)”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Saripalli in the apparatus of the modified Hughes to implement, based at least in part on the one or more factors, determine whether to perform the atomic operation at the first caching agent or to forward the atomic operation to the home agent for performance of the atomic operation, in order to avoid non-deterministic behavior and reduced latency [Saripalli, paragraph 31].
Referring to claims 2, 13, and 19, taking claim 2 as exemplary, the modified Hughes discloses the apparatus of claim 1, wherein determining whether to perform the atomic operation at the first caching agent or to forward the atomic operation to the home agent includes:
determining whether the data is cached in the first cache [Vasudevan, paragraph 41, “Home agent 202 may include or have access to a directory that tracks ownership and/or status of each cache line”]; and
upon determining that the data is not cached in the first cache, forwarding the atomic operation to the home agent [Vasudevan, paragraph 50, “The consumer 610 desires to obtain a copy of this cache line and therefore issues a read request 622. Since consumer's local cache 608 does not contain a copy of the cache line, the read request results in a miss 624 which is then forwarded to the home agent 606”].
Referring to claim 7, the modified Hughes discloses wherein, upon determining to perform the atomic operation at the home agent and further determining that current ownership of the memory address is with a cluster of the plurality of clusters, the home agent is to acquire ownership of the memory address to perform the atomic operation [Vasudevan, paragraph 73, “Home agent 1206 may determine from a director that producer's local cache 1204 is the exclusive owner of the cache line. A request for the cache line is then sent to and received by the producer's local cache 1204 via a snoop 1252. Responding to the request, the producer's local cache 1204 includes a copy of the request cache line with a response message 1254 back to the home agent. The copy of the cache line 1222 in the producer's local cache is marked as shared (S)”].
Referring to claim 9, the modified Hughes discloses the apparatus of claim 1, wherein the one or more processing resources include one or more graphics processing resources [Hughes, col. 31, lines 8-18].
Referring to claim 10, the modified Hughes discloses the apparatus of claim 1, wherein the atomic operation is a read-modify-write operation [Hughes, col. 3, lines 66-67].
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hughes, in view of Vasudevan, in view of Saripalli, as applied to claim 1 above, and further in view of Mola, US 20180203780 A1.
Referring to claim 8, the modified Hughes does not explicitly disclose the apparatus of claim 1, wherein the one or more factors include: a statistic describing performance of operations at the memory address.
However, Mola discloses wherein the one or more factors include: a statistic describing performance of operations at the memory address [paragraph 55, monitoring operations(s) in block 406, in block 407 the cache management component 304 evicts the imported cache line in the cache 203 upon notification to do so from the breakpoint component 302. Notably, the imported cache line is removed from the cache 203 whether or not a breakpoint was actually encountered (as determined by the monitoring operation(s) in block 406). This is because the replay component 300 ensures that any cache line that overlaps with any watched-for memory address is evicted from the cache, so that a breakpoint check for each watched-for memory address is performed every time there is a cache miss that overlaps with a watched-for memory address].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Mola in the apparatus of the modified Hughes to implement, wherein the one or more factors include: a statistic describing performance of operations at the memory address, in order to greatly reduce overhead [Mola, paragraph 6].
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hughes, in view of Vasudevan, in view of Saripalli, as applied to claim 1 above, and further in view of Windh et al (hereinafter Windh), US 20220206846 A1.
Referring to claim 11, the modified Hughes does not explicitly disclose the apparatus of claim 1, wherein the apparatus includes a plurality of processor chiplets, a plurality of memory chiplets, and an interconnect between the processor chiplets and the memory chiplets.
However, Windh discloses wherein the apparatus includes a plurality of processor chiplets, a plurality of memory chiplets, and an interconnect between the processor chiplets and the memory chiplets [paragraph 127].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Windh in the apparatus of the modified Hughes to implement, wherein the apparatus includes a plurality of processor chiplets, a plurality of memory chiplets, and an interconnect between the processor chiplets and the memory chiplets, in order to provide an efficient mechanism to process large tasks in parallel [Windh, paragraph 28].
Allowable Subject Matter
Claims 3-6, 14-17, and 20-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein determining whether to perform the atomic operation at the first caching agent or to forward the atomic operation to the home agent further includes: upon determining that the data is cached in the first cache, determining a state of the cacheline in the first cache; and performing the atomic operation at the first cache or forwarding the atomic operation to the home agent based at least in part on the determined state of the cacheline, in combination with other recited limitations in claim 3.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein, upon forwarding the atomic operation to the home agent, the apparatus further to: evaluate the one or more factors regarding processing of atomic operations; and based at least in part on the evaluation of the one or more factors, determine whether to perform the atomic operation at the home agent or to forward the atomic operation to a selected caching agent of one of the clusters for performance of the atomic operation on behalf of the home agent, in combination with other recited limitations in claim 5.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein determining whether to perform the atomic operation at the first caching agent or to forward the atomic operation to the home agent further includes: upon determining that the data is cached in the first cache, determining a state of the cacheline in the first cache; and performing the atomic operation at the first cache or forwarding the atomic operation to the home agent based at least in part on the determined state of the cacheline, in combination with other recited limitations in claim 14.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest upon forwarding the atomic operation to the home agent, evaluating the one or more factors regarding processing of atomic operations; and based at least in part on the evaluation of the one or more factors, determining whether to perform the atomic operation at the home agent or to forward the atomic operation to a selected caching agent of one of the clusters for performance of the atomic operation on behalf of the home agent, in combination with other recited limitations in claim 16.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein determining whether to perform the atomic operation at the first caching agent or to forward the atomic operation to the home agent further includes: upon determining that the data is cached in the first cache, determining a state of the cacheline in the first cache; and performing the atomic operation at the first cache or forwarding the atomic operation to the home agent based at least in part on the determined state of the cacheline, in combination with other recited limitations in claim 20.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest upon forwarding the atomic operation to the home agent, evaluating the one or more factors regarding processing of atomic operations; and based at least in part on the evaluation of the one or more factors, determining whether to perform the atomic operation at the home agent or to forward the atomic operation to a selected caching agent of one of the clusters for performance of the atomic operation on behalf of the home agent, in combination with other recited limitations in claim 22.
Claims 4, 6, 15, 17, 21, and 23 are objected to by virtue of their dependency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Menhusen, US 11874767 B2, discloses wherein each processing entity of the plurality of processing entities has exclusive ownership of a corresponding memory partition of the plurality of memory partitions of the shared memory address space [claim 1].
Chamberlain et al, US 20150178206 A1, discloses etecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M') state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache [Abstract].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARLEY J ABAD whose telephone number is (571)270-3425. The examiner can normally be reached Mon-Fri 8:30 AM - 7 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Farley Abad/Primary Examiner, Art Unit 2181