Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I drawn to claims 1-13 in the reply filed on December 29, 2025 is acknowledged.
Claim Interpretation
Examiner notes that a “dummy region” and “dummy gate region” cited in claims 5 and 12 respectfully are interpreted as regions of the device wherein no active gate is present.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 9 recites the limitation "the VBPR S/D metal". There is insufficient antecedent basis for this limitation in the claim. Examiner notes that claim 3 cites a VBPR S/D metal contact which is interpreted to correspond to VBPR1 shown in Fig. 18 of the instant application. Claim 9 cites that “the VBPR S/D metal contacts another portion of the at least two portions of the BSPR.”
For examination purposes, “the VBPR S/D metal” is interpreted to be the metallization layer which includes the VPBR S/D metal contact cited in claim 3.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li (US 20220293513 A1).
Regarding Claim 1, Li teaches a semiconductor device (400, shown fig. 4), comprising:
a backside power rail (BSPR) (portions 446, 448 and 449, see [0061]);
a source-drain (S/D) region (see S/D regions of transistor 460 annotated below) connected to the BSPR (shown Fig. 4 being electrically connected); and
a metal-insulator-metal capacitor (MIMC) (450, see [0061]),
wherein the BSPR directly connects to the MIMC by a MIMC via for backside power rail (VBPR) metal contact (see via directly connecting upper electrode 454 to backside power rail portions 446 and 449).
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Regarding Claim 2, Li teaches the semiconductor device of claim 1, wherein the MIMC VBPR contact is connected to at least one electrode of the MIMC (shown Fig. 4).
Regarding Claim 3, Li teaches the semiconductor device of claim 2, wherein the source-drain region is connected to the BSPR by a VBPR S/D metal contact (shown in Fig. 4, see metal portions connected to BPR 475).
Regarding Claim 4, Li teaches the semiconductor device of claim 3, wherein the source-drain region is directly connected to the BSPR by the VBPR S/D metal contact (shown Fig. 4 being in direct electrical connection).
Regarding Claim 5, Li teaches the semiconductor device of claim 4, wherein the MIMC is in a dummy region (interpreted as a region of the device wherein no active gate is present) of the semiconductor device (shown Fig. 4).
Regarding Claim 6, Li teaches the semiconductor device of claim 5, further comprising:
a back-side power distribution network (BSPDN) (470, a power management IC, see also [0058]) directly connected with the BSPR (shown Fig. 4).
Regarding Claim 7, Li teaches the semiconductor device of claim 6, further comprising:
a middle-end-of-the-line (MOL) region (region vertically between the capacitors and transistors, shown Fig. 4) including a plurality of metal contacts (shown Fig. 4, see metallization under BPR portions 475), wherein at least one electrode (lower electrode 452) of the MIMC is directly coupled (interpreted as a direct electrical coupling) to at least one of the plurality of metal contacts of the MOL region (shown Fig. 4).
Regarding Claim 8, Li teaches the semiconductor device of claim 7, wherein the at least one MIMC electrode connected to the MIMC VBPR contact (upper electrode 454) is distinct from the at least one electrode of the MIMC connected the at least one of the plurality of metal contacts of the MOL region (lower electrode 452).
Regarding Claim 9, Li teaches the semiconductor device of claim 6, wherein:
the BSPR includes at least two portions (shown Fig. 4, corresponding to portions 446, 448 and 449);
the MIMC VBPR contacts at least one of the at least two portions of the BSPR (shown in electrical contact in Fig. 4); and
the VBPR S/D metal (interpreted as being the same metal layer as the VBPR S/D contact cited in claim 3) contacts another portion of the at least two portions of the BSPR (shown, wherein a separate VPBR S/D metal portion is shown contact a second portion 449 in Fig. 4).
Regarding Claim 10, Li teaches a semiconductor device (400, shown Fig. 4), comprising:
a back-end-of-the-line (BEOL) region (440);
a front-end-of-the-line (FEOL) region (420);
a backside power distribution network (BSPDN) (470); and
a metal-insulator-metal (MIM) capacitor (450) connected to both the BEOL region and the BSPDN region (shown Fig. 4), wherein the MIM capacitor is directly connected to a via-buried-power-rail (VBPR) (446, 448 and 449) that in turn directly connects to the BSPDN (shown Fig. 4).
Regarding Claim 11, Li teaches the semiconductor device of claim 10, wherein the MIM capacitor is located in a distinct region (region 440, shown Fig. 4) of the semiconductor device than a region of the semiconductor device including one or more transistor devices (region 420, shown Fig. 4).
Regarding Claim 12, Li teaches the semiconductor device of claim 10, wherein the MIM capacitor is located in a dummy gate region (region 440 comprises no active gates) of the semiconductor device (shown Fig. 4).
Regarding Claim 13, Li teaches the semiconductor device of claim 12, wherein the dummy gate region does not include a dummy gate.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
LaJoie (US 20210408002 A1) teaches a device comprising a transistor layer (1004) and a capacitor layer (1000), wherein an electrode of a MIM capacitor is electrically coupled to a drain electrode of a transistor.
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/C.P.B./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893