Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment to claims 1, 2, 7, 9 and 10 submitted on April 29, 2026 are acknowledged and have since been entered.
Claim Interpretation
Examiner notes that a “dummy region” and “dummy gate region” cited in claims 5 and 12 respectfully are interpreted as regions of the device wherein no active gate is present.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li (US 20220293513 A1).
Regarding Claim 1, Li teaches a semiconductor device (600, shown fig. 6), comprising:
a backside power rail (BSPR) (portions 646, 648 and 649, see [0071]);
a source-drain (S/D) region (see S/D regions of transistor 660 annotated below) connected to the BSPR (shown Fig. 6 being electrically connected); and
a metal-insulator-metal capacitor (MIMC) (650, see [0071]),
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and a MIMC via backside power rail (VBPR) metal contact (metal distribution portions of layer 640, see also annotated below) comprising a first end (bottom end, see annotated) directly contacting the BSPR, a second end (upper end, see annotated), opposite the first end, directly contacting an interlayer dielectric layer, and a sidewall (see annotated) in direct contact with a sidewall of the MIMC.
Regarding Claim 2, Li teaches the semiconductor device of claim 1, wherein the sidewall of the MIMC VBPR contact is connected to at least one electrode of the MIMC (shown Fig. 6).
Regarding Claim 3, Li teaches the semiconductor device of claim 2, wherein the source-drain region is connected to the BSPR by a VBPR S/D metal contact (shown in Fig. 6, see metal portions connected to BPR 675).
Regarding Claim 4, Li teaches the semiconductor device of claim 3, wherein the source-drain region is directly connected to the BSPR by the VBPR S/D metal contact (shown Fig. 6).
Regarding Claim 5, Li teaches the semiconductor device of claim 4, wherein the MIMC is in a dummy region (interpreted as a region of the device wherein no active gate is present) of the semiconductor device (shown Fig. 6).
Regarding Claim 6, Li teaches the semiconductor device of claim 5, further comprising:
a back-side power distribution network (BSPDN) (670, a power management IC, see also [0069]) directly connected with the BSPR (shown Fig. 6).
Regarding Claim 7, Li teaches the semiconductor device of claim 6, further comprising:
a middle-end-of-the-line (MOL) region (region vertically between the capacitors and transistors, shown Fig. 6) including a plurality of metal contacts (shown Fig. 6, see metallization adjacent BPR portions 675), wherein at least one electrode (lower electrode 652) of the MIMC is directly coupled (interpreted as a direct electrical coupling) to at least one of the plurality of metal contacts of the MOL region (shown Fig. 6).
Regarding Claim 8, Li teaches the semiconductor device of claim 7, wherein the at least one MIMC electrode connected to the MIMC VBPR contact (upper electrode 656) is distinct from the at least one electrode of the MIMC connected the at least one of the plurality of metal contacts of the MOL region.
Regarding Claim 9, Li teaches the semiconductor device of claim 6, wherein:
the BSPR includes at least two portions (shown Fig. 6, corresponding to portions 646, 648 and 649);
the MIMC VBPR contacts at least one of the at least two portions of the BSPR (see annotated above); and
the VBPR S/D metal contact contacts another portion of the at least two portions of the BSPR (shown, wherein a separate VPBR S/D metal portion is shown contact a second portion 649 in Fig. 6).
Regarding Claim 10, Li teaches a semiconductor device (600, shown Fig. 6), comprising:
a back-end-of-the-line (BEOL) region (640);
a front-end-of-the-line (FEOL) region (620);
a backside power distribution network (BSPDN) (670);
a metal-insulator-metal (MIM) capacitor (650); and
a MIMC via backside power rail (VBPR) metal contact (see metal regions defined by a first end, second end and sidewall annotated below) connecting the MIMC to the BSPDN (shown Fig. 6), wherein a sidewall of the MIMC VBPR metal contact directly contacts a sidewall of the MIMC (shown Fig. 6).
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Regarding Claim 11, Li teaches the semiconductor device of claim 10, wherein the MIM capacitor is located in a distinct region (region 640, shown Fig. 6) of the semiconductor device than a region of the semiconductor device including one or more transistor devices (region 620, shown Fig. 6).
Regarding Claim 12, Li teaches the semiconductor device of claim 10, wherein the MIM capacitor is located in a dummy gate region (region 640 comprises no active gates) of the semiconductor device (shown Fig. 6).
Regarding Claim 13, Li teaches the semiconductor device of claim 12, wherein the dummy gate region does not include a dummy gate.
Response to Arguments
Applicant's arguments filed April 29, 2026 have been fully considered but they are not persuasive.
Applicant argues that Li does not disclose a semiconductor device including “a MIMC via backside power rail (VBPR) metal contact comprising a first end directly contacting the BSPR, a second end, opposite the first end, directly contacting an interlayer dielectric layer, and a sidewall in direct contact with a sidewall of the MIMC.” Examiner respectfully disagrees, and notes that the embodiment 600 of Fig. 6 disclosed by Li anticipates the claimed subject matter. See annotated figure 6 above for details.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.P.B./Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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