DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15, 18, 20, 22, and 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Otani (Pub 2017/0264469).
As to claim 15, Otani teaches a method for determining a phase noise and/or jitter of a phase locked loop (PLL)(fig 1),comprising:
generating, by a first PLL (10), a first clock signal based on a reference clock signal (11);
mixing, by a mixer (21), the first clock signal with a second clock signal (from 100, paragraph 31);
converting an output of the mixer to digital data (22);
processing the digital data to determine a phase noise or jitter of the first PLL (paragraphs 6, 7, 8, 13, 33, the phase noise detected is phase noise in the PLL as the PLL will switch LPF to determine least phase noise); and
generating an output based on the phase noise or jitter of the first PLL (paragraph 40).
As to claim 18, Otani teaches wherein the second clock signal is received from an external
clock source ((100) is external to (1)).
As to claim 20, Otani teaches combing the first and the second clock (at the mixer) to generate a third clock (paragraph 31)
As to claim 22, Otani teaches the phase noise power is integrated over a frequency range of interest to determine the jitter (paragraphs 38, 39, and 53).
As to claim 24, Otani teaches non-transitory readable medium including code when executed to cause machine to perform claim 15 (paragraph 42).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 5, 7-10, 12, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Otani in view of Sato (Pub 2011/0115467).
As to claim 1, Otani teaches a system for determining a phase noise and/or jitter of a phase locked loop (PLL)(fig 1),comprising:
a first PLL (10), a first clock signal based on a reference clock signal (11);
a mixer (21), the first clock signal with a second clock signal (from 100, paragraph 31);
an analog to digital converter (ADC)(22) configured to convert an output of the mixer to digital data)
a processing circuit (24) configured to process the digital data to determine a phase noise or jitter of the first PLL (paragraphs 6, 7, 8, 13, 33, the phase noise detected is phase noise in the PLL as the PLL will switch LPF to determine least phase noise); and generate an output based on the phase noise or jitter of the first PLL (paragraph 40).
Otani does not explicitly teach using a first buffer.
Sato teaches a PLL circuit (fig 2) in which a reference signal generator (A and C) contains a buffer (2) and output sent to a PLL circuit (B). As such it would have been obvious to a person of ordinary skill in the art before the filing date of the invention to combine the clock circuit taught in Otani with use of a buffer taught in Sato in order to use a notoriously well known in the art reference oscillator with PLL circuitry.
As to claim 2, Otani teaches wherein the second clock signal is received from an external
clock source ((100) is external to (1)). It would have been obvious to a person of ordinary skill in the art to use a PLL with a buffer as doing so would be a mere matter of design choice to choosing user desired DUT to use.
As to claim 4, Otani teaches wherein the second clock signal is received from an external
clock source ((100) is external to (1)).
As to claim 5, Otani teaches wherein the second clock signal is received from an external
clock source ((100) is external to (1)). It would have been obvious to a person of ordinary skill in the art to use a high precision clock having phase noise or jitter below a certain threshold as doing so would be a mere matter of design choice to choosing user desired DUT to use.
As to claim 7, Otani teaches a processing circuit to use digital data to determine phase noise (paragraph 33). It would be obvious to a person of ordinary skill in the art to use a fast Fourier transform as doing so would be a mere matter of design choice to using a notoriously well known in the art method of spectrum analysis of phase noise.
As to claim 8, Otani teaches the phase noise power is integrated over a frequency range of interest to determine the jitter (paragraphs 38, 39, and 53).
As to claim 9, Otani teaches a system for determining a phase noise and/or jitter of a phase locked loop (PLL)(fig 1),comprising:
a first PLL (10), a first clock signal based on a reference clock signal (11);
a mixer (21), the first clock signal with a second clock signal (from 100, paragraph 31);
an analog to digital converter (ADC)(22) configured to convert an output of the mixer to digital data)
a processing circuit (24) configured to process the digital data to determine a phase noise or jitter of the first PLL (paragraphs 6, 7, 8, 13, 33, the phase noise detected is phase noise in the PLL as the PLL will switch LPF to determine least phase noise); and generate an output based on the phase noise or jitter of the first PLL (paragraph 40).
Otani does not explicitly teach using a first buffer or a transceiver device with a plurality of transceiver units including ADC and DAC.
Sato teaches a PLL circuit (fig 2) in which a reference signal generator (A and C) contains a buffer (2) and output sent to a PLL circuit (B). Furthermore, the combined invention used with multiple transceivers is done merely as intended use to use the combined device in different circuit Applications. As such it would have been obvious to a person of ordinary skill in the art before the filing date of the invention to combine the clock circuit taught in Otani with use of a buffer taught in Sato in order to use a notoriously well known in the art reference oscillator with PLL circuitry.
As to claim 10, Otani teaches wherein the second clock signal is received from an external
clock source ((100) is external to (1)). It would have been obvious to a person of ordinary skill in the art to use a PLL with a buffer as doing so would be a mere matter of design choice to choosing user desired DUT to use.
As to claim 12, Otani teaches wherein the second clock signal is received from an external
clock source ((100) is external to (1)).
As to claim 13, Otani teaches wherein the second clock signal is received from an external
clock source ((100) is external to (1)). It would have been obvious to a person of ordinary skill in the art to use a high precision clock having phase noise or jitter below a certain threshold as doing so would be a mere matter of design choice to choosing user desired DUT to use.
Claim(s) 16, 19, 21, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Otani.
As to claim 16, Otani teaches a method for determining a phase noise and/or jitter of a phase locked loop (PLL)(fig 1),comprising:
generating, by a first PLL (10), a first clock signal based on a reference clock signal (11);
mixing, by a mixer (21), the first clock signal with a second clock signal (from 100, paragraph 31);
converting an output of the mixer to digital data (22);
processing the digital data to determine a phase noise or jitter of the first PLL (paragraphs 6, 7, 8, 13, 33, the phase noise detected is phase noise in the PLL as the PLL will switch LPF to determine least phase noise); and
generating an output based on the phase noise or jitter of the first PLL (paragraph 40).
Otani does not explicitly teach using a second PLL based on the reference.
As would have been recognized by a person ordinary skill in the art, the use of a second PLL in place of the DUT of Otani is done merely as a design choice to choosing a user desired DUT to connected to the clock system taught in Otani. As such it would have been obvious to a person of ordinary skill in the art before the filing date of the invention to use a user desired DUT in the circuit of Otani as doing so would be mere matter of design choice to choosing a user desired circuit to connected to the clock system of Otani.
As to claim 19, Otani teaches wherein the second clock signal is received from an external
clock source ((100) is external to (1)). It would have been obvious to a person of ordinary skill in the art to use a high precision clock having phase noise or jitter below a certain threshold as doing so would be a mere matter of design choice to choosing user desired DUT to use.
As to claim 21, Otani teaches a processing circuit to use digital data to determine phase noise (paragraph 33). It would be obvious to a person of ordinary skill in the art to use a fast Fourier transform as doing so would be a mere matter of design choice to using a notoriously well known in the art method of spectrum analysis of phase noise.
As to claim 23, Otani teaches the conversion circuitry (22) and the processing circuit (24) are external to the PLL (10). It would have been obvious to a person of ordinary skill in the art to have the processor or ADC be external as it would be a mere matter of design choice to make separate/nonintegrated.
Allowable Subject Matter
Claims 3, 6, 11, 14, 17, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the cited prior art teach or suggest the more than two PLL and selection taught in claims 3, 11 and 17; and the combiner taught in claims 6, 14 and 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Josefsberg et al (Patent 9762251), teaches a multi PLL and mixer system. Chow et al (Patent 7890279) teaches a multi PLL system for detecting noise.
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/JEFFREY M SHIN/ Primary Examiner, Art Unit 2849