DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-5, 8-15, and 18-21 a re rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Oshidari et al. (WO 97/24858) [Oshidari] . Regarding claims 1, 15, 18 - 21, Oshidari discloses a n apparatus for controlling an equalizer, the apparatus comprising: interface circuitry configured to receive at least one of an input signal and an output signal of the equalizer; and processing circuitry configured to: determine at least one signal metric based on the at least one of the input signal and the output signal of the equalizer; select an operating mode of the equalizer from a plurality of different operating modes based on the determined signal metric; and control the equalizer to operate in the selected operating mode (power of input signal is measured, and if below a threshold, operating mode of equalizer is set to “OFF”, page 29 line 17 – page 30 line 18) . Regarding claim 2, Oshidari discloses the apparatus of claim 1, wherein the plurality of operating modes differ from each other by a power consumption of the equalizer (“on” or “off”, page 30 lines 4-18). Regarding claim 3, Oshidari discloses the apparatus of claim 1, wherein the plurality of operating modes at least comprises a first operating mode, in which a first number of basis functions of the equalizer is enabled for equalization of the input signal, and at least a second operating mode, in which a second number of basis functions of the equalizer is enabled for equalization of the input signal, and the second number of enabled basis functions is smaller than the first number of enabled basis functions (all basis functions are enabled in first mode, and none are enabled in the second mode, page 30 lines 4-18). Regarding claim 4, Oshidari discloses the apparatus of claim 3, wherein one or more nonlinear basis functions and/or one or more linear basis functions enabled in the first operating mode are disabled in the second operating mode (all basis functions are enabled in first mode, and none are enabled in the second mode, page 30 lines 4-18). Regarding claim 5, Oshidari discloses the apparatus of claim 3, wherein the second operating mode causes a lower power consumption of the equalizer than the first operating mode (second operating mode consumes no power, page 30 lines 4-18). Regarding claim 8, Oshidari discloses the apparatus of claim 1, wherein the processing circuitry is configured to cause selection of the operating mode based on comparing the at least one signal metric to at least one corresponding threshold (power of input signal is measured, and if below a threshold, operating mode of equalizer is set to “OFF”, page 29 line 17 – page 30 line 18). Regarding claim 9, Oshidari discloses the apparatus of claim 1, wherein the processing circuitry is configured to apply at least one measurement metric to the at least one of the input signal and the output signal of the equalizer to obtain the at least one signal metric (power level of input signal, page 12 lines 11-15). Regarding claim 10, Oshidari discloses the apparatus of claim 1, wherein the at least one signal metric indicates a signal size of the input signal of the equalizer (power level of input signal, page 12 lines 11-15). Regarding claim 11, Oshidari discloses the apparatus of claim 10, wherein the at least one measurement metric is configured for estimation of an average power of the input signal of the equalizer (page 30 lines 4-18) . Regarding claim 12 , Oshidari discloses t he apparatus of claim 1, wherein the processing circuitry is configured to utilize a finite state machine, FSM, for selecting the operating mode from the plurality of operating modes, and each operating mode corresponds to a respective state of the FSM. Regarding claim 13 , Oshidari discloses t he apparatus of claim 12, wherein the processing circuitry is configured to cause transition from one operating mode or state of the FSM to another operating mode or state of the FSM based on comparing the at least one signal metric to at least one corresponding threshold (power of input signal is measured, and if below a threshold, operating mode of equalizer is set to “OFF”, page 29 line 17 – page 30 line 18) . Regarding claim 14 , Oshidari discloses t he apparatus of claim 1, further comprising signal condition estimation circuitry configured to obtain the at least one signal metric, wherein the signal estimation circuit comprises a number of filters each of which has a different bandwidth and into which the at least one of the input signal and the output signal of the equalizer is fed, and the signal estimation circuit is configured to cause selection of the operating mode from the plurality of operating modes based on an output of the number of filters (signal estimation is measured in decibels, page 29 line 17 – page 30 line 18) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Oshidari . Regarding claims 16 and 17, Oshidari discloses the signal processing system of claim 15, wherein analog to digital conversion is disclosed as taking place (page 20 lines 24-26), but fails to specifically disclose the nonlinear signal processing circuitry is a time-interleaved analog-to-digital converter ( ADC ) and the equalizer is a time-variant non-linear equalizer ( NLEQ ). Examiner takes official notice that including analog to digital conversion within the input stages of signal processing circuitry and the use of time-variant non-linear equalizer s were both notoriously well known in the art at the time of effective filing. It would have been obvious at the time of effective filing to include the conversion of analog to digital signals to take place within the signal processing circuitry and to utilize a time variant NLEQ as claimed, for the known quality of superior channel distortion mitigation. Allowable Subject Matter Claims 6 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Said claimed subject matter describes the second operating mode as an intermediary mode that uses less power and fewer basis functions than the first mode while still being in an operable state relative to a third mode. While adaptive equalization methods are known in the art, the particular claimed combination does not appear to be taught or reasonably suggested in the prior art at the time of effective filing. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT DOMINIC D SALTARELLI whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-7302 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 9:00 am - 5:00 pm EST . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Nathan Flynn can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-1915 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DOMINIC D SALTARELLI/ Primary Examiner, Art Unit 2421