Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-6,8-14,16-18 and 20 are currently pending and have been examined.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-6, 8-14, 16-18 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1+4 of U.S. Patent No. 11,537,420 B2 in view of U.S. Pub. No. 20150242229 A1 (van Riel), further in view of Cuthbert (U.S. Pub. 11405329 B1) and further in view of van Riel2 (U.S. Pub. 20150193249 A1).
The differences between the claims are bolded in the table below:
INSTANT APPLICATION (Current)
U.S. Patent No. 11,537,420 B2
1. A method comprising:
determining, by a guest running in a virtual machine executing on a host computer system, that a virtual processor of the virtual machine is to be idle based on an estimation that interrupts will not be scheduled for the virtual processor within a given time interval;
responsive to determining that the virtual processor of the virtual machine is to be idle, an estimated idle time for a virtual processor of the virtual machine managed by the guest in view of historical idle times of the virtual processor
comparing, by the guest, the estimated idle time with a target latency time assigned to the virtual processor by a hypervisor executing on the host computer system, wherein the target latency time is determined based on a user input specifying a desired response latency for the virtual machine; and
in response to determining that the estimated idle time is not less than the target latency time, selecting, by the guest, a first host power state associated with an entry method involving a virtual machine exit; and
requesting, by the guest, the hypervisor to place a processor of the host computer system in a first host power state and thereby cause the virtual machine to exit to the hypervisor.
1. A power management method for a virtualized computer system, comprising:
assigning, by a hypervisor, a target latency time to a virtual machine of a plurality of virtual machines running on a host computer system, wherein the target latency time represents a desired response latency time for the virtual machine;
determining, by the hypervisor, a plurality of host latency times for a plurality of processor power states of a processor of the host computer system;
comparing, by the hypervisor executed on the host computer system, each host latency time of the plurality of host latency times to the target latency time associated with the virtual machine running on the host computer system; for each of the plurality of processor power states, mapping a processor power state of the plurality of processor power states, in view of the comparison, to a host power state of a plurality of host power states implemented by the hypervisor for the virtual machine; and
providing, by the hypervisor, the plurality of host power states to the virtual machine, wherein the virtual machine performs power management for the virtual machine utilizing the plurality of host power states.
4. The method of claim 1, wherein mapping the plurality of processor power states of the processor to the plurality of host power states in view of the comparison comprises: in response to determining that a second host latency time for a second processor power state of the plurality of processor power states is not less than the target latency time, mapping the second processor power state to a second host power state of the plurality of host power states, wherein the second host power state is associated with a second entry method comprising causing the virtual machine to exit to the hypervisor.
Claim 9 is a system variation of claim 1.
Claim 10 is a system variation of claim 1.
Claim 17 is a non-transitory machine-readable storage medium variation of claim 1.
Claim 18 is a non-transitory machine-readable storage medium variation of claim 1.
Although the claims at issue are not identical, they are not patentably distinct from each other because both the instant claims and the patent claims are directed to methos for power management of a virtualized computer system. The only differences between the claims is that the patent claim recites the additional limitations of “determining … an estimated idle time for a virtual processor … in view of historical idle times of the virtual processor” and “wherein the target latency time is determined based on a user input specifying a desired response latency”. However, van Riel discloses determining an estimated idle time for a virtual processor in view of historical idle times of the virtual processor (par. 0026, guest OS 220 of virtual machine estimates an idle time for virtual CPU (e.g., based on the state of one or more processes managed by guest OS based on historical data)). It would have been obvious to one of ordinary skill to modify the reference patent claims to include the technique of determining idle times based on historical data as disclosed by van Riel to allow for more accurately determining latency times of a virtual processor. Further, Cuthbert teaches wherein the target latency time is determined based on a user input specifying a desired response latency (col. 18, lines 13-14 a latency tolerance input control to specify a relative latency tolerance for the computing resources [e.g., VM instances]). It would have been obvious to one of ordinary skill to modify the reference patent to incorporate the technique of inputting latency period/time as set forth by Cuthbert because it would facility users to specify or input predefined latency times to serve as a trigger to cause a processor to be placed in particular host power states. Further, van Riel2 teaches, that determination may be in response, for example, to detecting that there are no tasks scheduled for execution by the virtual processor, or that there are no interrupts currently schedule. It would have been obvious to one of ordinary skill to modify the reference patent to incorporate the technique of that a virtual process is to be idle a set forth by van Riel2 because it would provide a guest OS for accurately estimating a idle time of a virtual processor of a virtual machine. This would have provided a number of advantages including reducing latencies incurred by processor wake-ups, thereby improving system performance while simultaneously reducing power consumption.
Further, instant application claims 9-14, 16 are similar to patent claims 1-8. Therefore, they are rejected under the same rationale as applied to claims 1.
Further, instant application claims 17-18, 20 are similar to patent claims 1-8. Therefore, they are rejected under the same rationale as applied to claims 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9-14, 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over van Riel et al. (U.S. Pub. No. 20150242229 A1) in view of Tsirkin et al. (U.S. Pub. No. 20180060100 A1), further in view of Cuthbert et al. (U.S. Pub. 11405329 B1), and further in view of van Riel et al. (U.S. Pub. 20150193249 A1, hereinafter van Riel2).
Van Riel, Colman, Cuthbert and van Riel2 were cited in a previous office action.
As per claim 1, van Riel teaches the invention as claimed including a method comprising:
determining, by a guest running in a virtual machine executing on a host computer system, that a virtual processor of the virtual machine is to be idle … (par. 0024 … of determining when virtual CPU 260 will be idle);
responsive to determining that the virtual processor of the virtual machine is to be idle, determining, by the guest, an estimated idle time for the virtual processor of the virtual machine managed by the guest in view of historical idle times of the virtual processor (par. 0025, 0026 At block 301, guest OS 220 of virtual machine 130 estimates an idle time for virtual CPU 260 (e.g., based on [in response to] the state of one or more processes managed by guest OS 220, based on historical data, etc.));
comparing, by the guest, the estimated idle time with a target latency time assigned to the virtual processor by a hypervisor executing on the host computer system … (page 5, claim 10, guest operating system is modified to estimate the host latency time and compare the host latency time to the quotient of the idle time for the virtual CPU; par. 0014 (idle time/performance multiplier)>host latency time; wherein, par. 0029, one or more of these times [target latency times] may be provided to guest OS 220 by hypervisor 125 (e.g., via a message from latency data provider 129 to idle processor manager 225, via shared memory, etc.), either individually or as a sum of the individual times);
in response to determining that the estimated idle time is not less than the target latency time, selecting, by the guest, a first host power state … (par. 0024, idle processor manager 225 … is capable … of determining when virtual CPU 260 will be idle; of estimating idle times for virtual CPU 260; of estimating host latency times; of selecting CPU power states; par. 0030 guest OS 220 selects a power state P of CPU 160 such that: [0031] (i) the host latency time of the power state P is less than (idle time/performance multiplier); par. 0010 When the idle time for the virtual CPU divided by a performance multiplier exceeds the host latency time, the virtual CPU is halted); and
requesting, by the guest, the hypervisor to place a processor of the host computer system in a first host power state … (pg. 5, left column, claim 5, when the idle time for the virtual CPU divided by the performance multiplier exceeds the host latency time, sending to the hypervisor, by the guest operating system, a request to place the CPU in the first power state; par. 0026 a time for CPU 160 to enter the particular CPU power state (also referred to as "an entry time for the power state"; par. 0010 When the idle time for the virtual CPU divided by a performance multiplier exceeds the host latency time, the virtual CPU is halted. Here, by halting the virtual CPU of the VM, which implicitly causes the VM to exit to the hypervisor).
van Riel does not expressly describe: a first host power state associated with an entry method involving a virtual machine exit; thereby cause the virtual machine to exit to the hypervisor.
However, Tsirkin teaches: a first host power state associated with an entry method involving a virtual machine exit; thereby cause the virtual machine to exit to the hypervisor (par. 0045 In some examples, the virtual machine is placed in the suspended state [power state] by stopping a virtual processor of the virtual machine … This may be performed by triggering a virtual machine exit (e.g., by sending an interrupt to the CPU executing the virtual machine) In some examples, the guest triggers the virtual machine exit via a hypercall or a communication to the hypervisor … The hypervisor may also place the virtual machine in a suspended state by transitioning a processor from a guest mode to a host kernel mode and/or a host userspace mode, such that the processor executes instructions of the hypervisor and/or host machine and does not execute instructions of virtual machine guests).
It would have been obvious to one of ordinary skill in the before the effective filing date of the claimed invention to combine the technique of placing a virtual machine in a suspended state by stopping a virtual processor of the virtual machine, thereby causing virtual machine to exit to the hypervisor of Tsirkin with the system and method of van Riel resulting in a system which provides for selecting to place a virtual machine in a suspended state by stopping a virtual processor of the virtual machine, thereby causing virtual machine to exit to the hypervisor as in Tsirkin. One of ordinary skill in the art would have been motivated to make this combination for the purpose temporarily suspending processing of instructions of the virtual machine's guests (par. 0064). Further, this would have allowed the hypervisor to context-switch the underlying processor resources to be used by the hypervisor or another active virtual machine.
van Riel and Tsirkin do not expressly describe: wherein the target latency time is determined based on a user input specifying a desired response latency for the virtual machine.
However, Cuthbert teaches: wherein the target latency time is determined based on a user input specifying a desired response latency for the virtual machine (par. 8, lines 58-63, The latency tolerance may be received as a latency value based on user input to a user interface provided by the user interface component 118. In some embodiments, the user interface may include a latency control or latency selector, which may be manipulated by users to specify a relative importance of latency; col. 18, lines 13-14 a latency tolerance input control to specify a relative latency tolerance for the computing resources [e.g., VM instances]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the technique of specifying a latency tolerance for computing resource such as VM instances of Cuthbert with the system and method of van Riel and Tsirkin resulting in a system and method which provides for specifying a latency tolerance for a virtual machine as in Cuthbert. One of ordinary skill in the art would have been motivated to make this combination for the purpose of providing user users the ability to customize their services, which may require empowering these users to make more decisions (col. 1, lines 15-17).
van Riel, Tsirkin and Cuthbert do not expressly describe: determining … that a virtual processor of the virtual machine is to be idle based on an estimation that interrupts will not be scheduled for the virtual processor within a given time interval.
However, van Riel2 teaches: based on an estimation that interrupts will not be scheduled for the virtual processor within a given time interval (par. 0043 guest OS 220 determines that virtual processor 260, and by extension CPU 160, will be idle. This determination may be in response, for example, to detecting that there are no tasks scheduled for execution by virtual processor 260, or that there are no interrupts currently scheduled for, or expected to be scheduled for, virtual processor 260 within a given time interval).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the technique of determining a virtual processor is to be idle based on detecting no interrupts currently being scheduled of van Riel2 with the system of van Riel, Tsirkin and Cuthbert resulting in a system and method which provides for determining virtual CPU idle time based on detecting no interrupts currently being scheduled as in van Riel2. One of ordinary skill in the art would have been motivated to make this combination for the purpose of reducing latencies incurred by processor wake-ups, thereby improving system performance while simultaneously reducing power consumption (par. 0019).
As per claim 2, van Riel further teaches: wherein the virtual processor is mapped to the processor of the host computer system (par. 0010 where the virtual CPU is mapped to the CPU).
As per claim 3, van Riel further teaches: wherein the first host power state is associated with a first host latency time that is not less than the target latency time (par. 0030 guest OS 220 selects the CPU power state with the largest host latency time satisfying: (idle time/performance multiplier)>host latency time … such that: [0031] (i) the host latency time of the power state P is less than (idle time/performance multiplier)).
A per claim 4, van Riel further teaches: in response to determining that the estimated idle time is less than the target latency time, sending, to the hypervisor, a request to place the processor in a second host power state, wherein the second host power state corresponds to a processor power state of the processor of the host computer system (par. 0024 determining when virtual CPU 260 will be idle; of estimating idle times for virtual CPU 260; of estimating host latency times; of selecting CPU power states; and of sending requests to hypervisor 125 to place CPU 160 in particular power state; pg. 5, claim 7 wherein every other power state of the plurality of power states satisfies one of the following two conditions: (i) the idle time for the virtual CPU divided by the performance multiplier does not exceed an exit time of the other power state).
As per claim 5, van Riel further teaches: wherein the processor power state is associated with a first host latency time that is less than the target latency time, wherein the first host latency time represents a delay between a time of a request to the virtual machine and a time of a response to the request by the virtual machine (par. 0030 guest OS 220 selects the CPU power state with the largest host latency time satisfying: (idle time/performance multiplier)>host latency time [target latency time], when such a selection is possible (i.e., when at least one of the host latency times estimated at block 302 satisfies the inequality). In other words, guest OS 220 selects a power state P of CPU 160 such that: [0031] (i) the host latency time of the power state P is less than (idle time/performance multiplier)).
As per claim 6, van Riel further teaches: wherein the second host power state is associated with an entry method that does not comprise a virtual machine exit (par. 0011 In one implementation, the estimated host latency time for one or more of the power states of the CPU may optionally be further based on at least one of: [0012] one or more context switch times for the CPU to execute the guest (e.g., a time for the CPU to enter execution of the virtual machine).
As per claim 8, van Riel2 further teaches: providing, by the guest, the estimated idle time for the virtual processor to the hypervisor. (par. 0018 More particularly, in some embodiments, one or more commands may be added to the guest operating system (OS) so that the guest OS, upon determining that the processor will be idle, provides an anticipated idle time to the hypervisor).
As per claim 9, it is a system having similar limitations as claim 1. Thus, claim 9 is rejected for the same rationale as applied to claim 1. Van Riel further teaches: a memory; and a processing device operatively coupled to the memory (Fig. 1, CPU, 160, Main Memory 170).
As per claim 10, it is a system having similar limitations as claim 2. Thus, claim 10 is rejected for the same rationale as applied to claim 2.
As per claim 11, it is a system having similar limitations as claim 3. Thus, claim 11 is rejected for the same rationale as applied to claim 3.
As per claim 12, it is a system having similar limitations as claim 4. Thus, claim 12 is rejected for the same rationale as applied to claim 4.
As per claim 13, it is a system having similar limitations as claim 5. Thus, claim 13 is rejected for the same rationale as applied to claim 5.
As per claim 14, it is a system having similar limitations as claim 6. Thus, claim 14 is rejected for the same rationale as applied to claim 6.
As per claim 16, it is a system having similar limitations as claim 8. Thus, claim 16 is rejected for the same rationale as applied to claim 8.
As per claim 17, it is a non-transitory machine-readable storage medium having similar limitations as claim 1. Thus, claim 17 is rejected for the same rationale as applied to claim 1.
As per claim 18, it is a non-transitory machine-readable storage medium having similar limitations as claim 4. Thus, claim 18 is rejected for the same rationale as applied to claim 4.
As per claim 20, it is a non-transitory machine-readable storage medium having similar limitations as claim 8. Thus, claim 20 is rejected for the same rationale as applied to claim 8.
Response to Arguments
Applicant's arguments with respect to claims 1, 9 and 17 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Pub. No. 20200326766 A1 teaches methods for improving idle time estimation by a process scheduler.
U.S. Patent No. 10572667 B2 teaches methods for coordinating Power Management Between Virtual Machines.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Willy W. Huaracha whose telephone number is (571) 270-5510. The examiner can normally be reached on M-F 8:30-5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bradley Teets can be reached on (571) 272-3338. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WH/
Examiner, Art Unit 2195
/BRADLEY A TEETS/Supervisory Patent Examiner, Art Unit 2197
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