DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This action is in response to the submission filed 12 June 2026 for application 18/146,295. Currently claims 24-30 are canceled. Claims 1-5, 8, 9, 11-15, 17, 18, and 20-22 are amended. Claims 1-23 are pending and have been examined.
The objection to the specification has been withdrawn in view of the amendments made.
Response to Arguments
Regarding Applicant’s arguments, filed 12 June 2026, see pages 8-10, with respect to the features “access an acknowledgement from the INA, the acknowledgement to indicate (a) that the first vector was received by the INA, and (b) that the INA has received a corresponding vector from another worker node that is to report to the INA; and execute a second processing iteration after receipt of the acknowledgement” as recited in independent claim 1 (and similarly in independent claims 8 and 17), Applicant specifically argues that Sapio/Lao combination fails to establish a prima facie case of obviousness of the apparatus of claim 1. Withdrawal of the § 103 rejections of claim I (and similarly in independent claims 8 and 17), and all claims dependent thereon is respectfully requested.
Examiner’s response: Applicant’s arguments have been fully considered but are moot because the new ground of rejection (citing new references Yang (SwitchAgg: A Further Step Towards In-Network Computation, 2019) and Wang et al (Efficient Data-Plane Memory Scheduling for In-Network Aggregation, 2022) for teaching the new limitations) does not rely on any reference combination applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 8-10, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al (Efficient Data-Plane Memory Scheduling for In-Network Aggregation, 2022) in view of Yang (SwitchAgg: A Further Step Towards In-Network Computation, 2019).
Regarding claim 1:
Wang teaches: An apparatus to accelerate processing iterations, comprising: train management circuitry to cause a first vector to be sent from a worker node to an in-network-aggregator (INA) after completion of a first processing iteration requested by a parameter server, the INA intermediate the worker node and the parameter server ([Page 2, Column 1, Last Paragraph] Based on programmable switches, a recent technique called In-Network Aggregation (INA) is proposed to scale out distributed training communication. The basic mechanism is illustrated in Figure 1, where workers offload their gradient aggregation from hosts to the switch. As workers’ gradients stream through the switch, the switch adds up the gradient packets from different workers as result packets, and streams the result packets either back to workers (e.g., SwitchML [2], 2 PANAMA [13]) or to the PS (e.g., ATP [1]). Note: Also see Figure 1 which shows the In-network aggregation corresponding to the INA being in between workers and Parameter server corresponding to the INA being intermediate to the worker node and the parameter server);
However, Wang does not explicitly disclose: and protocol configuration circuitry to: access an acknowledgement from the INA, the acknowledgement to indicate (a) that the first vector was received by the INA, and (b) that the INA has received a corresponding vector from another worker node that is to report to the INA; and execute a second processing iteration after receipt of the acknowledgement.
Yang teaches, in an analogous system: and protocol configuration circuitry to: access an acknowledgement from the INA, the acknowledgement to indicate (a) that the first vector was received by the INA, and (b) that the INA has received a corresponding vector from another worker node that is to report to the INA ([Page 5, Column 1, Paragraph 2] Controller. The controller is primarily responsible for configuring the control plane of the switch. Before the execution of an aggregation task, the master issues requests to the controller to launch an aggregation task. The controller must be aware of three kinds of information: 1. The worker numbers of the current aggregation task; 2. The physical topology of the network. Based on these information, the controller constructs an aggregation tree and disseminates this information across the switches. When all the switches receive the information and finishes its configuration, it will send back an acknowledgement to the controller. [Page 5, Column 1, Section 4.1, Paragraph 1] The third type of packets is Ack, which is used for confirmation. Type 0 is used between the controller and master, while type 1 is used between the controller and the switch. The last type is the Aggregation packet, which carries the data that needs to be aggregated);
and execute a second processing iteration after receipt of the acknowledgement ([Page 5, Column 1, Paragraph 2] After ensuring that all the aggregation nodes are rightly configured, the controller replies to the master to start data transmission).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Wang to incorporate the teachings of Yang to use protocol configuration circuitry to: access an acknowledgement from the INA, the acknowledgement to indicate (a) that the first vector was received by the INA, and (b) that the INA has received a corresponding vector from another worker node that is to report to the INA; and execute a second processing iteration after receipt of the acknowledgement. One would have been motivated to do this modification because doing so would give the benefit of ensuring that all the aggregation nodes are rightly configured as taught by Yang [Page 5, Column 1, Paragraph 2].
Regarding claim 2:
The system of Wang and Yang teaches: The apparatus as defined in claim 1 (as shown above).
However, Wang does not explicitly disclose: further including resource location circuitry to identify the INA to which the worker node will report based on a proximity of the worker node to the INA.
Yang further teaches: further including resource location circuitry to identify the INA to which the worker node will report based on a proximity of the worker node to the INA ([Page 5, Column 1, Paragraph 2] The controller is primarily responsible for configuring the control plane of the switch. Before the execution of an aggregation task, the master issues requests to the controller to launch an aggregation task. The controller must be aware of three kinds of information: 1. The worker numbers of the current aggregation task; 2. The physical topology of the network. Based on these information, the controller constructs an aggregation tree and disseminates this information across the switches).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Wang to incorporate the teachings of Yang to further include resource location circuitry to identify the INA to which the worker node will report based on a proximity of the worker node to the INA. One would have been motivated to do this modification because doing so would give the benefit of ensuring that all the aggregation nodes are rightly configured as taught by Yang [Page 5, Column 1, Paragraph 2].
Regarding claim 3:
The system of Wang and Yang teaches: The apparatus as defined in claim 2 (as shown above).
Yang further teaches: wherein the resource location circuitry is to determine the proximity is based on at least one of a physical distance metric or a node hop metric ([Page 4, Column 1, Last but one Paragraph] THEOREM 2.2 When data is evenly distributed among different key varieties, the results of multi-hop aggregation is exactly the same to single-hop aggregation; When data is nonuniformly distributed, the reduction ratio of multi-hop aggregation has the same upper- and lower-bound of the singe-hop aggregation).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Wang to incorporate the teachings of Yang wherein the resource location circuitry is to determine the proximity is based on at least one of a physical distance metric or a node hop metric. One would have been motivated to do this modification because doing so would give the benefit of ensuring that all the aggregation nodes are rightly configured as taught by Yang [Page 5, Column 1, Paragraph 2].
Regarding claim 8:
Wang teaches: An apparatus to facilitate distributed machine learning, comprising: memory; machine readable instructions ([Page 793, Column 2, Section 6, Paragraph 2] Testbed. We conduct most of our experiments on a testbed of 8 machines, each with 1 NVIDIA P100 16 GB GPU, dual 10-core CPU Intel Xeon E5-2630v4 at 2.20 GHz, 128 GB of RAM, and 3 ⇥ 1 TB disks for storage (as single RAID)).
The claim recites substantially same limitations as claim 1 except for the above limitations and is therefore rejected for same rationale as claim 1.
Regarding claim 9:
The claim recites substantially same limitations as claim 2 and is therefore rejected for same rationale as claim 2.
Regarding claim 10:
The claim recites substantially same limitations as claim 3 and is therefore rejected for same rationale as claim 3.
Regarding claim 17:
Wang teaches: A non-transitory machine readable storage medium comprising instructions that, when executed, cause processor circuitry to at least: complete a first processing iteration requested by an orchestrator computing device ([Page 9, Column 1, Section 7.1.1, Paragraph 1] Our testbed contains 5 physical GPU servers, each with 2 V100 GPUs, 40 CPU cores (Intel Xeon Gold 5115), 128GB memory, 2 Mellanox ConnectX5 100Gbps NICs, and one Edgecore Wedge100BF-32X switch, each server have two 100Gbps links connecting to the switch. To scale up our testbed, we further divide one physical server into two separated docker containers, each with 1_ GPU, 20_ CPU cores, 64GB memory and a 100Gbps virtual NIC).
The claim recites substantially same limitations as claim 1 except for the above limitations and is therefore rejected for same rationale as claim 1.
Regarding claim 18:
The claim recites substantially same limitations as claim 2 and is therefore rejected for same rationale as claim 2.
Regarding claim 19:
The claim recites substantially same limitations as claim 3 and is therefore rejected for same rationale as claim 3.
Claims 4, 6, 7, 11, 15, 16, 20, 22, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al (Efficient Data-Plane Memory Scheduling for In-Network Aggregation, 2022) in view of Yang (SwitchAgg: A Further Step Towards In-Network Computation, 2019) and further in view of Gebara et al (IN-NETWORK AGGREGATION FOR SHARED MACHINE LEARNING CLUSTERS, 2021).
Regarding claim 4:
The system of Wang and Yang teaches: The apparatus as defined in claim 1 (as shown above).
However, the system of Wang and Yang does not explicitly disclose: further including resource determination circuitry to access an aggregation tree representative of relationships between the parameter server, a plurality of worker nodes, and a plurality of INAs.
Gebara teaches, in an analogous system: further including resource determination circuitry to access an aggregation tree representative of relationships between the parameter server, a plurality of worker nodes, and a plurality of INAs ([Page 4, Column 1, Paragraph 2] When the PANAMA controller selects in-network aggregation for a job, it initializes all the PSwitches belonging to the spanning trees connecting the workers. Note: Also see Figure 3 showing trees and relationships).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combined teachings of Wang and Yang to incorporate the teachings of Gebara to further include resource determination circuitry to access an aggregation tree representative of relationships between the parameter server, a plurality of worker nodes, and a plurality of INAs. One would have been motivated to do this modification because doing so would give the benefit of higher network efficiency and lower congestion as taught by Gebara [Page 4, Column 1, Paragraph 2].
Regarding claim 6:
The system of Wang and Yang teaches: The apparatus as defined in claim 1 (as shown above).
However, the system of Wang and Yang does not explicitly disclose: wherein the protocol configuration circuitry is to cause a first model to be sent from the parameter server to the worker node.
Gebara teaches, in an analogous system: wherein the protocol configuration circuitry is to cause a first model to be sent from the parameter server to the worker node ([Page 4, Column 1] Note: Figure 3 shows PS in step 2 corresponding to Parameter server and workers in step 3 corresponding to sending from parameter server to worker node).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combined teachings of Wang and Yang to incorporate the teachings of Gebara wherein the protocol configuration circuitry is to cause a first model to be sent from the parameter server to the worker node. One would have been motivated to do this modification because doing so would give the benefit of higher network efficiency and lower congestion as taught by Gebara [Page 4, Column 1, Paragraph 2].
Regarding claim 7:
The system of Wang and Yang teaches: The apparatus as defined in claim 6 (as shown above).
However, the system of Wang and Yang does not explicitly disclose: wherein the protocol configuration circuitry is to cause the worker node to calculate gradient data based on the first model, the worker node to send the gradient data to the INA as the first vector.
Gebara teaches, in an analogous system: wherein the protocol configuration circuitry is to cause the worker node to calculate gradient data based on the first model, the worker node to send the gradient data to the INA as the first vector ([Page 4, Column 2, Last Paragraph] Workers distribute the gradient packets to different trees in a round robin fashion. For instance, in the topology in Fig. 3, with four aggregation trees AggTreei, i = 1; : : : ; 4 and eight aggregation packets with IDs pj , j = 1; : : : ; 8, assuming workers start by sending a single packet to each of the trees).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combined teachings of Wang and Yang to incorporate the teachings of Gebara wherein the protocol configuration circuitry is to cause the worker node to calculate gradient data based on the first model, the worker node to send the gradient data to the INA as the first vector. One would have been motivated to do this modification because doing so would give the benefit of higher network efficiency and lower congestion as taught by Gebara [Page 4, Column 1, Paragraph 2].
Regarding claim 11:
The claim recites substantially same limitations as claim 4 and is therefore rejected for same rationale as claim 4.
Regarding claim 15:
The claim recites substantially same limitations as claim 6 and is therefore rejected for same rationale as claim 6.
Regarding claim 16:
The claim recites substantially same limitations as claim 7 and is therefore rejected for same rationale as claim 7.
Regarding claim 20:
The claim recites substantially same limitations as claim 4 and is therefore rejected for same rationale as claim 4.
Regarding claim 22:
The claim recites substantially same limitations as claim 6 and is therefore rejected for same rationale as claim 6.
Regarding claim 23:
The claim recites substantially same limitations as claim 7 and is therefore rejected for same rationale as claim 7.
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al (Efficient Data-Plane Memory Scheduling for In-Network Aggregation, 2022) in view of Yang (SwitchAgg: A Further Step Towards In-Network Computation, 2019) and Gebara et al (IN-NETWORK AGGREGATION FOR SHARED MACHINE LEARNING CLUSTERS, 2021) and further in view of Lao et al (ATP: In-network Aggregation for Multi-tenant Learning, 2021).
Regarding claim 5:
The system of Wang, Yang, and Gebara teaches: The apparatus as defined in claim 4 (as shown above).
However, the system of Wang, Yang, and Gebara does not explicitly disclose: wherein the protocol configuration circuitry is to prevent resource stalling by permitting the second processing iteration to begin before the parameter server receives the first vector.
Lao teaches, in an analogous system: wherein the protocol configuration circuitry is to prevent resource stalling by permitting the second processing iteration to begin before the parameter server receives the first vector ([Page 742, Column 1, Section 2.1, Last Paragraph] as shown in Figure 1 enables data-parallel training, where training data is partitioned and distributed to workers. There are two phases: gradient computation, where workers locally compute gra [Page 742, Column 2, Paragraph 1] dients; and gradient aggregation, where workers' gradients are transmitted over the network to be aggregated (which in volves the addition of gradients) at one or more end-hosts called parameter servers (PSs). Note: Figure 1 also shows calculations before the parameter server receives).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Wang, Yang, and Gebara to incorporate the teachings of Lao wherein the protocol configuration circuitry is to prevent resource stalling by permitting the second processing iteration to begin before the parameter server receives the first vector. One would have been motivated to do this modification because doing so would give the benefit of enables data-parallel training as taught by Lao [Page 742, Column 1, Section 2.1, Last Paragraph].
Regarding claim 12:
The claim recites substantially same limitations as claim 5 and is therefore rejected for same rationale as claim 5.
Claims 13, 14, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al (Efficient Data-Plane Memory Scheduling for In-Network Aggregation, 2022) in view of Yang (SwitchAgg: A Further Step Towards In-Network Computation, 2019) and further in view of Lao et al (ATP: In-network Aggregation for Multi-tenant Learning, 2021).
Regarding claim 13:
The system of Wang and Yang teaches: The apparatus as defined in claim 11 (as shown above).
However, the system of Wang and Yang does not explicitly disclose: wherein the processor circuitry is to prevent INA stalling by permitting the second processing iteration to begin when an indication of INA availability is detected.
Lao teaches, in an analogous system: wherein the processor circuitry is to prevent INA stalling by permitting the second processing iteration to begin when an indication of INA availability is detected ([Page 745, Column 2, Paragraph 1] The collision flag is marked by a switch when it forwards a gradient packet onward due to the aggregator not being available because it is in use by a different job. This flag helps PS choose another aggregator to avoid collision in the next round).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of the system of Wang and Yang to incorporate the teachings of Lao wherein the processor circuitry is to prevent INA stalling by permitting the second processing iteration to begin when an indication of INA availability is detected. One would have been motivated to do this modification because doing so would give the benefit of avoiding collision in the next round as taught by Lao [Page 745, Column 2, Paragraph 1].
Regarding claim 14:
The system of Wang and Yang teaches: The apparatus as defined in claim 13 (as shown above).
However, the system of Wang and Yang does not explicitly disclose: wherein the processor circuitry is to permit the second processing iteration to begin before data corresponding to the first processing iteration has propagated from the computing resource to the parameter server.
Lao teaches, in an analogous system: wherein the processor circuitry is to permit the second processing iteration to begin before data corresponding to the first processing iteration has propagated from the computing resource to the parameter server ([Page 742, Column 1, Section 2.1, Last Paragraph] as shown in Figure 1 enables data-parallel training, where training data is partitioned and distributed to workers. There are two phases: gradient computation, where workers locally compute gra [Page 742, Column 2, Paragraph 1] dients; and gradient aggregation, where workers' gradients are transmitted over the network to be aggregated (which in-volves the addition of gradients) at one or more end-hosts called parameter servers (PSs). Note: Figure 1 also shows calculations before the parameter server receives).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combined teachings of Wang and Yang to incorporate the teachings of Lao wherein the processor circuitry is to permit the second processing iteration to begin before data corresponding to the first processing iteration has propagated from the computing resource to the parameter server. One would have been motivated to do this modification because doing so would give the benefit of avoiding collision in the next round as taught by Lao [Page 745, Column 2, Paragraph 1].
Regarding claim 21:
The claim recites substantially same limitations as claim 5 and is therefore rejected for same rationale as claim 5.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sapio et al (In-Network Computation is a Dumb Idea Whose Time Has Come, 2017) discloses the opportunities and challenges for co-designing data center distributed systems with their network layer. We believe that the time has finally come for offloading part of their computation to execute in-network. However, in-network computation tasks must be judiciously crafted to match the limitations of the network machine architecture of programmable devices. With the help of our experiments on machine learning and graph analytics workloads, we identify that aggregation functions raise opportunities to exploit the limited computation power of networking hardware to lessen network congestion and improve the overall application performance. Moreover, as a proof-of-concept, we propose DAIET, a system that performs in-network data aggregation. Experimental results with an initial prototype show a large data reduction ratio (86.9%-89.3%) and a similar decrease in the workers’ computation time.
Jepsen et al (From Sand to Flour: The Next Leap in Granular Computing with NanoSort, 2022) discloses leveraging the low communication latency of a new NIC/CPU hardware design, the nanoPU, to explore a new extreme of granularity in distributed computation, where a problem is partitioned into tens of thousands of nanosecondscale tasks. To evaluate the feasibility and practicality of extremely fine-grained computing, we built NanoSort, a distributed sorting algorithm running on the nanoPU. Using cycle-accurate FireSim simulations of 65,536 nanoPU cores, we show that NanoSort can sort 1M keys in 68μs, an order of magnitude faster than MilliSort, the current state-of-the-art.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAITANYA RAMESH JAYAKUMAR whose telephone number is (571)272-3369. The examiner can normally be reached Mon-Fri 9am-1pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Omar Fernandez Rivas can be reached at (571)272-2589. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.R.J./Examiner, Art Unit 2128
/OMAR F FERNANDEZ RIVAS/Supervisory Patent Examiner, Art Unit 2128
