DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to applicant’s amendment filed on 12/12/2025.
Claims 1-20 are pending and examined.
Response to Arguments
Applicant’s arguments filed 12/12/2025, with respect to the objection of claim 6 have been fully considered and are persuasive. The objection of claim 6 has been withdrawn.
Applicant's arguments filed 12/12/2025 with respect to 35 U.S.C. 101 have been fully considered but they are not persuasive. The applicant argued that “determining whether a memory device is full cannot reasonably be performed in a human mind.” Examiner respectfully disagrees, see the 35 U.S.C. 101 rejections below for a detailed analysis. The examiner interprets the limitation of “determining whether a memory device is full…” can be reasonably performed in a human mind by having a human read a GUI, chart, or other interface displaying the current memory information of a device. When the interface indicates that the memory of a particular device is full, it would be reasonable for a human mind to determine that the memory device is full. The applicant further argues that “the process address space identifier (PASID) to which the weight is being assigned corresponds to an input/output command from a virtual device that is received at the processor. Thus, it is physically impossible for a human mind to assign a weight to each PASID because the PASID is associated with an interrupt generated by the processor and is, thus, a value associated with a physical or virtual memory that is readable only by the processor” and disagrees with “the recitation of "determining the interrupts to be evicted from the first queue based on the weight," is a mental process at least for the reason that such determination cannot be practically performed in a human mind because the interrupts are stored in a physical or virtual memory (i.e., first queue) that are executable only by the processor.” For the reasons provided above with regards to determining whether a memory device is full, the examiner would follow the same reasoning in which a human mind could read an interface displaying relevant information and either make a determination of the interrupts to be evicted based on the weight or assign a weight to each PASID. Therefore, the 35 U.S.C. 101 rejections are maintained.
Applicant's arguments filed 12/12/2025 with respect to 35 U.S.C. 103 have been fully considered but they are not persuasive. Applicant argued that “there is no evidence in any of the cited references to suggest that one would be motivated to evict the interrupt data” and “combining Jani with the teachings of Liu is at best an exercise in hindsight to shoehorn the combined teachings cited references into the claims without any evidence to suggest that such combination would result in the claimed subject matter, let alone that it would have been obvious to make such a combination.” Examiner respectfully disagrees, see 35 U.S.C. 103 rejections below for a detailed analysis. Examiner interprets Liu’s virtual server querying the cache queue for a record whose popularity is lower than a threshold and deleting the corresponding record to disclose determining and evicting the data to be evicted from the first queue based on the weight. While Liu does not explicitly teach that the data stored corresponds to the interrupts, interrupt data is a popular type of data to be stored as evidenced by Jani. Deleting the corresponding record correlates to evicting the data, and combining Jani’s teachings which include stored interrupt data with Liu’s teachings which include the eviction of stored data would therefore disclose the limitation of evicting the interrupt data. It would have been obvious to one of ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to combine Jani with Liu because the virtual server can implement interlinked storage, which can improve disk utilization. Deleting content whose popularity is low based on popularity information further improves disk utilization. Therefore, the 35 U.S.C. 103 rejections are maintained.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to (an) abstract idea(s) without significantly more.
Claim 1 recites:
A method for managing resources by using a processor coupled to a physical memory device, the processor including a first queue and a second queue, the method comprising:
receiving, by the processor, input/output commands from a virtual device;
generating, by the processor, interrupts that each includes a process address space identifier (PASID) that corresponds to one of the input/output commands;
storing, by the processor, the interrupts in the first queue;
storing, by the processor, in the memory device, data that respectively corresponds to each of the interrupts;
storing, by the processor, in the second queue, location information that indicates a storage location of the respective data stored in the memory device and size information that indicates a size of the respective data,
determining, by the processor executing a first queue management program, whether the memory device is full;
upon determining that the memory device is full, assigning, by the processor, a weight to each PASID, and
determining the interrupts to be evicted from the first queue based on the weight and
evicting, by the processor, the determined interrupts from the first queue.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes.
Claim 1 is a process.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The ‘determining’ limitation in #6 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. The limitation “determining” in the context of this claim encompasses a person analyzing, evaluating, or determining whether the memory device is full, including comparison or judgement.
The ‘assigning’ limitation in #7 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. The limitation “assigning” in the context of this claim encompasses a person analyzing, evaluating, or determining a weight for each PASID, including comparison or judgement.
The ‘determining’ limitation in #8 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. The limitation “determining” in the context of this claim encompasses a person analyzing, evaluating, or determining the interrupts to be evicted based on the weight, including comparison or judgement.
Step 2A, Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The ‘receiving’ limitation in #1 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element that is insignificant extra-solution activity. The limitation “receiving” in the context of this claim encompasses mere data gathering. See MPEP 2106.05(g).
The ‘generating’ limitation in #2 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element as “apply it” that is mere instructions to apply an exception. The limitation “generating” in the context of this claim encompasses merely generating interrupts that include corresponding PASID. See MPEP 2106.05(f).
The ‘storing’ limitation in #3 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element that is insignificant extra-solution activity. The limitation “storing” in the context of this claim encompasses merely storing information in memory. See MPEP 2106.05(g).
The ‘storing’ limitation in #4 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element that is insignificant extra-solution activity. The limitation “storing” in the context of this claim encompasses merely storing information in memory. See MPEP 2106.05(g).
The ‘storing’ limitation in #5 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element that is insignificant extra-solution activity. The limitation “storing” in the context of this claim encompasses merely storing information in memory. See MPEP 2106.05(g).
The ‘evicting’ limitation in #9 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element as “apply it” that is mere instructions to apply an exception. The limitation “evicting” in the context of this claim encompasses merely evicting the determined interrupts from the first queue. See MPEP 2106.05(f).
Additionally, one or more of the claims recite the following additional elements:
A processor (Claim 1)
A first and second queue (Claim 1)
A physical memory device (Claim 1)
These additional elements are recited at a high level of generality (i.e., as generic computer components) such that they amount to no more than components comprising mere instructions to apply the exception. Accordingly, these additional elements do not integrate the abstract idea(s) into a practical application because they do not impose any meaningful limits on practicing the abstract ideas(s).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
Additionally, with regards to #3-5 above, per MPER 2106.05(d)(II), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic matter (e.g., at a high level of generality) or as insignificant extra-solution activity:
Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93;
As discussed above with respect to integration of the abstract idea(s) into a practical application, the aforementioned additional elements amount to no more than components for obtaining or gathering data and comprising mere instructions to apply the exception which is evidently seen in MPEP 2106.05(g)&(f). Mere instructions to apply an exception using generic computer components cannot provide an inventive concept.
Claim 7 merely further describes the first and second queue of Claim 1. The claim does not include additional elements that integrate into practical application or are sufficient to amount to significantly more than the judicial exception.
Claim 8 merely further describes the processor of Claim 1. The claim does not include additional elements that integrate into practical application or are sufficient to amount to significantly more than the judicial exception.
Claim 9 merely further describes the virtual devices of Claim 1. The claim does not include additional elements that integrate into practical application or are sufficient to amount to significantly more than the judicial exception.
Claim 10 merely further describes the memory devices of Claim 1. The claim does not include additional elements that integrate into practical application or are sufficient to amount to significantly more than the judicial exception.
Therefore, Claims 1 and 7-10 are directed to (an) abstract idea(s) without significantly more.
Claim 2 recites:
wherein storing the interrupts in the first queue includes:
when the memory device is not full, storing, by the processor, the interrupts in the first queue.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes.
Claim 2 is a process.
Step 2A, Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The ‘storing’ limitation in #10 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element that is insignificant extra-solution activity. The limitation “storing” in the context of this claim encompasses merely storing information in memory. See MPEP 2106.05(g).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
Additionally, with regards to #10 above, per MPER 2106.05(d)(II), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic matter (e.g., at a high level of generality) or as insignificant extra-solution activity:
Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93;
As discussed above with respect to integration of the abstract idea(s) into a practical application, the aforementioned additional elements amount to no more than components for obtaining or gathering data and comprising mere instructions to apply the exception which is evidently seen in MPEP 2106.05(g). Mere instructions to apply an exception using generic computer components cannot provide an inventive concept.
Therefore, Claim 2 is directed to (an) abstract idea(s) without significantly more.
Claim 3 recites:
erasing, by the processor, all or part of data that is stored in the memory device.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes.
Claim 3 is a process.
Step 2A, Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The ‘erasing’ limitation in #11 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element as “apply it” that is mere instructions to apply an exception. The limitation “erasing” in the context of this claim encompasses merely erasing all or part of data stored in a memory device. See MPEP 2106.05(f).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
As discussed above with respect to integration of the abstract idea(s) into a practical application, the aforementioned additional elements amount to no more than components for obtaining or gathering data and comprising mere instructions to apply the exception which is evidently seen in MPEP 2106.05(f). Mere instructions to apply an exception using generic computer components cannot provide an inventive concept.
Therefore, Claim 3 is directed to (an) abstract idea(s) without significantly more.
Claims 4, 13 and 18 recite:
evicting, by the processor, location information and size information that correspond to each of the interrupts evicted from the first queue from the second queue; and
erasing, by the processor, data that corresponds to each of the evicted interrupts from the memory device.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes.
Claim 4 is a process.
Claim 13 is a machine.
Claim 18 is a machine.
Step 2A, Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The ‘evicting’ limitation in #12 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element as “apply it” that is mere instructions to apply an exception. The limitation “evicting” in the context of this claim encompasses merely evicting location and size information corresponding to each of the interrupts from the first and second queue. See MPEP 2106.05(f).
The ‘erasing’ limitation in #13 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element as “apply it” that is mere instructions to apply an exception. The limitation “erasing” in the context of this claim encompasses merely erasing all or part of data stored in a memory device. See MPEP 2106.05(f).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
As discussed above with respect to integration of the abstract idea(s) into a practical application, the aforementioned additional elements amount to no more than components for obtaining or gathering data and comprising mere instructions to apply the exception which is evidently seen in MPEP 2106.05(f). Mere instructions to apply an exception using generic computer components cannot provide an inventive concept.
Therefore, Claims 4, 13, and 18 are directed to (an) abstract idea(s) without significantly more.
Claims 5, 14, and 19 recite:
wherein assigning weight to each PASID includes:
calculating, by the processor, a number of interrupts for each PASID that are stored in the first queue; and
assigning, by the processor, a lowest weight to those interrupts that correspond to a PASID having a smallest number of interrupts calculated for each PASID.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes.
Claim 5 is a process.
Claim 14 is a machine.
Claim 19 is a machine.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The ‘calculating’ limitation in #14 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. The limitation “calculating” in the context of this claim encompasses a person analyzing, evaluating, or determining a number of interrupts for each PASID, including comparison or judgement.
The ‘assigning’ limitation in #15 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. The limitation “assigning” in the context of this claim encompasses a person analyzing, evaluating, or determining a lowest weight to interrupts corresponding to a PASID having a smallest number of interrupts, including comparison or judgement.
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
As discussed above with respect to integration of the abstract idea(s) into a practical application, the aforementioned additional elements amount to no more than components for obtaining or gathering data and comprising mere instructions to apply the exception which is evidently seen in MPEP 2106.05(f). Mere instructions to apply an exception using generic computer components cannot provide an inventive concept.
Therefore, Claims 5, 14, and 19 are directed to (an) abstract idea(s) without significantly more.
Claims 6, 15, and 20 recite:
wherein assigning weight to each PASID includes:
calculating, by the processor, a time difference between a time point of storage of a first interrupt and a time point of storage of a last interrupt for each PASID of the interrupts stored in the first queue; and
assigning, by the processor, the weight based on the time difference calculated for each PASID, wherein the weight increases as the calculated time difference increases.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes.
Claim 6 is a process.
Claim 15 is a machine.
Claim 20 is a machine.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The ‘calculating’ limitation in #16 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. The limitation “calculating” in the context of this claim encompasses a person analyzing, evaluating, or determining a time difference between time points of storage, including comparison or judgement.
The ‘assigning’ limitation in #17 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. The limitation “assigning” in the context of this claim encompasses a person analyzing, evaluating, or determining a weight based on the time difference, including comparison or judgement.
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
As discussed above with respect to integration of the abstract idea(s) into a practical application, the aforementioned additional elements amount to no more than components for obtaining or gathering data and comprising mere instructions to apply the exception which is evidently seen in MPEP 2106.05(f). Mere instructions to apply an exception using generic computer components cannot provide an inventive concept.
Therefore, Claims 6, 15, and 20 are directed to (an) abstract idea(s) without significantly more.
Claim 11 recites:
A processor coupled to a physical memory device, comprising:
a first queue and a second queue,
wherein the processor executes a process address space identifier (PASID) allocation computer program, a first queue management computer program, and a second queue management computer program,
wherein the PASID allocation computer program receives input/output commands from virtual devices and
generates interrupts that each include a PASID that corresponds to one of the input/output commands,
wherein the first queue management computer program receives the interrupts generated by the PASID allocation computer program,
determines whether the memory device is full, and
upon determining that the memory is full, assigns a weight to each PASID,
determines the interrupts to be evicted from the first queue based on the weight, and
evicts the determined interrupts from the first queue, and
wherein the second queue management computer program stores, in the memory device, data that respectively corresponds to each of the interrupts in response to each of the interrupts received from the PASID allocation computer program or the first queue management computer program, and
stores in the second queue location information that indicates a storage location of the data that is stored in the memory device, and size information that indicates a size of the data.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes.
Claim 11 is a machine.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The ‘determining’ limitation in #21 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. The limitation “determining” in the context of this claim encompasses a person analyzing, evaluating, or determining whether the memory device is full, including comparison or judgement.
The ‘assigning’ limitation in #22 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. The limitation “assigning” in the context of this claim encompasses a person analyzing, evaluating, or determining a weight for each PASID, including comparison or judgement.
The ‘determining’ limitation in #23 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. The limitation “determining” in the context of this claim encompasses a person analyzing, evaluating, or determining the interrupts to be evicted based on the weight, including comparison or judgement.
Step 2A, Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The ‘receiving’ limitation in #18 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element that is insignificant extra-solution activity. The limitation “receiving” in the context of this claim encompasses mere data gathering. See MPEP 2106.05(g).
The ‘generating’ limitation in #19 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element as “apply it” that is mere instructions to apply an exception. The limitation “generating” in the context of this claim encompasses merely generating interrupts that include corresponding PASID. See MPEP 2106.05(f).
The ‘receiving’ limitation in #20 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element that is insignificant extra-solution activity. The limitation “receiving” in the context of this claim encompasses mere data gathering. See MPEP 2106.05(g).
The ‘evicting’ limitation in #24 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element as “apply it” that is mere instructions to apply an exception. The limitation “evicting” in the context of this claim encompasses merely evicting the determined interrupts from the first queue. See MPEP 2106.05(f).
The ‘storing’ limitation in #25 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element that is insignificant extra-solution activity. The limitation “storing” in the context of this claim encompasses merely storing information in memory. See MPEP 2106.05(g).
The ‘storing’ limitation in #26 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element that is insignificant extra-solution activity. The limitation “storing” in the context of this claim encompasses merely storing information in memory. See MPEP 2106.05(g).
Additionally, one or more of the claims recite the following additional elements:
A processor (Claim 11)
A first and second queue (Claim 11)
A physical memory device (Claim 11)
These additional elements are recited at a high level of generality (i.e., as generic computer components) such that they amount to no more than components comprising mere instructions to apply the exception. Accordingly, these additional elements do not integrate the abstract idea(s) into a practical application because they do not impose any meaningful limits on practicing the abstract ideas(s).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
Additionally, with regards to #25-26 above, per MPER 2106.05(d)(II), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic matter (e.g., at a high level of generality) or as insignificant extra-solution activity:
Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93;
As discussed above with respect to integration of the abstract idea(s) into a practical application, the aforementioned additional elements amount to no more than components for obtaining or gathering data and comprising mere instructions to apply the exception which is evidently seen in MPEP 2106.05(g)&(f). Mere instructions to apply an exception using generic computer components cannot provide an inventive concept.
Therefore, Claim 11 is directed to (an) abstract idea(s) without significantly more.
Claims 12 and 17 recite:
wherein the first queue management computer program stores the interrupts in the first queue when the memory device is not full, and
the second queue management computer program erases all or part of data from the data stored in the memory device.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes.
Claim 12 is a machine.
Claim 17 is a machine.
Step 2A, Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The ‘storing’ limitation in #27 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element that is insignificant extra-solution activity. The limitation “storing” in the context of this claim encompasses merely storing information in memory. See MPEP 2106.05(g).
The ‘erasing’ limitation in #28 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element as “apply it” that is mere instructions to apply an exception. The limitation “erasing” in the context of this claim encompasses merely erasing all or part of data stored in a memory device. See MPEP 2106.05(f).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
Additionally, with regards to #27 above, per MPER 2106.05(d)(II), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic matter (e.g., at a high level of generality) or as insignificant extra-solution activity:
Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93;
As discussed above with respect to integration of the abstract idea(s) into a practical application, the aforementioned additional elements amount to no more than components for obtaining or gathering data and comprising mere instructions to apply the exception which is evidently seen in MPEP 2106.05(g)&(f). Mere instructions to apply an exception using generic computer components cannot provide an inventive concept.
Therefore, Claims 12 and 17 are directed to (an) abstract idea(s) without significantly more.
Claim 16 recites:
A processor coupled to a physical memory device, comprising:
a process address space identifier (PASID) management computer program, a first queue management computer program, a second queue management computer program, a first hardware queue, and a second hardware queue,
wherein the PASID management computer program receives input/output commands from virtual devices,
generates interrupts that each include a PASID that corresponds to each of the input/output commands, and
stores the interrupts in the first hardware queue,
wherein the first queue management computer program determines whether the memory device is full, and
upon determining that the memory device is full, assigns a weight to each PASID,
determines the interrupts to be evicted from the first hardware queue based on the weight, and
evicts the determined interrupts from the first hardware queue, and
wherein the second queue management computer program stores data that respectively corresponds to each of the interrupts in the memory device in response to each of the interrupts received from the PASID management computer program, and
stores, in the second hardware queue, location information that indicates a storage location of the data that is stored in the memory device, and size information that indicates a size of the respective data.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes.
Claim 16 is a machine.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The ‘determining’ limitation in #32 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. The limitation “determining” in the context of this claim encompasses a person analyzing, evaluating, or determining whether the memory device is full, including comparison or judgement.
The ‘assigning’ limitation in #33 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. The limitation “assigning” in the context of this claim encompasses a person analyzing, evaluating, or determining a weight for each PASID, including comparison or judgement.
The ‘determining’ limitation in #34 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. The limitation “determining” in the context of this claim encompasses a person analyzing, evaluating, or determining the interrupts to be evicted based on the weight, including comparison or judgement.
Step 2A, Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The ‘receiving’ limitation in #29 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element that is insignificant extra-solution activity. The limitation “receiving” in the context of this claim encompasses mere data gathering. See MPEP 2106.05(g).
The ‘generating’ limitation in #30 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element as “apply it” that is mere instructions to apply an exception. The limitation “generating” in the context of this claim encompasses merely generating interrupts that include corresponding PASID. See MPEP 2106.05(f).
The ‘storing’ limitation in #31 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element that is insignificant extra-solution activity. The limitation “storing” in the context of this claim encompasses merely storing information in memory. See MPEP 2106.05(g).
The ‘evicting’ limitation in #35 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element as “apply it” that is mere instructions to apply an exception. The limitation “evicting” in the context of this claim encompasses merely evicting the determined interrupts from the first queue. See MPEP 2106.05(f).
The ‘storing’ limitation in #36 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element that is insignificant extra-solution activity. The limitation “storing” in the context of this claim encompasses merely storing information in memory. See MPEP 2106.05(g).
The ‘storing’ limitation in #37 above, as claimed and under broadest reasonable interpretation (BRI), is an additional element that is insignificant extra-solution activity. The limitation “storing” in the context of this claim encompasses merely storing information in memory. See MPEP 2106.05(g).
Additionally, one or more of the claims recite the following additional elements:
A processor (Claim 16)
A first and second hardware queue (Claim 16)
A physical memory device (Claim 16)
These additional elements are recited at a high level of generality (i.e., as generic computer components) such that they amount to no more than components comprising mere instructions to apply the exception. Accordingly, these additional elements do not integrate the abstract idea(s) into a practical application because they do not impose any meaningful limits on practicing the abstract ideas(s).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
Additionally, with regards to #31 and #36-37 above, per MPER 2106.05(d)(II), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic matter (e.g., at a high level of generality) or as insignificant extra-solution activity:
Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93;
As discussed above with respect to integration of the abstract idea(s) into a practical application, the aforementioned additional elements amount to no more than components for obtaining or gathering data and comprising mere instructions to apply the exception which is evidently seen in MPEP 2106.05(g)&(f). Mere instructions to apply an exception using generic computer components cannot provide an inventive concept.
Therefore, Claim 16 is directed to (an) abstract idea(s) without significantly more.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-9, 11-13, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Jani et al. (US Patent No. US 20220350714 A1), hereinafter “Jani” in view of Benisty et al. (US Patent No. US 20170315943 A1), hereinafter “Benisty” and Liu et al. (US Patent No. US 20180278680 A1), hereinafter “Liu.”
With regards to Claim 1, Jani teaches:
A method for managing resources by using a processor coupled to a physical memory device, the processor including a first queue and a second queue (Fig. 5, paragraphs 59, 66, 88 and 92, “VDEV 404 may be composed of a static number of ADIs that are pre-allocated at the time of VDEV instantiation or composed dynamically by VDCM 402 in response to guest driver 424 requests to allocate/free resources… For fast path interrupts from ADIs, the VDCM invokes host driver 412 to allocate and configure required interrupt message address and data in the IMS… an ADI composed of N queues on a PF may support N interrupt messages to distinguish work arrivals or completions for each queue, where N is a natural number... The size, location, and storage format for IMS 328 is device-specific. For example, some devices may implement IMS as on-device storage, while other stateful devices that manage contexts that are saved to and restored from primary memory 130 may implement IMS as part of the context privileged state.” The virtual device VDEV includes a processor and a static number of ADIs which include a natural number of queues correlates to managing resources using a processor that includes a first and second queue. The interrupt message address and data being stored in the IMS, which can be implemented as on-device storage, correlates to a processor coupled to a physical memory device), the method comprising:
receiving, by the processor, input/output commands from a virtual device (Paragraph 79, “There are one or more virtual devices (VDEVs) such as virtual device 1 508, virtual device 2 510, . . . virtual device K 512, where K is a natural number, being executed by computing platform 101. Each guest partition may call one or more virtual devices for I/O requests.” The virtual device being called to receive I/O requests correlates to receiving input/output commands from a virtual device);
generating, by the processor. interrupts that each includes a process address space identifier (PASID) that corresponds to one of the input/output commands (Paragraphs 65 and 81, “One source is VDCM software 402 itself that may generate virtual interrupts on behalf of the VDEV to be delivered to the guest driver. These are software generated interrupts by the slow path operations of the VDEV emulated by the VDCM. The other source of interrupts is ADI instances 432, 434 on the device that are used to support fast path operations of VDEV 404. ADI generated interrupts use interrupt messages stored in Interrupt Message Storage (IMS) 328… requests from ADIs are distinguished through a Process Address Space Identifier (PASID) in an end-to-end PASID TLP Prefix. The PCI Express specification defines the Process Address Space Identifier (PASID) in the PASID TLP Prefix of a transaction, which in conjunction with the RID, identifies the address space associated with the request.” The virtual interrupts generated on behalf of the VDEV and ADI instances from fast and slow path operations correlates to generating interrupts that correspond to one of the input/output commands. The PASID that is included in requests from ADIs correlates to interrupts including a PASID):
storing, by the processor, the interrupts in the first queue (Paragraph 45, “IMS 328 enables devices to store the interrupt messages for ADIs in a device-specific optimized manner without the scalability restrictions of PCI Express defined MSI-X capability. PF BARs 320 and ADI MMIO components 322 are coupled with device backend resources 330. Device backend resources 330 may include command/status registers, on device queues, references to in-memory queues, local memory on the device, or any other device specific internal constructs.” The interrupt messages being stored on device backend resources which include on device queues and references to in-memory queues and are coupled to the ADI correlates to storing the interrupts in the first queue);
storing- by the processor, in the memory device, data that respectively corresponds to each of the interrupts (Paragraphs 66 and 92, “For fast path interrupts from ADIs, the VDCM invokes host driver 412 to allocate and configure required interrupt message address and data in the IMS... The size, location, and storage format for IMS 328 is device-specific. For example, some devices may implement IMS as on-device storage, while other stateful devices that manage contexts that are saved to and restored from primary memory 130 may implement IMS as part of the context privileged state.” The interrupt message address and data being stored in the IMS, which can be implemented as on-device storage, correlates to storing data corresponding to each of the interrupts in the memory device):
Jani does not explicitly teach:
and storing, by the processor, in the second queue, location information that indicates a storage location of the respective data stored in the memory device and size information that indicates a size of the respective data,
determining, by the processor executing a first queue management program, whether the memory device is full;
upon determining that the memory device is full, assigning, by the processor, a weight to each PASID, and determining the interrupts to be evicted from the first queue based on the weight and evicting, by the processor, the determined interrupts from the first queue.
However, Benisty teaches:
and storing, by the processor, in the second queue, location information that indicates a storage location of the respective data stored in the memory device and size information that indicates a size of the respective data (Paragraph 32, “in response to the completion queue entry being posted to the completion queue 110, the access device 130 (e.g., the processor 111) may cause the access device DMA engine 113 to fetch the data 123 at the first location 117 based on the access device DMA parameters 124 in the completion queue entry that identifies an address (e.g., a source address) of the data 123 and a size of the data 123.” The completion queue entry identifying an address of the data and the size of the data correlates to storing location and size information of the respective data in a second queue).
Benisty does not explicitly teach that the respective data corresponds to each of the interrupts. However, interrupt data is a popular type of data to be stored as evidenced by Jani above (Paragraph 45).
Additionally, Liu teaches:
determining, by the processor, whether the memory device is full (Paragraph 22, “determining, by the first virtual server, that the storage capacity of the partition corresponding to the second URL is full.” The first virtual server having a processor determining the storage capacity of the partition is full corresponds to the processor determining whether the memory device is full);
upon determining that the memory device is full, assigning, by the processor, a weight to each ID (Paragraph 22, “With reference to the sixth possible implementation of the first aspect, in a seventh possible implementation of the first aspect, each partition corresponds to one virtual server, and the method further includes determining, by the first virtual server, that the storage capacity of the partition corresponding to the second URL is full, determining that a storage capacity of at least one of multiple partitions managed by the first virtual server is not full, and selecting a partition whose storage capacity is not full, and instructing, by the first virtual server, the second storage server to cache the content corresponding to the second URL into the selected partition, and adding a hash value of the second URL, a hash value of the partition caching the content corresponding to the second URL, and the popularity information corresponding to the second URL to a record of a cache queue.” The processor determining that the storage capacity of the partition is full corresponds to the processor determining the memory device is full. The second storage server caching content including the popularity information corresponding to the second URL to a record of a cache queue corresponds to the processor assigning a weight to each ID), and determining the data to be evicted from the first queue based on the weight and evicting, by the processor, the determined data from the first queue (Paragraph 22, “determining, by the first virtual server, that the storage capacity of the partition corresponding to the second URL is full, determining that storage capacities of the multiple partitions managed by the first virtual server are all full, and querying the cache queue for a record whose popularity is lower than a first threshold, and instructing, according to the found record, a storage server corresponding to a partition in the record to delete content corresponding to a URL in the record.” The virtual server querying the cache queue for a record whose popularity is lower than a threshold and deleting the corresponding record corresponds to determining and evicting the data to be evicted from the first queue based on the weight).
Liu does not explicitly teach that the data stored corresponds to the interrupts, that the ID is a PASID, and that the processor [is] executing a first queue management program. However, interrupt data is a popular type of data to be stored as evidenced by Jani above (Paragraph 45). Additionally, PASID are a popular type of identifier as evidenced by Jani above (Paragraphs 65 and 81). Lastly, first queue management programs are a popular type of management program executed by processors as evidenced by Jani below (Paragraphs 44-45 and 66).
Therefore, it would have been obvious to one of ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to combine Jani with and storing, by the processor, in the second queue. location information that indicates a storage location of the respective data stored in the memory device and size information that indicates a size of the respective data as taught by Benisty because providing additional information on the size and location of the data allows the data to be accessed without using the interconnect and instead using the processor and DMA engine, which improves the performance of the interconnect by reducing load (Benisty: paragraph 33).
Additionally, it would have been obvious to one of ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to combine Jani with determining, by the processor, whether the memory device is full; upon determining that the memory device is full, assigning, by the processor, a weight to each ID, and determining the data to be evicted from the first queue based on the weight and evicting, by the processor, the determined data from the first queue as taught by Liu because the virtual server can implement interlinked storage, which can improve disk utilization. Deleting content whose popularity is low based on popularity information further improves disk utilization (Liu: paragraph 23).
With regards to Claim 2, Jani in view of Benisty and Liu teaches the method of Claim 1 above. Liu further teaches:
when the memory device is not full, storing, by the processor, the data in the first queue (Paragraph 22, “determining that a storage capacity of at least one of multiple partitions managed by the first virtual server is not full, and selecting a partition whose storage capacity is not full, and instructing, by the first virtual server, the second storage server to cache the content corresponding to the second URL into the selected partition… and the popularity information corresponding to the second URL to a record of a cache queue.” The first virtual server selecting a partition whose storage capacity is not full and storing popularity information corresponding to the second URL to a record of a cache queue corresponds to the processor storing data in the first queue when the memory device is not full).
Therefore, it would have been obvious to one of ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to combine Jani with wherein storing the data in the first queue includes: determining, by the processor, whether the memory device is full; and when the memory device is not full, storing, by the processor, the data in the first queue as taught by Liu because the virtual server can implement interlinked storage, which can improve disk utilization (Liu: paragraph 23).
With regards to Claim 3, Jani in view of Benisty and Liu teaches the method of Claim 1 above. Liu further teaches:
erasing, by the processor, all or part of data that is stored in the memory device (Paragraph 329, “instructing, according to the found record, a storage server corresponding to a partition in the record to delete content corresponding to a URL in the record.” The content corresponding to a URL in the record being deleted in the partition corresponds to erasing all or part of data that is stored in the memory device).
Liu does not explicitly teach that the data stored corresponds to the interrupts. However, interrupt data is a popular type of data to be stored as evidenced by Jani above (Paragraph 45).
Therefore, it would have been obvious to one of ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to combine Jani with erasing, by the processor, all or part of data that is stored in the memory device as taught by Liu because the virtual server can implement interlinked storage, which can improve disk utilization. Additionally, deleted content allows for the reallocation of the storage resource to a different virtual server (Liu: paragraphs 23 and 29).
With regards to Claims 12 and 17, the method of Claims 2 and 3 perform the same steps as the machines of Claims 12 and 17, and Claims 12 and 17 are therefore rejected using the same rationale set forth above in the rejection of Claims 2 and 3. Liu does not explicitly teach that the first queue management computer program is determining whether the memory device is full and that the second queue management computer program is erasing data stored in the memory device. However, first and second queue management computer programs are popular methods of handling data storage as evidenced by Jani above (Paragraphs 44-45 and 66).
With regards to Claim 4, Jani in view of Benisty and Liu teaches the method of Claim 1 above. Liu further teaches:
evicting, by the processor, information that correspond to each of the data evicted (Paragraph 329, “querying the cache queue for a record whose popularity is lower than a first threshold, and instructing, according to the found record, a storage server corresponding to a partition in the record to delete content corresponding to a URL in the record.” Instructing the storage server corresponding to a partition to delete content corresponding to a URL in the record correlates to evicting information corresponding to the evicted data); and
erasing, by the processor, data that corresponds to each of the evicted data from the memory devices (Paragraph 329, “querying the cache queue for a record whose popularity is lower than a first threshold, and instructing, according to the found record, a storage server corresponding to a partition in the record to delete content corresponding to a URL in the record.” Instructing the storage server corresponding to a partition to delete content corresponding to a URL in the record correlates to erasing the data from the memory devices).
Liu does not explicitly teach that the data stored and evicted corresponds to the interrupts, that the [information] evicted corresponding to the data includes location and size information, and that the [data] is evicted from a first and second queue. However, interrupt data is a popular type of data to be stored as evidenced by Jani above (Jani: Paragraph 45). Additionally, location and size information corresponding to [data] is a popular type of data to be stored as evidenced by Benisty above (Benisty: Paragraph 32). It would be obvious to one of ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention that evicting data from the memory device would trigger the eviction of relevant data from other popular data storage formats such as queues because the data would no longer be relevant.
Therefore, it would have been obvious to one of ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to combine Jani with erasing, by the processor, all or part of data that is stored in the memory device as taught by Liu because the virtual server can implement interlinked storage, which can improve disk utilization. Additionally, deleted content allows for the reallocation of the storage resource to a different virtual server (Liu: paragraphs 23 and 29).
With regards to Claims 13 and 18, the method of Claim 4 performs the same steps as the machines of Claims 13 and 18, and Claims 13 and 18 are therefore rejected using the same rationale set forth above in the rejection of Claim 4. Liu does not explicitly teach that the first queue management computer program is determining data to be evicted from the first queue, that first or second queue management computer program is erasing size and location data stored in the memory device and queue, and that the first and second queues are hardware queues. However, first and second queue management computer programs are popular methods of handling data storage as evidenced by Jani above (Paragraphs 44-45 and 66). Additionally, location and size information corresponding to data is a popular type of data to be stored as evidenced by Benisty above (Benisty: Paragraph 32). It would be obvious to one of ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention that evicting data from the memory device would trigger the eviction of relevant data from other popular data storage formats such as queues because the data would no longer be relevant. Lastly, hardware queues are a popular form of queue as evidenced by Jani above (Paragraph 120).
With regards to Claim 7, Jani in view of Benisty and Liu teaches the method of claim 1 above. Jani further teaches:
wherein each of the first queue and the second queue is implemented by usinu software or by using hardware (Paragraphs 88 and 120, “an ADI composed of N queues on a PF may support N interrupt messages to distinguish work arrivals or completions for each queue, where N is a natural number… ADI MMIO registers 828, 830, . . . 832, 834 are used by VDEVs to directly communicate with hardware queues 436, 438, . . . 440, 442.” The ADI being composed of N queues and its ADI MMIO registers used by the VDEVs communicating with multiple hardware queues correlates to the first and second queue implemented using hardware).
With regards to Claim 8, Jani in view of Benisty and Liu teaches the method of claim 1 above. Jani further teaches:
wherein the processor supports a scalable I/O virtualization (S-IOV) specification (Paragraph 89, “The Scalable IOV architecture enables device implementations to support a large number of ADIs, and each ADI may use multiple interrupt messages.” The scalable IOV architecture used to support a large number of ADIs which each use multiple interrupt messages correlates to the processor supporting a scalable I/O specification).
With regards to Claim 9, Jani in view of Benisty and Liu teaches the method of claim 1 above. Jani further teaches:
wherein each of the virtual devices is a virtual machine or a container (Paragraph 58, “Similarly, multiple types of VDEV compositions are possible (with respect to the number of backing ADIs, functionality of ADIs, etc.) on a Scalable IOV device 230. VDCM 402 may publish support for composing multiple ‘VDEV types’, enabling a virtual machine resource manager (VMRM) 416 to request different types of VDEV instances for assigning to virtual machines (VMs).” The different VDEV compositions which include virtual machines correlates to each of the virtual devices being a virtual machine).
With regards to Claim 11, Jani teaches:
A processor coupled to a physical memory device, comprising:
a first queue and a second queue (Fig. 5, paragraphs 59, 66, 88 and 92, “VDEV 404 may be composed of a static number of ADIs that are pre-allocated at the time of VDEV instantiation or composed dynamically by VDCM 402 in response to guest driver 424 requests to allocate/free resources… For fast path interrupts from ADIs, the VDCM invokes host driver 412 to allocate and configure required interrupt message address and data in the IMS… an ADI composed of N queues on a PF may support N interrupt messages to distinguish work arrivals or completions for each queue, where N is a natural number... The size, location, and storage format for IMS 328 is device-specific. For example, some devices may implement IMS as on-device storage, while other stateful devices that manage contexts that are saved to and restored from primary memory 130 may implement IMS as part of the context privileged state.” The virtual device VDEV includes a processor and a static number of ADIs which include a natural number of queues correlates to managing resources using a processor that includes a first and second queue. The interrupt message address and data being stored in the IMS, which can be implemented as on-device storage, correlates to a processor coupled to a physical memory device), wherein the processor executes a process address space identifier (PASID) allocation computer program (Paragraphs 51 and 79, “The Scalable IOV architecture of embodiments of the present invention introduces a device-specific software component referred to as the Virtual Device Composition Module (VDCM) 402 that is responsible for composing one or more virtual device (VDEV) 404 instances utilizing one or more Assignable Device Interfaces (ADIs)… There are one or more virtual devices (VDEVs) such as virtual device 1 508, virtual device 2 510, . . . virtual device K 512, where K is a natural number, being executed by computing platform 101. Each guest partition may call one or more virtual devices for I/O requests.” The VDCM composing one or more virtual devices being called to receive I/O requests correlates to a PASID allocation computer program), a first queue management computer program (Paragraphs 44-45, “PF BARs 302 and VF BARs 312 are coupled to device resource remapping logic and VF⇔PF mailbox logic 308, which calls device backend resources 310. In an embodiment, device backend resources 310 includes a plurality of queues for storing packets. PF BARs 320 and ADI MMIO components 322 are coupled with device backend resources 330. Device backend resources 330 may include command/status registers, on device queues, references to in-memory queues, local memory on the device, or any other device specific internal constructs.” The PF BARs coupled to the ADI and device backend resources which include a plurality of queues correlates to a first queue management computer program), and a second queue management computer program (Paragraph 66, “For fast path interrupts from ADIs, the VDCM invokes host driver 412 to allocate and configure required interrupt message address and data in the IMS.” The host driver allocating and configuring interrupt message address and data to the IMS correlates to a second queue management computer program),
wherein the PASID allocation computer program receives input/output commands from virtual devices (Paragraphs 51 and 79, “The Scalable IOV architecture of embodiments of the present invention introduces a device-specific software component referred to as the Virtual Device Composition Module (VDCM) 402 that is responsible for composing one or more virtual device (VDEV) 404 instances utilizing one or more Assignable Device Interfaces (ADIs)… There are one or more virtual devices (VDEVs) such as virtual device 1 508, virtual device 2 510, . . . virtual device K 512, where K is a natural number, being executed by computing platform 101. Each guest partition may call one or more virtual devices for I/O requests.” The VDCM that composes one or more virtual devices being called to receive I/O requests correlates to the PASID allocation computer program receiving input/output commands from a virtual device) and generates interrupts that each include a PASID that corresponds to one of the input/output commands (Paragraphs 65 and 81, “One source is VDCM software 402 itself that may generate virtual interrupts on behalf of the VDEV to be delivered to the guest driver. These are software generated interrupts by the slow path operations of the VDEV emulated by the VDCM. The other source of interrupts is ADI instances 432, 434 on the device that are used to support fast path operations of VDEV 404. ADI generated interrupts use interrupt messages stored in Interrupt Message Storage (IMS) 328… requests from ADIs are distinguished through a Process Address Space Identifier (PASID) in an end-to-end PASID TLP Prefix. The PCI Express specification defines the Process Address Space Identifier (PASID) in the PASID TLP Prefix of a transaction, which in conjunction with the RID, identifies the address space associated with the request.” The virtual interrupts generated on behalf of the VDEV and ADI instances from fast and slow path operations by the VDCM software correlates to generating interrupts that correspond to one of the input/output commands. The PASID that is included in requests from ADIs correlates to interrupts including a PASID), wherein the first queue management computer program receives the interrupts generated by the PASID allocation computer program (Paragraphs 44-45 and 65, “PF BARs 302 and VF BARs 312 are coupled to device resource remapping logic and VF⇔PF mailbox logic 308, which calls device backend resources 310… IMS 328 enables devices to store the interrupt messages for ADIs in a device-specific optimized manner without the scalability restrictions of PCI Express defined MSI-X capability. PF BARs 320 and ADI MMIO components 322 are coupled with device backend resources 330. Device backend resources 330 may include command/status registers, on device queues, references to in-memory queues, local memory on the device, or any other device specific internal constructs… For typical virtual device compositions, there are two sources of interrupts delivered as VDEV interrupts to guest driver 424. One source is VDCM software 402 itself that may generate virtual interrupts on behalf of the VDEV to be delivered to the guest driver. These are software generated interrupts by the slow path operations of the VDEV emulated by the VDCM. The other source of interrupts is ADI instances 432, 434 on the device that are used to support fast path operations of VDEV 404. ADI generated interrupts use interrupt messages stored in Interrupt Message Storage (IMS) 328.” Interrupts being generated on the VDCM software or ADI instances correlate to the PASID allocation computer generating interrupts. The received interrupt messages being stored on device backend resources which include on device queues and references to in-memory queues through the PF BARs and are coupled to the ADI correlates to the first queue management computer program receiving the interrupts generated by the PASID allocation computer program), and
wherein the second queue management computer program stores, in the memory device, data that respectively corresponds to each of the interrupts in response to each of the interrupts received from the PASID allocation computer program or the first queue management computer program (Paragraphs 66 and 92, “For fast path interrupts from ADIs, the VDCM invokes host driver 412 to allocate and configure required interrupt message address and data in the IMS... The size, location, and storage format for IMS 328 is device-specific. For example, some devices may implement IMS as on-device storage, while other stateful devices that manage contexts that are saved to and restored from primary memory 130 may implement IMS as part of the context privileged state.” The host driver storing interrupt message address and data in the IMS, which can be implemented as on-device storage, correlates to the second queue management computer system storing data corresponding to each of the interrupts in the memory device),
Jani does not explicitly teach:
determines whether the memory device is full, and upon determining that the memory is full, assigns a weight to each PASID, determines the interrupts to be evicted from the first queue based on the weight, and evicts the determined interrupts from the first queue,
and stores in the second queue location information that indicates a storage location of the data that is stored in the memory device, and size information that indicates a size of the data.
However, Benisty teaches:
and stores in the second queue location information that indicates a storage location of the data that is stored in the memory device, and size information that indicates a size of the data. (Paragraph 32, “in response to the completion queue entry being posted to the completion queue 110, the access device 130 (e.g., the processor 111) may cause the access device DMA engine 113 to fetch the data 123 at the first location 117 based on the access device DMA parameters 124 in the completion queue entry that identifies an address (e.g., a source address) of the data 123 and a size of the data 123.” The completion queue entry identifying an address of the data and the size of the data correlates to storing location and size information of the respective data in a second queue).
Benisty does not explicitly teach that the respective data corresponds to each of the interrupts. However, interrupt data is a popular type of data to be stored as evidenced by Jani above (Paragraph 45).
Additionally, Liu teaches:
determines whether the memory device is full, (Paragraph 22, “determining, by the first virtual server, that the storage capacity of the partition corresponding to the second URL is full.” The first virtual server having a processor determining the storage capacity of the partition is full corresponds to determining whether the memory device is full);
and upon determining that the memory device is full, assigns a weight to each ID (Paragraph 22, “With reference to the sixth possible implementation of the first aspect, in a seventh possible implementation of the first aspect, each partition corresponds to one virtual server, and the method further includes determining, by the first virtual server, that the storage capacity of the partition corresponding to the second URL is full, determining that a storage capacity of at least one of multiple partitions managed by the first virtual server is not full, and selecting a partition whose storage capacity is not full, and instructing, by the first virtual server, the second storage server to cache the content corresponding to the second URL into the selected partition, and adding a hash value of the second URL, a hash value of the partition caching the content corresponding to the second URL, and the popularity information corresponding to the second URL to a record of a cache queue.” The processor determining that the storage capacity of the partition is full corresponds to determining the memory device is full. The second storage server caching content including the popularity information corresponding to the second URL to a record of a cache queue corresponds to assigning a weight to each ID), determines the data to be evicted from the first queue based on the weight, and evicts the determined data from the first queue (Paragraph 22, “determining, by the first virtual server, that the storage capacity of the partition corresponding to the second URL is full, determining that storage capacities of the multiple partitions managed by the first virtual server are all full, and querying the cache queue for a record whose popularity is lower than a first threshold, and instructing, according to the found record, a storage server corresponding to a partition in the record to delete content corresponding to a URL in the record.” The virtual server querying the cache queue for a record whose popularity is lower than a threshold and deleting the corresponding record corresponds to determining and evicting the data to be evicted from the first queue based on the weight).
Liu does not explicitly teach that the data stored corresponds to the interrupts and that the ID is a PASID. However, interrupt data is a popular type of data to be stored as evidenced by Jani above (Paragraph 45). Additionally, PASID are a popular type of identifier as evidenced by Jani above (Paragraphs 65 and 81).
Therefore, it would have been obvious to one of ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to combine Jani with and stores in the second queue location information that indicates a storage location of the data that is stored in the memory device, and size information that indicates a size of the data as taught by Benisty because providing additional information on the size and location of the data allows the data to be accessed without using the interconnect and instead using the processor and DMA engine, which improves the performance of the interconnect by reducing load (Benisty: paragraph 33).
Additionally, it would have been obvious to one of ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to combine Jani with determines whether the memory device is full, and upon determining that the memory is full, assigns a weight to each PASID, determines the interrupts to be evicted from the first queue based on the weight, and evicts the determined interrupts from the first queue, and as taught by Liu because the virtual server can implement interlinked storage, which can improve disk utilization. Deleting content whose popularity is low based on popularity information further improves disk utilization (Liu: paragraph 23).
With regards to Claim 16, Jani teaches:
A processor coupled to a physical memory device (Fig. 5, paragraphs 59, 66, 88 and 92, “VDEV 404 may be composed of a static number of ADIs that are pre-allocated at the time of VDEV instantiation or composed dynamically by VDCM 402 in response to guest driver 424 requests to allocate/free resources… For fast path interrupts from ADIs, the VDCM invokes host driver 412 to allocate and configure required interrupt message address and data in the IMS… an ADI composed of N queues on a PF may support N interrupt messages to distinguish work arrivals or completions for each queue, where N is a natural number... The size, location, and storage format for IMS 328 is device-specific. For example, some devices may implement IMS as on-device storage, while other stateful devices that manage contexts that are saved to and restored from primary memory 130 may implement IMS as part of the context privileged state.” The virtual device VDEV including a processor correlates to a processor. The interrupt message address and data being stored in the IMS, which can be implemented as on-device storage, correlates to a processor coupled to a physical memory device), comprising:
a process address space identifier (PASID) management computer program (Paragraphs 51 and 79, “The Scalable IOV architecture of embodiments of the present invention introduces a device-specific software component referred to as the Virtual Device Composition Module (VDCM) 402 that is responsible for composing one or more virtual device (VDEV) 404 instances utilizing one or more Assignable Device Interfaces (ADIs)… There are one or more virtual devices (VDEVs) such as virtual device 1 508, virtual device 2 510, . . . virtual device K 512, where K is a natural number, being executed by computing platform 101. Each guest partition may call one or more virtual devices for I/O requests.” The VDCM composing one or more virtual devices being called to receive I/O requests correlates to a PASID management computer program), a first queue management computer program (Paragraphs 44-45, “PF BARs 302 and VF BARs 312 are coupled to device resource remapping logic and VF⇔PF mailbox logic 308, which calls device backend resources 310. In an embodiment, device backend resources 310 includes a plurality of queues for storing packets. PF BARs 320 and ADI MMIO components 322 are coupled with device backend resources 330. Device backend resources 330 may include command/status registers, on device queues, references to in-memory queues, local memory on the device, or any other device specific internal constructs.” The PF BARs coupled to the ADI and device backend resources which include a plurality of queues correlates to a first queue management computer program), a second queue management computer program (Paragraph 66, “For fast path interrupts from ADIs, the VDCM invokes host driver 412 to allocate and configure required interrupt message address and data in the IMS.” The host driver allocating and configuring interrupt message address and data to the IMS correlates to a second queue management computer program), a first hardware queue, and a second hardware queue (Fig. 5, paragraphs 59, 88 and 120, “VDEV 404 may be composed of a static number of ADIs that are pre-allocated at the time of VDEV instantiation or composed dynamically by VDCM 402 in response to guest driver 424 requests to allocate/free resources… an ADI composed of N queues on a PF may support N interrupt messages to distinguish work arrivals or completions for each queue, where N is a natural number… ADI MMIO registers 828, 830, . . . 832, 834 are used by VDEVs to directly communicate with hardware queues” The virtual device VDEV includes a processor and a static number of ADIs which include a natural number of hardware queues correlates to a first and second hardware queue).
wherein the PASID management computer program receives input/output commands from virtual devices (Paragraphs 51 and 79, “The Scalable IOV architecture of embodiments of the present invention introduces a device-specific software component referred to as the Virtual Device Composition Module (VDCM) 402 that is responsible for composing one or more virtual device (VDEV) 404 instances utilizing one or more Assignable Device Interfaces (ADIs)… There are one or more virtual devices (VDEVs) such as virtual device 1 508, virtual device 2 510, . . . virtual device K 512, where K is a natural number, being executed by computing platform 101. Each guest partition may call one or more virtual devices for I/O requests.” The VDCM that composes one or more virtual devices being called to receive I/O requests correlates to the PASID management computer program receiving input/output commands from a virtual device), generates interrupts that each include a PASID that corresponds to each of the input/output commands (Paragraphs 65 and 81, “One source is VDCM software 402 itself that may generate virtual interrupts on behalf of the VDEV to be delivered to the guest driver. These are software generated interrupts by the slow path operations of the VDEV emulated by the VDCM. The other source of interrupts is ADI instances 432, 434 on the device that are used to support fast path operations of VDEV 404. ADI generated interrupts use interrupt messages stored in Interrupt Message Storage (IMS) 328… requests from ADIs are distinguished through a Process Address Space Identifier (PASID) in an end-to-end PASID TLP Prefix. The PCI Express specification defines the Process Address Space Identifier (PASID) in the PASID TLP Prefix of a transaction, which in conjunction with the RID, identifies the address space associated with the request.” The virtual interrupts generated on behalf of the VDEV and ADI instances from fast and slow path operations by the VDCM software correlates to generating interrupts that correspond to one of the input/output commands. The PASID that is included in requests from ADIs correlates to interrupts including a PASID), and stores the interrupts in the first hardware queue (Paragraphs 45, 51, and 120, “IMS 328 enables devices to store the interrupt messages for ADIs in a device-specific optimized manner without the scalability restrictions of PCI Express defined MSI-X capability. PF BARs 320 and ADI MMIO components 322 are coupled with device backend resources 330. Device backend resources 330 may include command/status registers, on device queues, references to in-memory queues, local memory on the device, or any other device specific internal constructs... The Scalable IOV architecture of embodiments of the present invention introduces a device-specific software component referred to as the Virtual Device Composition Module (VDCM) 402 that is responsible for composing one or more virtual device (VDEV) 404 instances utilizing one or more Assignable Device Interfaces (ADIs)… ADI MMIO registers 828, 830, . . . 832, 834 are used by VDEVs to directly communicate with hardware queues” The VDCM which utilizes the ADI storing interrupt messages through ADI MMIO registers which communicate with hardware queues correlates to the PASID management computer program storing the interrupts in the first queue), and
wherein the second queue management computer program stores data that respectively corresponds to each of the interrupts in the memory device in response to each of the interrupts received from the PASID management computer program (Paragraphs 66 and 92, “For fast path interrupts from ADIs, the VDCM invokes host driver 412 to allocate and configure required interrupt message address and data in the IMS... The size, location, and storage format for IMS 328 is device-specific. For example, some devices may implement IMS as on-device storage, while other stateful devices that manage contexts that are saved to and restored from primary memory 130 may implement IMS as part of the context privileged state.” The host driver storing interrupt message address and data in the IMS, which can be implemented as on-device storage, correlates to the second queue management computer system storing data corresponding to each of the interrupts in the memory device).
Jani does not explicitly teach:
wherein the first queue management computer program determines whether the memory device is full, and upon determining that the memory device is full, assigns a weight to each PASID, determines the interrupts to be evicted from the first hardware queue based on the weight, and evicts the determined interrupts from the first hardware queue,
and stores, in the second hardware queue, location information that indicates a storage location of the data that is stored in the memory device, and size information that indicates a size of the respective data.
However, Benisty teaches:
and stores, in the second queue, location information that indicates a storage location of the data that is stored in the memory device, and size information that indicates a size of the respective data. (Paragraph 32, “in response to the completion queue entry being posted to the completion queue 110, the access device 130 (e.g., the processor 111) may cause the access device DMA engine 113 to fetch the data 123 at the first location 117 based on the access device DMA parameters 124 in the completion queue entry that identifies an address (e.g., a source address) of the data 123 and a size of the data 123.” The completion queue entry identifying an address of the data and the size of the data correlates to storing location and size information of the respective data in a second queue).
Benisty does not explicitly teach that the respective data corresponds to each of the interrupts and that the second queue is a hardware queue. However, interrupt data is a popular type of data to be stored as evidenced by Jani above (Paragraph 45). Additionally, hardware queues are a popular form of queue as evidenced by Jani above (Paragraph 120).
Additionally, Liu teaches:
wherein the processor determines whether the memory device is full, (Paragraph 22, “determining, by the first virtual server, that the storage capacity of the partition corresponding to the second URL is full.” The first virtual server having a processor determining the storage capacity of the partition is full corresponds to determining whether the memory device is full);
and upon determining that the memory device is full, assigns a weight to each ID (Paragraph 22, “With reference to the sixth possible implementation of the first aspect, in a seventh possible implementation of the first aspect, each partition corresponds to one virtual server, and the method further includes determining, by the first virtual server, that the storage capacity of the partition corresponding to the second URL is full, determining that a storage capacity of at least one of multiple partitions managed by the first virtual server is not full, and selecting a partition whose storage capacity is not full, and instructing, by the first virtual server, the second storage server to cache the content corresponding to the second URL into the selected partition, and adding a hash value of the second URL, a hash value of the partition caching the content corresponding to the second URL, and the popularity information corresponding to the second URL to a record of a cache queue.” The processor determining that the storage capacity of the partition is full corresponds to determining the memory device is full. The second storage server caching content including the popularity information corresponding to the second URL to a record of a cache queue corresponds to assigning a weight to each ID), determines the data to be evicted from the first queue based on the weight, and evicts the determined data from the first queue (Paragraph 22, “determining, by the first virtual server, that the storage capacity of the partition corresponding to the second URL is full, determining that storage capacities of the multiple partitions managed by the first virtual server are all full, and querying the cache queue for a record whose popularity is lower than a first threshold, and instructing, according to the found record, a storage server corresponding to a partition in the record to delete content corresponding to a URL in the record.” The virtual server querying the cache queue for a record whose popularity is lower than a threshold and deleting the corresponding record corresponds to determining and evicting the data to be evicted from the first queue based on the weight).
Liu does not explicitly teach that the processor is a first queue management computer program, that the data stored corresponds to the interrupts, that the ID is a PASID, and that the first queue is a hardware queue. However, queue management computer programs are a popular method of querying backend resources or devices as evidenced by Jani above (Paragraphs 44-45). Interrupt data is a popular type of data to be stored as evidenced by Jani above (Paragraph 45). Additionally, PASID are a popular type of identifier as evidenced by Jani above (Paragraphs 65 and 81). Hardware queues are a popular form of queue as evidenced by Jani above (Paragraph 120).
Therefore, it would have been obvious to one of ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to combine Jani and stores, in the second hardware queue, location information that indicates a storage location of the data that is stored in the memory device, and size information that indicates a size of the respective data as taught by Benisty because providing additional information on the size and location of the data allows the data to be accessed without using the interconnect and instead using the processor and DMA engine, which improves the performance of the interconnect by reducing load (Benisty: paragraph 33).
Additionally, it would have been obvious to one of ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to combine Jani with wherein the first queue management computer program determines whether the memory device is full, and upon determining that the memory device is full, assigns a weight to each ID, determines the data to be evicted from the first queue based on the weight, and evicts the determined data from the first queue as taught by Liu because the virtual server can implement interlinked storage, which can improve disk utilization. Deleting content whose popularity is low based on popularity information further improves disk utilization (Liu: paragraph 23).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jani in view of Benisty, Liu and Krishnegowda et al. (US Patent No. US 20220284105 A1), hereinafter “Krishnegowda.”
With regards to Claim 10, Jani in view of Benisty and Liu teaches the method of Claim 1 above. Jani in view of Benisty and Liu does not explicitly teach:
wherein, when the memory device is included inside the processor, the memory device is a static random access memory (SRAM), and
when the memory device is positioned outside the processor, the memory device is a dynamic random access memory (DRAM)
However, Krishnegowda teaches:
wherein, when the memory device is included inside the processor, the memory device is a static random access memory (SRAM) (Paragraph 11, “contents of the memory device are copied from the unsecured memory device outside a processor to static random-access memory (SRAM) inside the processor.” The contents of the memory device being transferred to SRAM inside the processor correlates to the memory device being a SRAM when inside the processor), and
when the memory device is positioned outside the processor, the memory device is a dynamic random access memory (DRAM) (Paragraphs 10 and 14, “the memory device may be outside a trusted environment or zone, and may be unsecured… system 100 may also include a memory device, such as memory 104, that may store data accessed by processor 102. In various embodiments, memory 104 is configured to be communicatively coupled with processor 102 via an interface, such as a dynamic random-access memory (DRAM) interface.” The memory device being outside of a trusted environment or zone such as the processor and having a DRAM interface correlates to the memory device being a DRAM when positioned outside the processor).
Therefore, it would have been obvious to one of ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to combine Jani with wherein, when the memory device is included inside the processor, the memory device is a static random access memory (SRAM), and when the memory device is positioned outside the processor, the memory device is a dynamic random access memory (DRAM) as taught by Krishnegowda because conventional application processors may have to rely on unsecured external memory devices and synchronization between the memory device and the processor might not be possible. When the memory device is SRAM inside the processor, it can be checked for integrity to reduce the risk of denial-of-service attacks due to data in external memory devices being modified. When the memory device is DRAM outside the processor, it can be communicatively coupled with the processor through an interface which can include a secured memory module for validation (Krishnegowda: paragraphs 10-11 and 14-15).
Objected Claims
Claims 5-6, 14-15, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Yadong et al. (WO Patent No. WO 2018063718 A1); teaching a method for I/O access to physical memory, VM, or container storage using a queue pair and assigning a PASID to the queue pair. A virtual device is provided information for read or write requests to the submission queue of the queue pair. Each read or write request sent by the controller for I/O access includes the PASID as a 20-bit prefix header. The host physical memory or storage can also include DRAM.
Conclusion
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/SELINA ELISA HU/ Examiner, Art Unit 2193
/Chat C Do/Supervisory Patent Examiner, Art Unit 2193