DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The present application, 18146727, filed 12/27/2022 claims priority from provisional application 63294299, filed 12/28/2021.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/19/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
A. wherein values of the first input of reduced processing elements (RPE's) which are PEs disposed in a first column of the PE array have a smaller number of bits than values of the first input of RPEs which are PEs disposed in other columns as specified in claims 6 and 17. Fig. 9 shows the values of the first input of reduced processing elements (RPE's) which are PEs disposed in a first column of the PE array have a larger number of bits (eight bits) than values of the first input of RPEs which are PEs disposed in other columns (four bits).
Figure 4 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See page 5 lines 7-8 which discloses that Fig. 4 shows a general (i.e., conventional) FIR filter structure. See MPEP § 608.02(g).
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: terminal 200 mentioned in page 11 line 20. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
A. wherein values of the first input of reduced processing elements (RPE's) which are PEs disposed in a first column of the PE array have a smaller number of bits than values of the first input of RPEs which are PEs disposed in other columns as specified in claims 6 and 17.
The claims are inconsistent with the drawings and the specification. Fig. 9 shows the values of the first input of reduced processing elements (RPE's) which are PEs disposed in a first column of the PE array have a larger number of bits (eight bits) than values of the first input of RPEs which are PEs disposed in other columns (four bits). See also page 21 lines 8-9 which discloses “the RPE's have a larger area (e.g., 4 bits x 8 bits) than RPEs”; and page 22 lines 21-22 which discloses “the RPEs have a bit-precision of 4 bits x 4 bits, and the RPE's have a bit-precision of 4 bits x 8 bits”.
Claim Objections
Claims 7-9 and 18-19 are objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected.
A. In claim 7 line 2, “values of the first input of the RPEs” should read “the values of the first input of the RPEs” instead because this limitation is already introduced in claim 6 line 3 from which the claim depends.
B. In claim 8 line 2, “m (m is a natural number larger than or equal to 2) parts” should read “m parts, wherein m is a natural number larger than or equal to 2” instead for better clarity because a parenthesis is normally only used to denote reference characters. Claim 18 recites the same limitations and is objected to for the same reason.
C. In claim 9 line 2, “the m input parts” should read “the m parts” instead for consistency of claim terminologies. Claim 19 recites the same limitations and is objected to for the same reason.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: compensator in claims 10-11 and 20.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
compensator: see Fig. 9 reference character C and page 18 lines 14-15 “the compensator C includes adders and flip-flops”
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 and 11-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1-9 and 11-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: the compensator and the configuration of the compensator to compensate for the differential values. Page 1 line 12 and page 3 lines 6-7 discloses that an adder or the like is needed for adding to a result of an accumulator. Page 15 lines 14-16 also discloses that it is only possible to perform MAC operations using differential values by adding an adder for performing an addition operation of a previous output (see Figs. 4 and 5 for comparison). See also page 18 line 14 to page 20 line 2 which discloses that compensator (which includes an adder) is needed to correctly calculate a MAC result when using differential values. Therefore, the compensator is an essential element because it is not possible to correctly calculate a MAC result when using differential values without including the compensator to compensate for the differential values.
Claim 8 recites “wherein a first value of the second input is divided into m (m is a natural number larger than or equal to 2) parts” in lines 1-2. This limitation is unclear because it merely states a function (that a first value of the second input is somehow divided into m parts) that is not performed by any structure recited in the claim. It is unclear whether the recited functions follow from the structure recited in the claim, i.e., the (PE) array which a plurality of PEs, so it is unclear whether the function requires some other structure or is simply a result of operating the system in a certain manner. Claim 18 recites the same limitation and is rejected for the same reason. Claim 9 inherit the same deficiency as claim 1 by reason of dependence.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 2 and 15 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 2 recites “wherein the PE array comprises: PEs configured to only apply the differential values to the first input” in line 1-2. Claim 2 fails to include all the limitations of claim 1 upon which it depends because claim 1 requires applying the differential values to the first input and the second input to each of the PEs, however, claim 2 requires PEs that only apply the differential values to the first input. It is not apparent that there can be PEs configured to only apply the differential values to the first input while each PE of the PE array applies the differential values to the first input and the second input. Claim 15 recites the same limitations and is rejected for the same reason. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-4, 10-16 and 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under Step 1, claims 1-4 and 10-13 recite a systolic array structure and, therefore, is a machine. Claim 14-16 and 20 recite a device and, therefore, is a machine.
Under Step 2A prong 1, claim 1 recites
A systolic array structure including
a processing element (PE) array in which a plurality of PEs are connected,
wherein the systolic array structure performs a multiply and accumulate (MAC) operation by applying differential values to a first input and a second input which are input to each of the PEs.
The above underlined limitations of performing a multiply and accumulate (MAC) operation using differential values amounts to processing mathematical relationships/calculations and falls within the “Mathematical Concepts” and “Mental Processes” grouping of abstract ideas. The step of “perform” is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. That is, other than reciting “processing element (PE) array”, nothing in the claim element precludes the step from practically being performed in the human mind. For example, but for the “processing element (PE) array” language, the claim encompasses manually performing multiplication and addition operations using difference values between previous inputs and current inputs as inputs to the multiplication and addition operations as disclosed in at least page 19 and Fig. 9 using pen and paper. Accordingly, the claim is directed to recite an abstract idea.
Under step 2A prong 2, the claim recites the following additional elements: a processing element (PE) array in which a plurality of PEs are connected. However, the additional element of “a processing element (PE) array in which a plurality of PEs are connected” is recited at a high-level of generality (i.e., as a generic PE array including PEs that are connected) such that it amounts to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as a tool to implement the abstract idea. At most, the additional element of “a processing element (PE) array in which a plurality of PEs are connected” is merely generally linking the use of the judicial exception to a particular technological environment or field of use in which the differential values are used for a MAC operation by the PE array. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claim 1 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “a processing element (PE) array in which a plurality of PEs are connected” is recited at a high-level of generality (i.e., as a generic PE array including PEs that are connected) such that it amounts to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as a tool to implement the abstract idea. At most, the additional element of “a processing element (PE) array in which a plurality of PEs are connected” is merely generally linking the use of the judicial exception to a particular technological environment or field of use in which the differential values are used for a MAC operation by the PE array. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under step 2A prong 1, claims 2-4 and 10-13 recite the same abstract idea as claim 1 by reason of dependence. Further, claim 2 recites further of details of the abstract idea of applying the differential values by “only apply the differential values to the first input, and apply the differential values to both of the first and second inputs”; claim 3 recites further of details of the abstract idea of applying the differential values wherein “the differential values are applied to values subsequent to a first value of each of the first and second inputs”; claim 10 recites further the abstract idea of “compensate for the differential values”; claim 11 recites further of details of the abstract idea of compensating for the differential values “uses a previous accumulation value of each column to compensate for the differential values of the second input and uses an accumulation value of a previous column to compensate for the differential values of the first input” which falls within the “Mathematical Concepts” and/or “Mental Processes” grouping of abstract ideas. In particular claims 2-3 do not include additional elements that would require further analysis under step 2A prong 2 and step 2B. Accordingly, the claims are directed to recite an abstract idea.
Under step 2A prong 2, claim 4 recites the following additional elements: the first input is preloaded and set, and the second input is systolically input; claim 10 recites the following additional elements: a compensator; claim 11 recites the following additional elements: the second input which are systolically input and the first input which are preloaded and set; claim 12 recites the following additional elements: wherein the MAC operation is an operation related to deep learning; claim 13 recites the following additional elements: wherein the first input is weights, and the second input is activations which are output from nodes of an input layer or activations which are calculated at nodes of any one hidden layer and output to nodes of a next hidden layer or an output layer. However, the additional element of “a compensator” in claim 10 is recited at a high-level of generality (i.e., as a generic compensator (adder) for compensating (adding) for the differential values) such that it amount to no more than mere instructions using a generic computer component or merely as a tool to implement the abstract idea or merely reciting the words “apply it” (or an equivalent) with the judicial exception. The additional elements of “wherein the MAC operation is an operation related to deep learning” in claim 12; and “wherein the first input is weights, and the second input is activations which are output from nodes of an input layer or activations which are calculated at nodes of any one hidden layer and output to nodes of a next hidden layer or an output layer” in claim 13 are merely generally linking the use of the judicial exception to a particular technological environment or field of use where the MAC operation is used for deep learning and where the first and second inputs are weights and activations for an input or hidden layer of the deep learning. The additional elements of “the first input is preloaded and set, and the second input is systolically input” in claim 4; and “the second input which are systolically input and the first input which are preloaded and set” in claim 11 are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under step 2B, claims 4 and 10-13 do not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a compensator” in claim 10 is recited at a high-level of generality (i.e., as a generic compensator (adder) for compensating (adding) for the differential values) such that it amount to no more than mere instructions using a generic computer component or merely as a tool to implement the abstract idea or merely reciting the words “apply it” (or an equivalent) with the judicial exception. The additional elements of “wherein the MAC operation is an operation related to deep learning” in claim 12; and “wherein the first input is weights, and the second input is activations which are output from nodes of an input layer or activations which are calculated at nodes of any one hidden layer and output to nodes of a next hidden layer or an output layer” in claim 13 are merely generally linking the use of the judicial exception to a particular technological environment or field of use where the MAC operation is used for deep learning and where the first and second inputs are weights and activations for an input or hidden layer of the deep learning. The additional elements of “the first input is preloaded and set, and the second input is systolically input” in claim 4; and “the second input which are systolically input and the first input which are preloaded and set” in claim 11 are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Receiving or transmitting data over a network” and “Storing and retrieving information in memory” as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claims do not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claims do not amount to significantly more than the abstract idea.
Under Step 2A prong 1, claim 14 recites
A device comprising:
a memory; and
a processor configured to use information stored in the memory,
wherein the processor includes a systolic array structure having a processing element (PE) array in which a plurality of PEs are connected, and the systolic array structure performs a multiply and accumulate (MAC) operation by applying differential values to a first input and a second input which are input to each of the PEs.
The above underlined limitations of performing a multiply and accumulate (MAC) operation using differential values amounts to processing mathematical relationships/calculations and falls within the “Mathematical Concepts” and “Mental Processes” grouping of abstract ideas. The step of “perform” is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. That is, other than reciting “systolic array structure”, nothing in the claim element precludes the step from practically being performed in the human mind. For example, but for the “systolic array structure” language, the claim encompasses manually performing multiplication and addition operations using difference values between previous inputs and current inputs as inputs to the multiplication and addition operations as disclosed in at least page 19 and Fig. 9 using pen and paper. Accordingly, the claim is directed to recite an abstract idea.
Under step 2A prong 2, the claim recites the following additional elements: a memory; a processor configured to use information stored in the memory, and wherein the processor includes a systolic array structure having a processing element (PE) array in which a plurality of PEs are connected. However, the additional elements of “a memory”, “a processor” and “a systolic array structure having a processing element (PE) array in which a plurality of PEs are connected” are recited at a high-level of generality (i.e., as a generic memory for storing information; as a generic processor for using the information; and as a generic PE array including PEs that are connected) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. At most, the additional element of “a systolic array structure having a processing element (PE) array in which a plurality of PEs are connected” is merely generally linking the use of the judicial exception to a particular technological environment or field of use in which the differential values are used for a MAC operation by a systolic array structure. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claim 14 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a memory”, “a processor” and “a systolic array structure having a processing element (PE) array in which a plurality of PEs are connected” are recited at a high-level of generality (i.e., as a generic memory for storing information; as a generic processor for using the information; and as a generic PE array including PEs that are connected) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. At most, the additional element of “a systolic array structure having a processing element (PE) array in which a plurality of PEs are connected” is merely generally linking the use of the judicial exception to a particular technological environment or field of use in which the differential values are used for a MAC operation by a systolic array structure. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Regarding claims 15-16 and 20, they recite substantially limitations as claims 2 ,4 and 11 respectively. Claims 2, 4 and 11 analysis applies equally to claims 15-16 and 20 respectively.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-4 and 10-11 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Katayama (US 20090094303 A1).
Regarding claim 1, Katayama teaches a systolic array structure including a processing element (PE) array in which a plurality of PEs are connected (Katayama Figs. 4 and 11 and paragraphs [0041, 0092-0093]; processing element (PE) array (plurality of PEs) – multiplier units),
wherein the systolic array structure performs a multiply and accumulate (MAC) operation by applying differential values to a first input and a second input which are input to each of the PEs (Katayama Figs. 4 and 11-12 and paragraphs [0011-12, 0043, 0092-0095] first input – filter coefficients or input data; second input – the other of the input data or filter coefficients; differential values – difference between previous and current (adjacent) values).
Regarding claim 3, Katayama teaches all the limitations of claim 1 as stated above. Further, Katayama teaches wherein the differential values are applied to values subsequent to a first value of each of the first and second inputs (Katayama Figs. 4 and 11-12 and paragraph [0094]).
Regarding claim 4, Katayama teaches all the limitations of claim 1 as stated above. Further, Katayama teaches wherein, in each of the PEs, the first input is preloaded and set, and the second input is systolically input (Katayama Figs. 11-12 and paragraph [0094]).
Regarding claim 10, Katayama teaches all the limitations of claim 1 as stated above. Further, Katayama teaches further comprising a compensator configured to compensate for the differential values (Katayama Figs. 4 and 11 and paragraph [0066] compensator – circuit which includes the adder 23, the selector 24, the register 25, the adder 26, and the register 27).
Regarding claim 11, Katayama teaches all the limitations of claim 10 as stated above. Further, Katayama teaches wherein the compensator uses a previous accumulation value of each column in the PE array to compensate for the differential values of the second input which are systolically input and uses an accumulation value of a previous column in the PE array to compensate for the differential values of the first input which are preloaded and set (Katayama Figs. 4 and 11-12 and paragraphs [0042-0043, 0066, 0094]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Katayama in view of Vantrease et al. (S 20190294413 A1) hereinafter Vantrease.
Regarding claim 14, Katayama teaches a device comprising:
a processor configured to use information (Katayama Figs. 3-4 and 11 and paragraphs [0037-0038, 0043] processor – 300 or 302/303; information – input data and/or filter coefficients),
wherein the processor includes a systolic array structure having a processing element (PE) array in which a plurality of PEs are connected (Katayama Figs. 4 and 11 and paragraphs [0041, 0092-0093]; processing element (PE) array (plurality of PEs ) – multiplier units), and
the systolic array structure performs a multiply and accumulate (MAC) operation by applying differential values to a first input and a second input which are input to each of the PEs (Katayama Figs. 4 and 11-12 and paragraphs [0011-12, 0043, 0092-0095] first input – filter coefficients or input data; second input – the other of the input data or filter coefficients; differential values – difference between previous and current (adjacent) values).
Katayama does not explicitly teach a memory; and a processor configured to use information stored in the memory.
However, on the same field of endeavor, Vantrease discloses a memory; and a processor configured to use information stored in the memory, wherein the processor includes a systolic array structure having a processing element (PE) array in which a plurality of PEs are connected, and
the systolic array structure performs a multiply and accumulate (MAC) operation (Vantrease Figs. 5-6 and paragraphs [0070, 0073, 0075-0077] memory – 512; processor – 502; PE array – 524/600).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Katayama using Vantrease and include a memory for storing instructions, input data, filter data or other parameters used by the processor and for storing output data of the processor in order to implement a system that may be used to perform neural network operations (Vantrease paragraphs [0070-0071]).
Therefore, the combination of Katayama as modified in view of Vantrease teaches a memory; and a processor configured to use information stored in the memory, wherein the processor includes a systolic array structure having a processing element (PE) array in which a plurality of PEs are connected, and the systolic array structure performs a multiply and accumulate (MAC) operation by applying differential values to a first input and a second input which are input to each of the PEs.
Regarding claim 16, Katayama as modified in view of Vantrease teaches all the limitations of claim 14 as stated above. Further, Katayama as modified in view of Vantrease teaches wherein, in each of the PEs, the first input is preloaded and set, and the second input is systolically input (Katayama Figs. 11-12 and paragraph [0094]).
Regarding claim 20, Katayama as modified in view of Vantrease teaches all the limitations of claim 14 as stated above. Further, Katayama as modified in view of Vantrease teaches further comprising a compensator configured to compensate for the differential values, wherein the compensator uses a previous accumulation value of each column in the PE array to compensate for the differential values of the second input which are systolically input and uses an accumulation value of a previous column in the PE array to compensate for the differential values of the first input which are preloaded and set (Katayama Figs. 4 and 11-12 and paragraph [0042-0043, 0066, 0094] compensator – circuit which includes the adder 23, the selector 24, the register 25, the adder 26, and the register 27).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Katayama as applied to claim 1 above, and further in view of Vantrease.
Regarding claim 12, Katayama teaches all the limitations of claim 1 as stated above. Further, Katayama teaches wherein the MAC operation is an operation (Katayama paragraph [0011-0012, 0043]).
Katayama does not explicitly teach wherein the MAC operation is an operation related to deep learning.
However, on the same field of endeavor, Vantrease discloses a MAC operation related to deep learning (Vantrease Figs. 1-4 and paragraphs [0025, 0030-0031] deep learning – deep neural network or convolutional neural network).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective
filling date of the claimed invention, to modify Katayama using Vantrease and implement the MAC operation of Katayama as part of a computation of an input matrix and a weight matrix in each hidden layer of a neural network in order to implement deep neural networks or convolutional neural networks that can be used for image recognition and/and classification (Vantrease paragraph [0001, 0023, 0040]).
Therefore, the combination of Katayama as modified in view of Vantrease teaches wherein the MAC operation is an operation related to deep learning.
Regarding claim 13, Katayama as modified in view of Vantrease teaches all the limitations of claim 12 as stated above. Further, Katayama as modified in view of Vantrease teaches wherein the first input is weights, and the second input is activations which are output from nodes of an input layer or activations which are calculated at nodes of any one hidden layer and output to nodes of a next hidden layer or an output layer (Vantrease Figs 1-4 and paragraphs [0026, 0030-0031]).
Claims 2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Katayama as applied to claims 1 and 4 above respectively, and further in view of Najafi et al. (US 20210256357 A1), hereinafter Najafi. Najafi is cited in the IDS submitted on 11/19/2024.
Regarding claim 2, Katayama teaches all the limitations of claim 1 as stated above. Further, Katayama teaches wherein the PE array comprises:
PEs configured to apply the differential values to both of the first and second inputs (Katayama Figs. 4 and 11-12 and paragraphs [0043, 0094]).
Katayama does not explicitly teach wherein the PE array comprises: PEs configured to only apply the differential values to the first input.
However, on the same field of endeavor, Najafi discloses only applying differential values to a first input of a MAC operation (Najafi Figs. 1-2 and paragraphs [0041-0044] first input – weights).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Katayama using Najafi and configure the systolic array to include PEs configured to only apply the differential values to the first input in order to minimize the differences between successive weights to reduce the computation time of the multiplications (Najafi paragraphs [0041-0042]). Paragraphs [0043 and 0095] of Katayama also discloses reducing calculation amount and calculation time by using differential values, therefore, it is obvious to apply the differential values to only one or both of the inputs to achieve the reductions in calculation amount and calculation time.
Therefore, the combination of Katayama as modified in view of Najafi teaches wherein the PE array comprises: PEs configured to only apply the differential values to the first input; and PEs configured to apply the differential values to both of the first and second inputs.
Regarding claim 5, Katayama teaches all the limitations of claim 4 as stated above.
Katayama does not explicitly teach wherein reduced processing elements (RPE's) which are PEs disposed in a first column of the PE array have higher bit-precision than RPEs which are PEs disposed in other columns with respect to the first input, and the RPE's and the RPEs have the same bit-precision with respect to the second input.
However, on the same field of endeavor, Najafi discloses only applying differential values to a first input of a MAC operation (Najafi Figs. 1-2 and paragraphs [0041-0044]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Katayama using Najafi and configure the PEs to have the same precision with respect to the second input since the differential values are not applied to the second input, while configuring the other PEs except the first PE to have a lower precision with respect to the first input by recognizing that the differential values applied to the values after the first value have a distribution closer to zero than the original values which can be represented using less number of bits in order to minimize the circuit size (Katayama Fig. 8 and paragraphs [0043, 0073, 0095]).
Therefore, the combination of Katayama as modified in view of Najafi teaches wherein reduced processing elements (RPE's) which are PEs disposed in a first column of the PE array have higher bit-precision than RPEs which are PEs disposed in other columns with respect to the first input, and the RPE's and the RPEs have the same bit-precision with respect to the second input.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Katayama in view of Vantrease as applied to claim 14 above, and further in view of Najafi.
Regarding claim 15, Katayama as modified in view of Vantrease teaches all the limitations of claim 14 as stated above. Further, Katayama as modified in view of Vantrease teaches wherein the PE array comprises:
PEs configured to apply the differential values to both of the first and second inputs (Katayama Figs. 4 and 11-12 and paragraphs [0043, 0094]).
Katayama does not explicitly teach wherein the PE array comprises: PEs configured to only apply the differential values to the first input.
However, on the same field of endeavor, Najafi discloses only applying differential values to a first input of a MAC operation (Najafi Figs. 1-2 and paragraphs [0041-0044] first input – weights).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Katayama using Najafi and configure the systolic array to include PEs configured to only apply the differential values to the first input in order to minimize the differences between successive weights to reduce the computation time of the multiplications (Najafi paragraphs [0041-0042]). Paragraphs [0043 and 0095] of Katayama also discloses reducing calculation amount and calculation time by using differential values, therefore, it is obvious to apply the differential values to only one or both of the inputs to achieve the reductions in calculation amount and calculation time.
Therefore, the combination of Katayama as modified in view of Vantrease and Najafi wherein the PE array comprises: PEs configured to only apply the differential values to the first input; and PEs configured to apply the differential values to both of the first and second inputs.
Allowable Subject Matter
Claims 6-9 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if rewritten to overcome the 35 U.S.C. 112(a) rejection discussed above.
The following is a statement of reasons for the indication of allowable subject matter:
None of the prior art references cited explicitly teach or suggest, in combination with other limitations of the claims, wherein values of the first input of reduced processing elements (RPE's) which are PEs disposed in a first column of the PE array have a smaller number of bits than values of the first input of RPEs which are PEs disposed in other columns, and values of the second input of the RPE's and values of the second input of the RPEs have the same number of bits as recited in claims 6 and 17.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bayat (US 11409356 B1) discloses calculating f(B,W) indirectly first calculating f(A,W), subtracting B−A, calculating f(B−A, W), then adding f(B−A, W) and f(A, W) to calculate f(B, W) (i.e., applying differential values) where A is a previous input and B is the current input.
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/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
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