ucatNotice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to Applicant’s reply filed 07/31/2026 to the non-final Office Action mailed 04/03/2026 (the “prior action”). In the reply, claims 1, 8 and 15 were amended and claim 17 was amended to depend from claim 16. The amendment has been entered. This application has been examined. Claims 1-20 are pending.
The rejection of claims 1, 8 and 15 under 35 U.S.C. 102(a)(1) over Bodas et al. is maintained with a revised and corrected mapping set forth below. The rejection of claims 3-7, 9-14 and 16-20 under 35 U.S.C. 103 over Bodas in view of Kaburlasos et al. (US 2016/0054782) is withdrawn. As Applicant correctly observed (Remarks, p. 9), that rejection’s heading omitted claim 2 while its body discussed claim 2, and the discussions of claims 2, 5, 9, 11, 12, 16 and 19 did not address the limitations those claims actually recite. The dependent claims are therefore rejected on new grounds (Bodas in view of Jasoliya, US 10,699,369) that were not necessitated by Applicant’s amendment, which only clarified wording (“while the computing circuitry is executing”). Accordingly, this action is made NON-FINAL. See MPEP 706.07(a).
Claim Interpretation
3. The claims have been reviewed for compliance with 35 U.S.C. 112(a) and (b), and no rejection under 35 U.S.C. 112 is made. The term “system management circuitry” is not treated as invoking 35 U.S.C. 112(f) because “circuitry” connotes sufficiently definite structure to one of ordinary skill in the art. See MPEP 2181(I). An antecedent-basis review of the amended claims found no deficiency; in particular, “the set of tasks” in claims 10 and 17 has antecedent basis in claims 8 and 15, respectively, and “the at least one operating frequency” in claim 19 has antecedent basis in claim 18.
Under the broadest reasonable interpretation (BRI) consistent with the specification, “record” is given its ordinary meaning of storing or retaining a value for later use. The specification states that the recorded frequencies may be stored “in a data array or any other predetermined memory location” (Spec. ¶ [0013]). Nothing in claims 1, 8 or 15 requires the recorded value to be a measured quantity, as opposed to the frequency setting at which the circuitry operated during the first task. “Task” is not limited to rendering a frame; the specification describes tasks generically and gives frame rendering only as an example (Spec. ¶¶ [0013], [0055]).
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1, 6, 8, 13 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bodas et al., (“Bodas”) (U.S. Pub No. 2016/0054780, published February 25, 2016). Bodas published more than one year before the December 27, 2022 effective filing date of the claimed invention, so no exception under 35 U.S.C. 102(b)(1) applies.
The examiner relies on the entire teachings of the Bodas reference; the applicant should carefully consider the entire teachings of the above-mentioned reference to better understand the examiner’s position.
Regarding claim 1,
Bodas teaches a system comprising: system management circuitry configured to: - data processing system 101 comprising nodes, where “each of the nodes, such as nodes 103, 104 and 105 comprises one or more processors, one or more controllers, or both coupled to a memory,” and head node 102 “comprises a resource manager having at least a portion of a power aware job scheduler and manager 113 stored in the memory” (Bodas ¶ [0049]; Fig. 1). The power aware job scheduler and manager includes calibrator 306, estimator 305 and job manager 312 (Bodas ¶¶ [0066]-[0067]; Fig. 3), and job manager 407 “obtains and sets processor register values related to the processor frequency via the OS MSR module” (Bodas ¶ [0077]). The processor(s) of head node 102 executing scheduler and manager 113 are system management circuitry under BRI; Applicant’s specification likewise states that the system management unit “may be a system management circuit or system management circuitry” (Spec. ¶ [0013]);
record one or more first operating frequencies of computing circuitry while the computing circuitry is executing a first task; and - calibrator 306 runs “a sample workload (e.g., a mini-application and/or a test script)” on every node, and “the sample workload may be run on each node at every operating frequency of the node” (Bodas ¶ [0067]). The calibrator’s inputs include a “List of frequencies (F1, F2, ... Fn),” and its “Output [is] saved in database” “For each frequency”: “Power (workload-Max, Workload-average),” “Temperature” and “Time of completion” (Bodas ¶¶ [0146]-[0156]). Similarly, “the processor frequency is varied across a plurality of representative mini-applications. For each frequency an average power, a maximum power, a power deviation, and a time to completion of the job are stored in a database” (Bodas ¶ [0104]). The stored calibration tables are organized “per compute node at different frequencies” (Bodas ¶ [0138]; Fig. 9A, tables 911-913). Calibration can also occur “during the run-time of a job” on “the one or more nodes on which a job is running” (Bodas ¶ [0068]). The sample workload (mini-application) reads on the first task, and the node processor that runs it reads on the computing circuitry. Each frequency F1…Fn at which the node executed the workload is stored in the calibration database as the key of that record, which reads on recording one or more first operating frequencies while the computing circuitry is executing a first task;
execute a second task with one or more second operating frequencies, wherein the one or more second operating frequencies are selected for executing the second task based at least in part on the one or more first operating frequencies - Bodas’ Frequency Estimator (Estimator-F) receives, as input, a workload that the user indicates “from list of sample workloads that is closer to application,” together with the available power and power levels, and outputs “Frequency of operation Fs” plus the job power at Fs and at the frequencies one bin above and below Fs (Bodas ¶¶ [0165]-[0173]). “Based upon available power, the scheduler calculates a best frequency for a job” using “a power-performance table” (Bodas ¶ [0131]). In fixed-frequency mode, the user’s selection “may be based upon a table that indicates a performance and power for each frequency” (Bodas ¶ [0130]). The job is then run at the determined frequency (Bodas ¶ [0111]; Fig. 5B, operation 523), and job manager 407 sets the processor frequency through the MSR module (Bodas ¶ [0077]). At run time, the decision to hop from frequency Fo to the next bin uses the calibrated average power “at a one bin higher frequency P(Fo+1)” and “at a current frequency Fo (Pfo)” (Bodas ¶ [0136]). The user job reads on the second task. Fs is selected from the calibrated frequencies F1…Fn using the power and completion data stored against each of those frequencies, so the selection is based at least in part on the recorded first operating frequencies; the claim requires no more than a partial dependency.
Regarding claim 6,
Bodas teaches the system of claim 1, as set forth above. Bodas further teaches wherein the system management circuitry is further configured to record a power state associated with the computing circuitry - for each calibrated frequency, Bodas saves the node’s power (workload-maximum and workload-average) and temperature to the database (Bodas ¶¶ [0152]-[0155]; ¶ [0104]). For each available frequency, from 1.2 GHz through “a nominal frequency (P1 frequency), and a turbo frequency,” Bodas also determines the maximum node power (PMP) (Bodas ¶ [0069]). See also the per-frequency average-power and maximum-power calibration tables (Bodas ¶ [0138]; Fig. 9A). Applicant’s specification does not define “power state” restrictively (see Spec. ¶ [0038]). Under BRI, the recorded power-consumption level of the circuitry at a given frequency or P-state operating point is a power state associated with the computing circuitry.
Regarding claim 8,
Claim 8 recites a method whose steps correspond to the functions of the system of claim 1, and it is rejected for the same reasons. Bodas teaches a method comprising: recording, by processing circuitry, one or more first operating frequencies of computing circuitry while the computing circuitry is executing a first task from a set of tasks - the processors of head node 102 executing scheduler and manager 113 (Bodas ¶ [0049]) run the sample workload at every operating frequency F1…Fn, with the output for each frequency saved in a database (Bodas ¶¶ [0067], [0104], [0146]-[0156]), including during run-time calibration (Bodas ¶ [0068]); and executing, by the processing circuitry, a second task from the set of tasks, with one or more second operating frequencies, wherein the one or more second operating frequencies are selected for executing the second task based at least in part on the one or more first operating frequencies - Estimator-F outputs frequency of operation Fs (Bodas ¶¶ [0165]-[0173]), selected from the per-frequency power-performance table (Bodas ¶¶ [0130]-[0131]), the job is run at that frequency (Bodas ¶ [0111], operation 523) as set via the MSR module (Bodas ¶ [0077]), and the run-time hop compares P(Fo+1) with P(Fo) (Bodas ¶ [0136]), as set forth for claim 1. As to the additional recitation that the first and second tasks are both from a set of tasks, Bodas’ calibration runs sample workloads, i.e., “a plurality of representative mini-applications” (Bodas ¶¶ [0067], [0104], [0148]), and the user’s job is associated with a workload the user indicates “from list of sample workloads that is closer to application” (Bodas ¶¶ [0158], [0167]). The calibration workload and the job are thus both drawn from the same set of workloads run on data processing system 101.
Regarding claim 13,
Bodas teaches the method of claim 8, as set forth above. Bodas further teaches wherein the one or more second operating frequencies are operating frequencies that were recorded during execution of the first task - the frequency of operation Fs output by Estimator-F (Bodas ¶¶ [0172]-[0173]) is one of the frequencies in the calibration “List of frequencies (F1, F2, ... Fn)” whose results were saved “For each frequency” while the sample workload ran (Bodas ¶¶ [0151]-[0153]). Likewise, in fixed-frequency mode the job frequency is chosen from “a table that indicates a performance and power for each frequency” (Bodas ¶ [0130]), and at run time the next frequency is the calibrated frequency one bin higher, Fo+1 (Bodas ¶ [0136]). The second operating frequency is therefore a frequency that was recorded during execution of the first task.
Regarding claim 14,
Bodas teaches the method of claim 8, as set forth above. Bodas further teaches wherein the one or more first operating frequencies are recorded while a power management mode is enabled - Bodas’ calibrator can calibrate “during the run-time of a job,” sampling “the one or more nodes on which a job is running” (Bodas ¶ [0068]). Jobs run under user-selected power policies (Bodas ¶ [0108]), including min-power, max-power and auto modes, in which “[w]ith dynamic power monitoring, a workload manager adjusts the uniform frequency periodically based upon a power headroom” (Bodas ¶ [0132]; see also ¶¶ [0112], [0131]). Run-time calibration of a job executing in such a mode records frequencies while a power management mode is enabled.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. § 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
7. Claims 2, 5, 7, 9, 11, 12, 15, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bodas et al., (“Bodas”) (U.S. Pub No. 2016/0054780) in view of Jasoliya, (“Jasoliya”) (U.S. Patent No. 10,699,369, filed December 27, 2017; published as U.S. Pub No. 2019/0197658 on June 27, 2019). Jasoliya is prior art under 35 U.S.C. 102(a)(1).
The examiner relies on the entire teachings of the Bodas and Jasoliya references; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
Regarding claim 2,
Bodas teaches the system of claim 1, as set forth above, and records the first operating frequencies (Bodas ¶¶ [0067]-[0068], [0104], [0146]-[0156]), performing calibration at launch time and at run time (Bodas ¶¶ [0067]-[0068]). Bodas does not teach wherein the system management circuitry is configured to record the one or more first operating frequencies of the computing circuitry, responsive to detection of a recording condition.
In the same field of endeavor, Jasoliya teaches that “at operation 1702, the Nth frame start is detected (where N can be a programmable value for sampling frame at regular interval …). Once the Nth frame start is detected, operation 1704 collects information” (Jasoliya col. 31:10-17; Fig. 17); see also Fig. 16, where “at frame start, operation 1602 starts the histogram generator logic” (Jasoliya col. 29:58-60). Detection of the Nth frame start is a detected recording condition that initiates the recording.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply Jasoliya’s frame-triggered, frame-granular history collection to Bodas’ frequency recording and frequency selection. Bodas and Jasoliya are analogous art, both being in the same field of endeavor as the claimed invention, namely processor power management by dynamic voltage and frequency scaling (DVFS) that selects an operating frequency using previously stored operating history (Bodas ¶¶ [0104], [0131]; Jasoliya col. 28:10-25). Bodas expressly contemplates that the managed processor 410 is “a graphics processing unit (GPU)” (Bodas ¶ [0077]). Jasoliya teaches that, for graphics workloads, “there is strong correlation between (e.g., consecutive) frames,” so that a metric recording “last frames bandwidth profile information” can be used “for improved prediction of the next frame” (Jasoliya col. 28:26-34), and Jasoliya accordingly collects that history on detected trigger frames, stores it, and reuses it “for the next N frames” to reach a better power/performance tradeoff (Jasoliya col. 30:38-50; col. 31:10-20). The resulting system would capture operating history at the granularity at which graphics workloads repeat and would improve power/performance, as Jasoliya teaches. The modification is the use of known techniques to improve similar devices in the same way, yielding predictable results. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007); MPEP § 2143(I)(C), (G). One of ordinary skill would have had a reasonable expectation of success because both references are Intel DVFS disclosures that already store operating data and select frequencies from it.
Regarding claim 5,
Bodas teaches the system of claim 1, as set forth above, and further teaches storing the recorded frequencies with their power and completion results in a database (Bodas ¶¶ [0104], [0152]-[0156]) and in per-frequency calibration tables 911-913 (Bodas ¶ [0138]; Fig. 9A), i.e., store the recorded one or more first operating frequencies in a data structure.
Bodas does not teach wherein the data structure at least in part stores one or more portions of a frame and corresponding operating frequencies recorded when rendering each portion.
In the same field of endeavor, Jasoliya builds a frame-level histogram in which each bin, SA_BW_HIST[x], is indexed by a DVFS frequency level x (Jasoliya col. 29:23-49); the histogram “is generated (and stored in memory …) for a single frame and used for the next N frames” (Jasoliya col. 30:38-50). Jasoliya further teaches that “rather than just taking the histogram at frame boundaries into account …, tile pass boundaries and/or render pass boundaries may be taken into account,” providing “better visibility in various phases of work in the frame” (Jasoliya col. 30:l-31:2), and collects heuristics per tile pass or render pass (Jasoliya col. 31:20-29; Fig. 17, operations 1708-1714). Tile passes and render passes are portions of a frame, and Jasoliya stores frequency-indexed data for each of them. In Jasoliya the per-portion entries are frequency-level bins of bandwidth demand, whereas Bodas supplies the recorded operating frequencies themselves; combining the two yields a data structure that associates each rendered portion of a frame with the operating frequency recorded while rendering it.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to organize Bodas’ recorded-frequency data structure at the render-pass/tile-pass granularity taught by Jasoliya, because Jasoliya teaches that pass-level history “may provide an even better visibility in various phases of work in the frame, resulting in a better overall frequency selection” (Jasoliya col. 30: -col. 31:2), for the reasons and with the reasonable expectation of success set forth for claim 2. MPEP § 2143(I)(C), (G).
Regarding claim 7,
Bodas teaches the system of claim 1, as set forth above. Bodas’ calibrator samples parameters “at predetermined time intervals” while the sample workload runs (Bodas ¶ [0067]), and the power aware scheduler and manager “runs at launch time and also at a programmable interval,” re-evaluating frequency selection in each control period (Bodas ¶ [0134]).
Bodas does not expressly teach wherein the one or more first operating frequencies are recorded at predetermined periodic intervals.
In the same field of endeavor, Jasoliya teaches that its collection operation “is run, e.g., periodically (such as every 100 microseconds)” (Jasoliya col. 29:25-27), and that collection is triggered on “the Nth frame … sampling frame at regular interval. For example every 10th frame if N=10” (Jasoliya col. 31:10-13; see also col. 30:12-20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform Bodas’ recording at the predetermined periodic intervals taught by Jasoliya so that the stored history stays current as workload behavior changes (Jasoliya col. 30:12-20), for the reasons and with the reasonable expectation of success set forth for claim 2. MPEP § 2143(I)(C), (G).
Regarding claim 9,
Bodas teaches the method of claim 8, as set forth above, including recording the first operating frequencies (Bodas ¶¶ [0067]-[0068], [0104], [0146]-[0156]). Bodas does not teach recording, by the processing circuitry the one or more first operating frequencies responsive to initiation of a recording condition. In the same field of endeavor, Jasoliya teaches detecting the Nth frame start and, once it is detected, collecting information (Jasoliya col. 31:10-17; Fig. 17; see also col. 29:58-60; Fig. 16), which reads on recording responsive to initiation of a recording condition, as set forth for claim 2. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Bodas and Jasoliya for the reasons, and with the reasonable expectation of success, set forth for claim 2.
Regarding claim 11,
Bodas in view of Jasoliya teaches the method of claim 9, as set forth above. Bodas’ jobs run under power-management modes in which the workload manager dynamically raises and lowers frequency (Bodas ¶¶ [0131]-[0132]).
Bodas does not teach disabling, by the processing circuitry, a power management mode for the computing circuitry responsive to initiation of the recording condition.
In the same field of endeavor, Jasoliya teaches: “Once the Nth frame start is detected, operation 1704 collects information and turns off DVFS so the system agent can run at the highest voltage/frequency. This mode is referred as heuristics collection mode” (Jasoliya col. 31:13-17). Likewise, “[w]hile collecting histogram, SAGV is disabled and highest DVFS frequency point is chosen to obtain unconstrained bandwidth profile” (Jasoliya col. 29:15-18). DVFS/SAGV is a power management mode, and it is disabled responsive to initiation of the recording condition.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to disable Bodas’ dynamic frequency management during recording, as Jasoliya teaches, so that the recorded history is “unconstrained” and not distorted by concurrent power-management frequency changes (Jasoliya col. 29:15-18), for the reasons and with the reasonable expectation of success set forth for claim 2. MPEP § 2143(I)(C), (G).
Regarding claim 12,
Claim 12 recites, in method form, the data-structure limitation of claim 5. Bodas teaches the method of claim 8, as set forth above, and stores the recorded frequencies in a database and per-frequency calibration tables (Bodas ¶¶ [0104], [0138], [0152]-[0156]; Fig. 9A).
Bodas does not teach that the data structure at least in part stores one or more portions of a frame and corresponding operating frequencies recorded when rendering each portion.
In the same field of endeavor, Jasoliya teaches frequency-indexed histogram data stored per frame and per tile pass or render pass (Jasoliya col. 29:23-49; col. 30:38-50; col. 30, l. 62 - col. 31, l. 2; col. 31:20-29; Fig. 17), as set forth for claim 5.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Bodas and Jasoliya for the reasons, and with the reasonable expectation of success, set forth for claims 2 and 5.
Regarding claim 15,
Bodas teaches a computing system comprising: a central processing unit comprising circuitry; - Bodas’ data processing system includes “a central processing unit (CPU) node 103 and a CPU node 104” (Bodas ¶ [0049]), and processor 410 “is a CPU” (Bodas ¶ [0077]);
a memory controller comprising circuitry; and - Bodas’ nodes comprise “one or more processors, one or more controllers, or both coupled to a memory” (Bodas ¶ [0049]);
system management circuitry configured to: record one or more first operating frequencies of computing circuitry while the computing circuitry is executing a first task from a set of tasks; and execute a second task from the set of tasks, with one or more second operating frequencies, wherein the one or more second operating frequencies are selected for executing the second task based at least in part on the one or more first operating frequencies - as set forth for claims 1 and 8 (Bodas ¶ [0049]; ¶¶ [0067]-[0068], [0104], [0138], [0146]-[0156] (recording); ¶¶ [0104], [0148], [0158], [0167] (set of tasks); ¶¶ [0077], [0111], [0130]-[0131], [0136], [0165]-[0173] (selection and execution)).
Bodas does not expressly teach a memory controller comprising circuitry.
In the same field of endeavor, Jasoliya teaches that processor 102 includes “an integrated memory controller 116,” which “facilitates communication between a memory device and other components of the system” (Jasoliya col. 4:49-53; Fig. 1), and that system agent core 210 includes “one or more integrated memory controllers 214” and a power control unit (PCU) that regulates “the power state of processor cores 202A-202N and graphics processor 208” (Jasoliya col. 6:12-26; Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include in Bodas’ CPU-based computing system a memory controller comprising circuitry, as taught by Jasoliya, because a memory controller is the conventional circuit that couples processors to the memory to which Bodas’ processors are already coupled (Bodas ¶ [0049]; Jasoliya col. 4:49-53). This is a combination of known elements according to known methods, yielding predictable results. MPEP § 2143(I)(A). The references are further combinable for the reasons, and with the reasonable expectation of success, set forth for claim 2.
Regarding claim 16,
Claim 16 recites, for the computing system of claim 15, the same limitation as claim 2 (record the one or more first operating frequencies of the computing circuitry, responsive to detection of a recording condition). Bodas in view of Jasoliya teaches the computing system of claim 15, as set forth above. Bodas does not teach recording responsive to detection of a recording condition. In the same field of endeavor, Jasoliya teaches detecting the Nth frame start and then collecting information (Jasoliya col. 31:10-17; col. 29:58-60). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Bodas and Jasoliya for the reasons, and with the reasonable expectation of success, set forth for claims 2 and 15.
Regarding claim 20,
Claim 20 recites, for the computing system of claim 15, the same limitation as claim 7 (wherein the one or more first operating frequencies are recorded at predetermined periodic intervals). Bodas in view of Jasoliya teaches the computing system of claim 15, as set forth above, and Bodas samples at predetermined time intervals and runs its scheduler at a programmable interval (Bodas ¶¶ [0067], [0134]). Bodas does not expressly teach recording the operating frequencies at predetermined periodic intervals. In the same field of endeavor, Jasoliya teaches periodic collection “such as every 100 microseconds” and collection on every Nth frame (Jasoliya col. 29:25-27; col. 31:10-13; col. 30:12-20). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Bodas and Jasoliya for the reasons, and with the reasonable expectation of success, set forth for claims 2, 7 and 15.
Allowable Subject Matter
8. Claims 3, 4, 10, 17, 18 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims (and, for claim 17, upon correction of the objection to intervening claim 16).
9. The following is a statement of reasons for the indication of allowable subject matter. The prior art of record, alone or in combination, does not teach or reasonably suggest:
• Claims 3 and 19: recording the first operating frequencies responsive to the computing circuitry operating at a threshold operating frequency (claim 19: the at-least-one operating frequency) when executing each of a plurality of tasks preceding the first task, i.e., recording that is gated on the frequency having settled across successive preceding tasks. Bodas records at fixed calibration frequencies (Bodas ¶ [0067]), and Jasoliya triggers on a frame count (Jasoliya col. 31:10-13). Neither conditions recording on the circuitry having operated at a threshold frequency for each of a plurality of preceding tasks.
• Claims 4 and 18: responsive to the recording condition, disabling a power management mode until one or more previously accumulated power credits are consumed (claim 4), or inspecting consumption of a power credit as an indication that an operating frequency has reached a threshold value (claim 18). Jasoliya disables DVFS for the duration of the collection frame to obtain an unconstrained profile (Jasoliya col. 31:13-17); it does not hold the mode disabled until accumulated unused power budget is drained, and it does not use credit consumption as a stability indicator. Bodas tracks stranded or unused power (Bodas ¶ [0007]) but reallocates it (Bodas ¶¶ [0139]-[0140]) rather than using its consumption to time the recording.
• Claims 10 and 17: a recording condition that includes detecting a change in a characteristic of the set of tasks comprising at least a frame length. Jasoliya’s trigger is the Nth frame start, not a change in frame length. Mondjak (US 9,424,620, cited below) flags frame-to-frame changes in GPU phase content (col. 4, l. 59 - col. 5, l. 4) and records phase length (col. 6:5-7), but does not detect a change in frame length as a condition for recording operating frequencies.
Response to Arguments
10. Applicant’s arguments filed 07/31/2026 have been fully considered. They are persuasive in part and not persuasive in part, as follows.
(a) Bodas item 402 and ¶¶ [0076]-[0077] (Remarks, p. 7). Persuasive in part. Item 402 is a node, not a recording operation, and ¶¶ [0076]-[0077] describe communicating and setting a frequency value rather than recording one while a task executes. The prior action’s reliance on those passages for the “record” limitation is withdrawn. The maintained rejection relies instead on calibrator 306 (Bodas ¶¶ [0067]-[0068], [0104], [0138], [0146]-[0156]). Paragraph [0077] is now cited only for setting the selected frequency when executing the second task.
(b) Calibration frequencies as mere “operating conditions” (Remarks, p. 7). Not persuasive. Applicant argues that Bodas’ calibration frequencies are “operating conditions under which power and performance are determined” rather than recorded operating frequencies. The claims do not require the frequency to be measured, as opposed to being the setting at which the circuitry operated, and they do not exclude a frequency that also serves as the condition of a test. Bodas runs the sample workload “at every operating frequency of the node” (Bodas ¶ [0067]) and saves results to a database “For each frequency” of the list F1…Fn (Bodas ¶¶ [0151]-[0153]; see also ¶ [0104]). Storing the frequency at which the node executed the workload, as the key of the stored record, is recording an operating frequency of the computing circuitry while it executes the first task. See the claim interpretation above; In re Van Geuns, 988 F.2d 1181, 1184 (Fed. Cir. 1993) (limitations from the specification are not read into the claims).
(c) Selection “based at least in part on” the recorded frequency (Remarks, pp. 7-8). Not persuasive. Applicant argues that Bodas selects frequency based on available power rather than on the recorded frequencies. Bodas’ Estimator-F selects Fs from among the calibrated frequencies, using the power recorded against each one (Bodas ¶¶ [0165]-[0173]; see also ¶¶ [0130]-[0131]), and its run-time hop decision compares the recorded power at Fo+1 with the power at Fo (Bodas ¶ [0136]). A selection made among the recorded frequencies, using data keyed to them, is based “at least in part” on those frequencies. That available power also informs the selection does not negate this, because the claims recite an open-ended, partial basis. Applicant’s own dependent claim 13, under which the second frequencies may simply be the recorded ones, confirms that claim 1 covers selecting a recorded frequency.
(d) Irregularities in the prior § 103 rejection (Remarks, p. 9). Persuasive. That rejection is withdrawn and replaced by the new grounds above, and this action is made non-final.
(e) Claims 4 and 18 (Remarks, p. 9) and claims 10 and 17 (Remarks, p. 10). Persuasive. These claims are indicated as containing allowable subject matter (see above).
(f) Claims 5, 11, 12 and 13 (Remarks, p. 10). Moot in view of the new grounds of rejection. Claims 5, 11 and 12 are now rejected over Bodas in view of Jasoliya, and claim 13 is rejected as anticipated by Bodas, for the reasons stated above.
Examiner's note:
Applicant is reminded that the Examiner has cited particular columns, line numbers, and paragraphs in the applied references for the convenience of the Applicant; other passages and figures of Man and Blaine may apply as well, and Applicant is encouraged to consider the references in their entirety.
In the interest of compact prosecution, the examiner further notes the following:
• Independent claims. The anticipation of claims 1, 8 and 15 turns on reading Bodas’ per-frequency calibration record as “recording” a frequency “while executing” a first task. As an independent alternative, Mondjak (US 9,424,620) (teaches that a GPU phase “inherits” the frequency setting of its immediately preceding phase, that “[t]he GPU’s current frequency is the GPU frequency that was used to process the immediately preceding phase,” and that the frequency for the current phase is changed only if a desirable frequency is not “sufficiently close” to that prior frequency (col. 6:1-30). Mondjak also keeps per-frame-interval phase data in a phase profile database (col. 4:22-28). If Applicant amends to require the recorded value to be a measured run-time frequency, Mondjak is a candidate replacement primary reference.
• Claim 6 (“power state”). This rejection reads recorded per-frequency power levels and P1/turbo operating points as a “power state.” A definitional amendment (e.g., an ACPI P-state or C-state identifier) would require a further search.
• Claims 5 and 12. This is a two-reference combination in which Jasoliya supplies frame-portion granularity and Bodas supplies the recorded frequency.
• Disclosed inventive concept. The specification’s disclosed contribution is at ¶¶ [0039]-[0043], [0057]-[0060] and [0073]-[0076]: a change in frame length triggers recording; the power-management (throttling) mode is then disabled so that any accumulated power credit drains; the frequency is recorded once it stabilizes, indicated by consecutive frames having the same render time or starting frequency; and the stable frequency is used as a reference operating point for similar subsequent frames so that newly generated credit is reserved for frequency-sensitive work. Claims 3, 4, 10 and 17-19 capture parts of this sequence. An independent claim combining the frame-length recording trigger (claims 10/17) with disabling the power-management mode until accumulated power credits are consumed (claims 4/18) would distinguish over the art of record.
Conclusion
11. Claims 1, 2, 5-9, 11-16 and 20 are rejected. Claims 3, 4, 10 and 17-19 are objected to as depending from a rejected base claim, and claim 16 is further objected to for an informality.
12. The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
U.S. Patent No. 9,424,620 (Mondjak et al.), discloses GPU frame phases tracked in a phase profile database per frame processing interval, each phase inheriting the frequency used for the immediately preceding phase, with the frequency changed only if the desired frequency differs sufficiently (col. 4:22-28; col. 6:1-30).
U.S. Pub No. 2016/0054782 (Kaburlasos et al.), of record and previously applied, discloses predicting graphics utilization from prior-frame utilization patterns.
U.S. Patent No. 11,263,044 (Nijasure et al.), discloses adjusting a GPU clock to a stored per-program specified frequency upon identifying the program thread that generated the workload.
U.S. Patent No. 9,310,872 (Aelion et al.), discloses controlling processor clock frequency on the basis of the current frame rate, a target frame rate, and load.
U.S. Patent No. 10,319,065, discloses intra-frame GPU frequency control using a moving average of prior frames’ rendering times to estimate current-frame completion.
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
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/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175
Prosecution Insights