Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 30, 2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Briere (US 20120235209 A1) in further view of Le (US 20210074702 A1) and further evidenced by Decoutere (US 20200203274 A1).
Regarding Claim 1, Briere teaches a III-N transistor (104, see also [0023]) connected in cascade (shown Fig. 1A) with a silicon transistor (102, see also [0024]), wherein a drain (124) of the group III-N based transistor is connected to the input (shown connected in parallel with input current 120), a drain (112) of the transistor is connected to a source (122) of the group III-N based transistor, a source (110) of the transistor is connected to a gate (G2, connected at node 108) of the group III-N based transistor and the output (shown, wherein an output voltage is at terminal 114), a gate of the transistor (G1) is configured to receive a control signal (see [0020]), and the control signal is configured to turn on or turn off the transistor (see [0035] which further describes gate terminal 218, corresponding to the gate terminal 118 of Fig. 1A as a “control terminal” which is understood to control the on/off state of the switch).
Briere does not explicitly teach the silicon transistor being a thin-film transistor stacked on the group III-N based transistor.
Le teaches a group III-N based semiconductor three-dimensional (3D) integrated circuit (see Fig. 2) configured as a CMOS inverter (see [0017]) comprising:
a group Ill-N based transistor (104, see [0025]): and
a thin-film transistor (102, see also [0023]), stacked on the group Ill-N based transistor (shown Fig. 2) and electrically connected to the group III-N based transistor (connected via interconnect 294, shown Fig. 2).
The device of Le gives an example of a III-N based semiconductor 3D integrated circuit configured as an inverter circuit. However, one of ordinary skill in the art would be capable of implementing the teachings of Le toward other circuit designs depending on the desired application (i.e., the cascade circuit of Briere, see also evidenced in Decoutere: [0040]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the cascade circuit of Briere to be monolithically integrated as disclosed by Le as this would enable smaller device footprints and higher density circuits (see also Le: [0062]).
More specifically, Briere as applied to Le would teach a group III-N based semiconductor three-dimensional (3D) integrated circuit comprising:
a group III-N based transistor; and
a thin-film transistor, stacked on the group III-N based transistor and electrically connected to the group III-N based transistor;
an input and an output, wherein a drain of the group III-N based transistor is connected to the input, a drain of the thin-film transistor is connected to a source of the group III-N based transistor, a source of the thin-film transistor is connected to a gate of the group III-N based transistor and the output, a gate of the thin-film transistor is configured to receive a control signal, and the control signal is configured to turn on or turn off the thin-film transistor.
Regarding Claim 3, Briere as modified by Le teaches the group III-N based semiconductor 3D integrated circuit according to claim 1, wherein the group III-N based transistor comprises a GaN metal-insulator-semiconductor high electron mobility transistor (see Le: [0025]).
Response to Arguments
Applicant's arguments filed January 30, 2026 have been fully considered but they are not persuasive.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant argues that the silicon-based enhancement-mode FET of Briere is not analogous to the enhancement-mode thin film transistor of Le and thus the teachings of Le and Briere cannot be combined. Examiner respectfully disagrees and notes that the design of Le would be obvious to implement in many complementary transistor configurations, such as the cascade circuit configuration of Briere as this would reduce device footprint (see also Le: [0062]).
Applicant further argues that the circuit of Le could not be modified into the circuit configuration shown in Fig. 1A of Briere. Examiner notes that the circuit configuration taught be Le is dependent on the disposition of the interconnect structure, which is being implemented as a common CMOS inverter in Le. Examiner respectfully disagrees and notes that the circuit configuration of Briere is not being modified, but rather the circuit is being monolithically integrated as suggested by Le to advantageously reduce device footprint.
Conclusion
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/C.P.B./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893