DETAILED ACTION
This Office Action is in response to the Applicant Election filed on 04/02/2026.
Currently, claims 1-20 are pending in the application. Currently, claims 15-20 are withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 1-14) in the reply filed on 04/02/2026 is acknowledged. Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-selected invention, there being no allowable generic or linking claim. Claims 1-14 are examined in this Office action.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/27/2022 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 6 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation “a buffer layer positioned between the buffer layer and a backside of the adjacent source and drain region”. It is unclear if the buffer layer recited in claim 5 is the same or different as the buffer layer established in claim 1. Therefore, the claim has an indefinite scope. For the purpose of examination, this limitation will be read as requiring a second buffer layer between the buffer layer of claim 1 and a backside of the adjacent source and drain region.
Claim 10 recites the limitation “the first controlled opening in the first controlled opening.” It is unclear how an opening can be inside of itself. Therefore, the claim has an indefinite scope. For the purpose of examination, this limitation will be read as “the first controlled opening”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-5, 7-8, and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LEE et al. (US Pub. No. 2024/0096984).
Regarding independent claim 1, Lee teaches a semiconductor device (Fig. 0), comprising:
a transistor device (Fig. 2, ¶ [0019]), including:
a source and drain region (Fig. 2, 126_1, ¶ [0021]); and
a gate region (Fig. 2, 129, ¶ [0021]);
a bottom dielectric isolation layer (Fig. 2, 114, ¶ [0019]) on a backside (Fig. 2, area of Lee’s device below a bottom surface of 126_1) of the transistor device;
a buffer layer (Fig. 2, 112, ¶ [0019]) on a backside (Fig. 2, bottom of backside insulator 114) of the bottom dielectric isolation layer;
a first conductive contact (Fig. 2, 162, ¶ [0028]) positioned on the backside of the transistor device in contact with a backside of the source and drain region (Fig. 2, side of 126_1 in contact with 162), through the bottom dielectric isolation layer and through the buffer layer; and
a second conductive contact (Fig. 2, 145, ¶ [0026]) in contact with the gate region (Fig. 2, ¶ [0026]) from a frontside of the gate region (Fig. 2, top side of 129).
Regarding claim 4, Lee teaches the semiconductor device of claim 1, and Lee teaches that the bottom dielectric isolation layer (Fig. 2, 114, ¶ [0019]) is in position to isolate (Fig. 2) the first conductive contact (Fig. 2, 162, ¶ [0028]) from the gate region (Fig. 2, 129, ¶ [0021]).
Regarding claim 5, Lee teaches the semiconductor device of claim 1, and Lee teaches that the bottom dielectric isolation layer (Fig. 2, 114, ¶ [0019]) is in position to isolate (Fig. 2) the first conductive contact (Fig. 2, 162, ¶ [0028]) from an adjacent source and drain region (Fig. 2, 126_2, ¶ [0021]).
Regarding claim 7, Lee teaches the semiconductor device of claim 1, and Lee teaches that the transistor device (Fig. 2) includes a stack of nanosheets (Fig. 2, 122, ¶ [0022] teaches that channel regions 122 can be nanosheets).
Regarding claim 8, Lee teaches a semiconductor device, comprising:
a transistor device (Figs. 1-2, TR, ¶ [0021] teaches a transistor structure) in a front end of line layer (Fig. 2, area of 114, 122, 129, 126_1, and 126_2, ¶¶ [0019] & [0021] ), including:
a source and drain region (Fig. 2, 126_1, ¶ [0021]); and
a gate region (Fig. 2, 129, ¶ [0021]);
a bottom dielectric isolation layer (Fig. 2, 114, ¶ [0019]) in the front end of line layer and on a backside (Fig. 2, area of Lee’s device below a bottom surface of 126_1) of the transistor device;
a first sacrificial layer (Fig. 3, 112, ¶ [0019]) on a backside of the bottom dielectric isolation layer including a first controlled opening (Fig. 2, area of 162 corresponding to 112, ¶ [0033]);
a middle of line layer (Fig. 2, area of 141 and 144, ¶ [0027]);
a back end of line layer (Fig. 2, 150, ¶ [0031]) coupled to a frontside of the middle of line layer (Fig. 2);
a first conductive contact (Fig. 2, 162, ¶ [0028]) positioned on a backside of the transistor device (Fig. 2, 162 is on the bottom side of Lee’s transistor device) in contact with a backside of the source and drain region (Fig. 2, bottom side of 126_1), through the bottom dielectric isolation layer and through the first controlled opening (Figs. 2 & 3) of the first sacrificial layer;
a second conductive contact (Fig. 2, 145, ¶ [0026]) in contact with the gate region from a frontside of the gate region (Fig. 2, top side of 129) and in contact with the back end of line layer (Fig. 2);
a backside power delivery network (Fig. 2, 170, ¶ [0029]) coupled to a back side of the front end of line layer (Fig. 2, 170 is coupled to a bottom side of Lee’s transistor device); and a power rail (Fig. 2, 172, ¶ [0029]) in the backside power delivery network in contact with a backside of the first conductive contact.
Regarding claim 14, Lee teaches the semiconductor device of claim 8, and Lee teaches that the bottom dielectric isolation layer (Fig. 2, 114, ¶ [0019]) is in position to isolate (Fig. 2) the first conductive contact (Fig. 2, 162, ¶ [0028]) from the gate region (Fig. 2, 129, ¶ [0021]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 and 6 are rejected under 35 U.S.C. 103 as being obvious over LEE et al. (US Pub. No. 2024/0096984). in view of YU et al. (US Pub. No. 2022/0165856).
Regarding claim 2, Lee teaches the semiconductor device of claim 1.
However, Lee does not explicitly teach an insulation layer positioned between the first conductive contact and the buffer layer.
However, Yu is a pertinent art that teaches an insulation layer (Fig. 15, 264, ¶ [0024]) positioned between the first conductive contact (Fig. 15, 280, ¶ [0032]) and the buffer layer (Fig. 15, 266, ¶ [0027]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s device to further include additional insulation layers between their contact and buffer layer according to the teaching of Yu (Fig. 15) in order to provide further insulation for Lee’s components during manufacturing.
Regarding claim 3, Lee modified by Yu teaches the semiconductor device of claim 2, and Yu teaches a dielectric inner spacer layer (Fig. 15, 284, ¶ [0032]) is positioned on a same level (Fig. 15, at least a portion of 284 is on a same vertical height as 266) as the buffer layer (Fig. 15, 266, ¶ [0027]).
Regarding claim 6, Lee teaches the semiconductor device of claim 5.
However, Lee does not explicitly teach a second buffer layer positioned between the buffer layer and a backside of the adjacent source and drain region.
However, Yu is a pertinent art that teaches a second buffer layer (Fig. 15, 264, ¶ [0024]) positioned between the buffer layer (Fig. 15, 266, ¶ [0027]) and a backside of the adjacent source and drain region (Fig. 15, bottom surface of 226D, ¶ [0017]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s device to further include additional insulation layers between their buffer layer and an adjacent source/drain region according to the teaching of Yu (Fig. 15) in order to provide further insulation for Lee’s components during manufacturing.
Claims 9-13 are rejected under 35 U.S.C. 103 as being obvious over LEE et al. (US Pub. No. 2024/0096984). in view of CHANG et al. (US Pub. No. 2023/0026310).
Regarding claim 9, Lee teaches the semiconductor device of claim 8.
However, Lee does not explicitly teach a second sacrificial layer positioned between the first sacrificial layer and the bottom dielectric isolation layer, wherein the first conductive contact is in contact with the backside of the source and drain region through a second controlled opening in the second sacrificial layer.
However, Chang is a pertinent art that teaches a second sacrificial layer (Fig. 5I-1, 106Q, ¶ [0116]) positioned between the first sacrificial layer (Fig. 5I-1, 182, ¶ [0120]) and the bottom dielectric isolation layer (Fig. 5I-1, 182, ¶ [0120]), wherein the first conductive contact (Fig. 5I-1, 190, ¶ [0137]) is in contact with the backside of the source and drain region (Fig. 5I-1, 154, ¶ [0071]) through a second controlled opening (Fig. 5I-1, area of 190 corresponding to a height of 106Q) in the second sacrificial layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s device to further include additional protective layers between their sacrificial layer and contact structure according to the teaching of Chang (Fig. 5I-1) in order to provide prevent damage to Lee’s components during manufacturing (Chang ¶ [0116]).
Regarding claim 10, Lee modified by Chang teaches the semiconductor device of claim 9 and Lee teaches that the first controlled opening (Figs. 2 & 3, area of 162 corresponding to 112, ¶ [0033]) is larger than the second controlled opening (Fig. 2, Lee’s contact structure is tapered so that their contact structure decreases in size from 112 towards 114. Lee modified by Chang’s structure would have an additional layer between 112 and 114. Therefore, Lee modified by Chang’s contact structure would have a larger area corresponding to 112 and would have a smaller area corresponding to Lee modified by Chang’s protective layer); and
the first conductive contact includes a tapered sidewall (opening (Fig. 2, Lee’s contact structure is tapered so that their contact structure decreases in size from 112 towards 114. Lee modified by Chang’s structure would have an additional layer between 112 and 114. Therefore, Lee modified by Chang’s contact structure be tapered) indexed through the first and second controlled openings.
Regarding claim 11, Lee teaches the semiconductor device of claim 8.
However, Lee does not explicitly teach a first dielectric inner spacer layer positioned in the first controlled opening between the first conductive contact and the first sacrificial layer.
However, Chang is a pertinent art that teaches a first dielectric inner spacer layer (Fig. 5I-1, 186, ¶ [0132]) positioned in the first controlled opening (Fig. 5I-1, area of 190 corresponding to 182, ¶ [0136]) between the first conductive contact (Fig. 5I-1, 190) and the first sacrificial layer (Fig. 5I-1, 182, ¶ [0123]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s device to have additional dielectric layers according to the teaching of Chang (Fig. 5I-1) in order to better insulate Lee’s components during manufacturing.
Regarding claim 12, Lee modified by Chang teaches the semiconductor device of claim 11, and Chang teaches a second dielectric inner spacer (Fig. 5I-1, 150R, ¶ [0195]) positioned in a second controlled opening (Fig. 5I-1, area of 190 corresponding to a height of 106Q) between the first conductive contact (Fig. 5I-1, 190, ¶ [0137]) and a second sacrificial layer (Fig. 5I-1, 106Q, ¶ [0116]).
Regarding claim 13, Lee modified by Chang teaches the semiconductor device of claim 12, and Chang teaches a first dielectric inner spacer (Fig. 5I-1, 180, ¶ [0121]) and the second dielectric inner spacer (Fig. 5I-1, 150R, ¶ [0195]) are in position to isolate the first conductive contact (Fig. 5I-1, 190, ¶ [0137]) from an adjacent source and drain region (Fig. 5I-1, 156, ¶ [0076]).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2021/0376155 by Chang et al discloses a transistor device.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2023/0009144 by Lin et al discloses a transistor device.
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/R.P.S./
Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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