DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: item 100 from figure 1.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to as failing to comply with 37 CFR 1.71(a) because of the following informalities: In par.82, in the table, under FIR filter Type, “Fraction 1/3 Decimation” should read as “Fractional 1/3 Decimation”. Appropriate correction is required.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1-2, 5, 12-14, 17, and 24 objected to as failing to comply with 37 CFR 1.75(a) because of the following informalities:
In claim 1, ll.3, "vector processing circuitry" should read as "a vector processing circuitry"
In claim 1, ll.14, "the output vector" should read as "the output data vector"
In claim 1, ll.15, "on data samples" should read as "on the data samples"
In claim 2, ll.2, "de-rotate data samples" should read as "de-rotate the data samples"
In claim 5, ll.1, “the filter type” should read as “the selected filter type”
In claim 5, ll.2, “perform filter processing operations" should read as "perform the filter processing operations”
In claim 5, ll.3 “on data samples" should read as "on the data samples”
In claim 12, ll.2, “coefficient clone logic" should read as "a coefficient clone logic”
In claim 13, ll.15, "on data samples" should read as "on the data samples"
In claim 14, ll.2, "de-rotate data samples" should read as "de-rotate the data samples"
In claim 17, ll.3, “perform filter processing operations" should read as "perform the filter processing operations”
In claim 17, ll.4 “on data samples" should read as "on the data samples”
In claim 24, ll.2, “coefficient clone logic" should read as "a coefficient clone logic”
Appropriate correction is required
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 6 and 18 are directed to a Markush grouping of an Open List of alternatives, as the limitation recites “wherein the selected filter type is selected from among a set of selectable filter types comprising:…”. The open list of alternatives renders the claim as indefinite because it is unclear what other alternatives are intended to be encompassed by the claim. See MPEP 2173.05(h).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-5, 13, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2020/0409701 A1), hereinafter Chen, and in view of Lee et al. (NPL: “A Low-Power DSP for Wireless Communications”), hereinafter Lee.
Regarding claim 1, Chen discloses:
A system on a chip (SoC), comprising:
a memory configured to store data samples [Fig.2, Register file/memory circuit 210; Par.64-65; “In the Figures herein, e.g., FIGS. 2-34, data may be loaded from a register/memory and/or stored in a register or memory” par.84]; and
vector processing circuitry [Fig.2, Execution circuit 212; "Benes network circuits 216 are coupled to (or part of) executing circuit 212" par.65; Fig.4, Benes Network; Fig.9, execution circuit 910], comprising:
a first set of butterfly networks, an input of each one of the first set of butterfly networks being coupled to an output of a first inverse butterfly network; a second set of butterfly networks, an input of each one of the second set of butterfly networks being coupled to an output of a second inverse butterfly network [“a first multicast Benes network circuit is included for data samples and a second multicast Benes network circuit is included for coefficients.” par.65; Fig.3, discloses Inverse butterfly circuit into normal butterfly circuit],
Unicast inverse butterfly networks and multicast butterfly networks. [par. 70-75 discloses unicast and multicast switches used by the benes network; “all switches in a butterfly circuit of a Benes network circuit are multicast switches and/or all switches in an inverse butterfly circuit of a Benes network circuit are multicast switches” par. 75, discloses three possibilities: both multicast, Multicast inverse butterfly circuit, or multicast butterfly circuit]
wherein each multicast butterfly network from among the first and the second set of multicast butterfly networks is configured to perform, on data samples output via a respectively coupled one of the first and the second unicast inverse butterfly networks, processing operations to generate respective data vectors comprising processed data samples ["a multicast Benes network circuit supports different modes to perform one or more operations that includes permutations, rotations, cloning of input values used to create the required output” par.76; See at least par.58, 61, 67,77,84,87-94]; and
Chen also discloses the execution circuit configured to generate an output data vector based upon the data vectors output via each butterfly network from among the first and the second set of butterfly networks, the output vector representing a result of filter processing operations that are performed on data samples read from the memory in accordance with a selected filter type. [“Benes network circuit… supplying input to a multiplier (e.g., multiply circuit) , and/or grouping multiplier inputs according to which products are summed to create the output samples” par.76; see par.101, 104,106,110, and 125-128]
However, Chen does not explicitly disclose:
an output interface configured to generate an output data vector based upon the data vectors output via each multicast butterfly network from among the first and the second set of multicast butterfly networks,
In the analogous art of Digital signal processing and vector/FIR processing, Lee teaches an output interface configured to generate an output data vector based on the inputs into a vector computation unit ["SIMD shuffle network performs data alignment that is required to support data movement operations between computations… implemented by a multiple stage shuffle exchange network" Sec.III.A.par.3]
It would have been obvious to one of ordinary skill in the art, having the teachings of Chen and Lee before him before the effective filing date of the claimed invention to modify the execution unit disclosed by Chen, to include an output interface taught by Lee, in order to perform data alignment that is required to support data movement between computations and to enable efficient control of the data [Lee: Sec.III.A par.3, Sec.III.C.2), Sec.IV.B.5), Sec.V.D-E, and Sec.VII]. the combination of Chen and Lee discloses an output interface configured to generate an output data vector based upon the data vectors output via each multicast butterfly network from among the first and the second set of multicast butterfly networks,
Regarding claim 3, Chen and Lee disclose the invention substantially as claimed. See the discussion of claim 1 above.
Chen discloses wherein each multicast butterfly network from among the first and the second set of multicast butterfly networks is configured to generate respective data vectors comprising processed data samples in accordance with a sliding time window pattern based upon the selected filter type [“…generation of a plurality of sets of sliding windows for filters with symmetry, and generation of a plurality of sets of variable offset windows for nonlinear filters.” Par.58; "the multicast Benes network circuitry performs one of the following operations to generate data in FIR sliding window format" par.109; also see par.114-121].
Regarding claim 4, Chen and Lee disclose the invention substantially as claimed. See the discussion of claim 1 above.
Chen discloses Benes networks [fig.4]
Lee discloses an output interface ["SIMD shuffle network performs data alignment that is required to support data movement operations between computations… implemented by a multiple stage shuffle exchange network" Sec.III.A.par.3]
While Lee does not explicitly disclose wherein the output interface comprises a Benes network.
It would have been obvious to one of ordinary skill in the art, having the teachings of Chen and Lee before him before the effective filing date of the claimed invention to modify the execution unit disclosed by Chen, to include an output interface taught by Lee, and further modify the output interface to use a Benes Network as disclosed by Chen, in order to, support multiple FIR filters and support a variety of applications efficiently that maximizes the usage of the multipliers of the hardware [Chen: Par.58-60].
Regarding claim 5, Chen and Lee disclose the invention substantially as claimed. See the discussion of claim 1 above.
Chen discloses:
wherein the filter type is from among a plurality of filter types, and wherein the vector processing circuitry is configured to perform filter processing operations on data samples read from the memory in accordance with a set of processing instructions based upon the selected filter type ["an instruction in its instruction set that formats a Benes network circuit to provide a desired output sequence" par.61; "a formatting instruction switches a multicast Benes network circuit to one of a plurality of modes… each mode provides unique control for alignment and cloning of input samples and/or coefficients… a mode may include any one or combination of [i.e. FIR, Symmetric FIR, Fractional rate, digital pre-distortion, or Half-band FIR filter mode]" par.67; Par.77-78 also discloses Digital Front-End DFE that can be used in SIMD systems including Benes Networks].
Regarding claim 13, Chen discloses:
A system on a chip (SoC), comprising:
a memory configured to store data samples [Fig.2, Register file/memory circuit 210; Par.64-65; “In the Figures herein, e.g., FIGS. 2-34, data may be loaded from a register/memory and/or stored in a register or memory” par.84]; and
a programmable processing array, [Fig.2, Execution circuit 212; "Benes network circuits 216 are coupled to (or part of) executing circuit 212" par.65; Fig.4, Benes Network; Fig.9, execution circuit 910], comprising:
a first set of butterfly networks, an input of each one of the first set of butterfly networks being coupled to an output of a first inverse butterfly network; a second set of butterfly networks, an input of each one of the second set of butterfly networks being coupled to an output of a second inverse butterfly network, [“a first multicast Benes network circuit is included for data samples and a second multicast Benes network circuit is included for coefficients.” par.65; Fig.3, discloses Inverse butterfly circuit into normal butterfly circuit],
Unicast inverse butterfly networks and multicast butterfly networks. [par. 70-75 discloses unicast and multicast switches used by the benes network; “all switches in a butterfly circuit of a Benes network circuit are multicast switches and/or all switches in an inverse butterfly circuit of a Benes network circuit are multicast switches” par. 75, discloses three possibilities: both multicast, Multicast inverse butterfly circuit, or multicast butterfly circuit]
wherein each multicast butterfly network from among the first and the second set of multicast butterfly networks is configured to perform, on data samples output via a respectively coupled one of the first and the second unicast inverse butterfly networks, processing operations to generate respective sets of processed data samples ["a multicast Benes network circuit supports different modes to perform one or more operations that includes permutations, rotations, cloning of input values used to create the required output” par.76; See at least par.58, 61, 67,77,84,87-94]; and
Chen also discloses the execution circuit configured to generate an output set of data samples based upon the processed data samples output via each multicast butterfly network from among the first and the second set of multicast butterfly networks, the output set of data samples representing a result of digital front end (DFE) processing operations that are performed on data samples read from the memory in accordance with a selected DFE function. [“Benes network circuit… supplying input to a multiplier (e.g., multiply circuit) , and/or grouping multiplier inputs according to which products are summed to create the output samples” par.76; see par.101, 104,106,110, and 125-128; Par.77-78 and 96 also discloses Digital Front-End DFE that can be used in SIMD systems including Benes Networks]
However, Chen does not explicitly disclose:
an output interface configured to generate an output set of data samples based upon the processed data samples output via each multicast butterfly network from among the first and the second set of multicast butterfly networks
In the analogous art of Digital signal processing and vector/FIR processing, Lee teaches an output interface configured to generate an output set of data samples based on the inputs into a SIMD computation unit ["SIMD shuffle network performs data alignment that is required to support data movement operations between computations… implemented by a multiple stage shuffle exchange network" Sec.III.A.par.3]
It would have been obvious to one of ordinary skill in the art, having the teachings of Chen and Lee before him before the effective filing date of the claimed invention to modify the execution unit disclosed by Chen, to include an output interface taught by Lee, in order to perform data alignment that is required to support data movement between computations and to enable efficient control of the data [Lee: Sec.III.A par.3, Sec.III.C.2), Sec.IV.B.5), Sec.V.D-E, and Sec.VII]. the combination of Chen and Lee discloses an output interface configured to generate an output set of data samples based upon the processed data samples output via each multicast butterfly network from among the first and the second set of multicast butterfly networks
Regarding claim 15, Chen and Lee disclose the invention substantially as claimed. See the discussion of claim 1 above.
Chen discloses wherein each multicast butterfly network from among the first and the second set of multicast butterfly networks is configured to generate respective sets of processed data samples in accordance with a sliding time window pattern based upon the selected DFE function [“…generation of a plurality of sets of sliding windows for filters with symmetry, and generation of a plurality of sets of variable offset windows for nonlinear filters.” Par.58; "the multicast Benes network circuitry performs one of the following operations to generate data in FIR sliding window format" par.109; also see par.114-121].
Regarding claim 16, Chen and Lee disclose the invention substantially as claimed. See the discussion of claim 1 above.
Chen discloses Benes networks [fig.4]
Lee discloses an output interface ["SIMD shuffle network performs data alignment that is required to support data movement operations between computations… implemented by a multiple stage shuffle exchange network" Sec.III.A.par.3]
While Lee does not explicitly disclose wherein the output interface comprises a Benes network.
It would have been obvious to one of ordinary skill in the art, having the teachings of Chen and Lee before him before the effective filing date of the claimed invention to modify the execution unit disclosed by Chen, to include an output interface taught by Lee, and further modify the output interface to use a Benes Network as disclosed by Chen, in order to, support multiple FIR filters and support a variety of applications efficiently that maximizes the usage of the multipliers of the hardware [Chen: Par.58-60].
Regarding claim 17, Chen and Lee disclose the invention substantially as claimed. See the discussion of claim 1 above.
Chen discloses:
wherein the DFE processing operations comprise filter processing operations in accordance with a selected filter type from among a plurality of filter types, and wherein the programmable processing array is configured to perform filter processing operations on data samples read from the memory in accordance with a set of processing instructions based upon the selected filter type ["an instruction in its instruction set that formats a Benes network circuit to provide a desired output sequence" par.61; "a formatting instruction switches a multicast Benes network circuit to one of a plurality of modes… each mode provides unique control for alignment and cloning of input samples and/or coefficients… a mode may include any one or combination of [i.e. FIR, Symmetric FIR, Fractional rate, digital pre-distortion, or Half-band FIR filter mode]" par.67; Par.77-78 also discloses Digital Front-End DFE that can be used in SIMD systems including Benes Networks].
Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chen and Lee, and further in view of Rahman et al. (US 2023/0333848 A1), hereinafter Rahman.
Regarding claim 2, Chen and Lee disclose the invention substantially as claimed. See the discussion of claim 1 above..
Chen discloses the use of the inverse butterfly networks and/or butterfly networks to permute and/or rotate data from memory [par.70-76; “In the Figures herein, e.g., FIGS. 2-34, data may be loaded from a register/memory and/or stored in a register or memory” par.84] and
Lee teaches vector alignment circuitry [see fig,5]
However, Chen and Lee does not explicitly disclose the unicast inverse butterfly network configured to respectively de-rotate data samples read from the memory to output, to each respectively coupled multicast butterfly network from among the first and the second set of multicast butterfly networks, vectors comprising time-aligned data samples.
In the analogous art of Digital signal processing and vector/FIR processing, Rahman teaches using a butterfly network for formatting the data in the correct order from an non-aligned fetch of data [“The reference sequence enables the data formatting network to present data to processing unit core 110 in the correct order” par. 180; “Respective butterfly network 2817 /2827 includes a seven-stage butterfly network that implements the formatter…. The first stage of the butterfly is actually a half-stage that collects bytes from both slots that match a non-aligned fetch and merges the collected bytes into a single, rotated 64-byte array” par.184]
It would have been obvious to one of ordinary skill in the art, having the teachings of Chen, Lee, and Rahman before him before the effective filing date of the claimed invention to modify the inverse butterfly circuitry disclosed by Chen, to include handling of non-aligned data taught by Rahman, in order to, maintain full throughput, addressing/tracking of data, and maximize performance [Rahman: par. 175-189 and 369]. The combination of Chen, Lee, and Rahman discloses the additional limitations of the claim
Regarding claim 14, Chen and Lee disclose the invention substantially as claimed. See the discussion of claim 1 above..
Chen discloses the use of the inverse butterfly networks and/or butterfly networks to permute and/or rotate data from memory [par.70-76; “In the Figures herein, e.g., FIGS. 2-34, data may be loaded from a register/memory and/or stored in a register or memory” par.84] and
Lee teaches vector alignment circuitry [see fig,5]
However, Chen and Lee does not explicitly disclose the unicast inverse butterfly network configured to respectively de-rotate data samples read from the memory to output, to each respectively coupled multicast butterfly network from among the first and the second set of multicast butterfly networks, sets of time-aligned data samples.
In the analogous art of Digital signal processing and vector/FIR processing, Rahman teaches using a butterfly network for formatting the data in the correct order from an non-aligned fetch of data [“The reference sequence enables the data formatting network to present data to processing unit core 110 in the correct order” par. 180; “Respective butterfly network 2817 /2827 includes a seven-stage butterfly network that implements the formatter…. The first stage of the butterfly is actually a half-stage that collects bytes from both slots that match a non-aligned fetch and merges the collected bytes into a single, rotated 64-byte array” par.184]
It would have been obvious to one of ordinary skill in the art, having the teachings of Chen, Lee, and Rahman before him before the effective filing date of the claimed invention to modify the inverse butterfly circuitry disclosed by Chen, to include handling of non-aligned data taught by Rahman, in order to, maintain full throughput, addressing/tracking of data, and maximize performance [Rahman: par. 175-189 and 369]. The combination of Chen, Lee, and Rahman discloses the additional limitations of the claim
Allowable Subject Matter
Claims 7-12 and 19-24 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7 (and 19):
The prior art of record does not teach or suggest a combination as claimed with: “…the first multicast butterfly network being configured to output, by performing processing operations on data samples received via the first unicast inverse butterfly network… and the second multicast butterfly network being configured to output, by performing processing operations on data samples received via the first unicast inverse butterfly network…”.
Claims 8-12 effectively depends on claim 7 and would be allowable for the reasons given above.
Claims 20-24 effectively depends on claim 19 and would be allowable for the reasons given above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Khlat (US 7,668,249 B1) discloses different sets of coefficients may be stored and retrieved from a Look-up table and may be duplicated or be symmetrical sections. See col.6 par.2
Puthusserypady (NPL: “Applied Signal Processing: Design of Digital Filters”) discloses symmetric and anti-symmetric FIR filters, and reduced number of coefficients compared to a normal FIR filter, see at least table 14.1 on p.284
Milic (NPL: “Multirate Filtering for Digital Signal Processing: MATLAB Applications”) discloses Fractional filters, rational factors used by fractional filters and examples given for rational factors of M=3, L=3, L/M = 4/3, and L/M = 3/4; and benefits of multirate systems. See at least p.23, 35-40, 62, 64, 73, and 171.
Ozgul et al. (US 11,061,673 B1) discloses a dual butterfly network used for pre-adding two vectors from one memory of input data prior to multiplication for vector processing. See fig,7, items 708, 710, and 714.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenny K. Bui whose telephone number is (571)270-0604. The examiner can normally be reached 8:00 am to 3:00 pm on Monday, 8:00 am to 4:00 pm on Tuesday to Friday ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew T Caldwell can be reached at (571)272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNY K. BUI/Patent Examiner, Art Unit 2182 (571)270-0604
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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