Prosecution Insights
Last updated: August 17, 2026
Application No. 18/147,330

VECTORIZED SPARSE CONVOLUTION

Non-Final OA §102§103§112
Filed
Dec 28, 2022
Examiner
YAARY, MICHAEL D
Art Unit
Tech Center
Assignee
Qualcomm Incorporated
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
883 granted / 1013 resolved
+27.2% vs TC avg
Moderate +8% lift
Without
With
+8.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
15 currently pending
Career history
1025
Total Applications
across all art units

Statute-Specific Performance

§101
24.9%
-15.1% vs TC avg
§103
35.6%
-4.4% vs TC avg
§102
19.6%
-20.4% vs TC avg
§112
8.7%
-31.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1013 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION 1. Claims 1-30 are pending in the application Notice of Pre-AIA or AIA Status 2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Interpretation 3. The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. 4. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Claim Rejections - 35 USC § 102 5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 6. Claim(s) 1, 3, 5-9, 11, 13, 15-19, 21, 23, and 25-30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tse et al (hereafter Tse)(US Pub. 20210319077). 7. As to claim 1, Tse discloses a processor-implemented method (abstract and [0001]), comprising: accessing an input tensor for a convolution operation using a convolution kernel ([0033] various types of tensor multiplications such as tensor product and convolution of input data and kernel data), wherein the input tensor comprises a set of valid elements ([0005] and [0017] valid elements); generating an aggregated output value for a valid element of the set of valid elements in the input tensor ([0074]-[0076] an accumulator that aggregates data generated from the results of first filter 506 or second filter 514 to separately store aggregated data of a dimension not to be reduced), comprising: determining a set of one or more affected output elements based on the convolution kernel ([0041]-[0042]); generating, for each respective affected output element of the set of one or more affected output elements, a respective intermediate value based on the convolution kernel and the valid element ([0055] and [0074] intermediate data); and accumulating the respective intermediate values to generate the aggregated output value; and outputting the aggregated output value ([0048]-[0049] and [0058]-[0060] accumulate operations, generating output data). 8. As to claims 3 13, and 23, Tse disclose wherein generating, for each respective affected output element of the set of one or more affected output elements, the respective intermediate value comprises: determining, for each respective affected output element of the set of one or more affected output elements, a corresponding element in the convolution kernel; and multiplying a value of the corresponding element in the convolution kernel with a value of the valid element ([0062]-[0063] and [0082]). 9. As to claims 5 15, and 25 Tse discloses wherein accumulating the respective intermediate values comprises, for a first intermediate value corresponding to a first affected output element in the set of one or more affected output elements: identifying a buffer element corresponding to the first affected output element; and adding the first intermediate value to a value stored in the buffer element ([054] and [0057]-[0060]). 10. As to claims 6, 16, and 26, Tse discloses generating a set of aggregated output values for the set of valid elements in the input tensor; and outputting the set of aggregated output values ([0045] and [0074]). 11. As to claims 7, 17, and 27, Tse discloses wherein the set of aggregated output values are generated in parallel ([0048] and [0066] computing in parallel). 12. As to claims 8, 18, and 28, Tse discloses discarding aggregated output values corresponding to one or more invalid elements for the input tensor ([0017] and [0074]-[0076]). 13. As to claims 9, 19, and 29, Tse discloses wherein: the input tensor is a sparse tensor, and the set of valid elements corresponds to elements having a non-zero value in the input tensor ([0045]-[0048]). 14. As to claims 11, 21, and 30, the claims are rejected for similar reasons as claim 1 above. Claim Rejections - 35 USC § 103 15. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 16. Claim(s) 2, 4, 10, 12, 14, 20, 22, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tse in view of Chentanez et al (hereafter Chentanez)(US Pub. 20220051094). 17. As to claims 2, 12, and 22, Tse does not disclose wherein determining the set of one or more affected output elements comprises: determining an index of the valid element; and determining a set of indices covered by the convolution kernel when the convolution kernel is centered on the index of the valid element. However, Chentanez discloses wherein determining the set of one or more affected output elements comprises: determining an index of the valid element ([0348] indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and/or pixel data, as well as state parameters and commands defining how data is to be processed and determining a set of indices covered by the convolution kernel when the convolution kernel is centered on the index of the valid element (e.g., what program is to be executed). In at least one embodiment, scheduler 2910 may be configured to fetch indices corresponding to tasks or may receive indices from front end 2908. In at least one embodiment, front end 2908 can be configured to ensure processing cluster array 2912 is configured to a valid state before a workload specified by incoming command buffers (e.g., batch-buffers, push buffers, etc.) is initiated). 18. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the teachings of Tse with the determining an index, as in Chentanez for the benefit of an improved way of using a neural network to solve problems (Chentanez [0065]). 19. As to claims 4, 14, and 24, the combination of Tse and Chentanez discloses wherein generating, for each respective affected output element of the set of one or more affected output elements, the respective intermediate value comprises generating the respective intermediate values in parallel using a single instruction, multiple data (SIMD) operation (Chentanez [0356] SIMD). 20. As to claims 10 and 20, the combination of Tse and Chentanez discloses wherein the input tensor comprises light detection and ranging (LIDAR) data (Chentanez [0209]-[0211). Conclusion 21. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. 20210279841 – related to Apparatuses, systems, and techniques for texture synthesis from small input textures in images using convolutional neural networks. In at least one embodiment, one or more convolutional layers are used in conjunction with one or more transposed convolution operations to generate a large textured output image from a small input textured image while preserving global features and texture. US Pub. 20200159809 – related to a method and hardware system for mapping an input map of a convolutional neural network layer to an output map are disclosed. An array of processing elements are interconnected to support unidirectional dataflows through the array along at least three different spatial directions. Each processing element is adapted to combine values of dataflows along different spatial directions into a new value for at least one of the supported dataflows. For each data entry in the output map, a plurality of products from pairs of weights of a selected convolution kernel and selected data entries in the input map is provided and arranged into a plurality of associated partial sums. Products associated with a same partial sum are accumulated on the array and accumulated on the array into at least one data entry in the output map. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL D YAARY whose telephone number is (571)270-1249. The examiner can normally be reached Mon-Fri 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571)272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL D. YAARY/ Primary Examiner, Art Unit 2151
Read full office action

Prosecution Timeline

Dec 28, 2022
Application Filed
Jul 17, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12699545
SECURE SELECTIVE PRODUCT COMPUTATION SYSTEM, SECURE SELECTIVE PRODUCT COMPUTATION METHOD, SECURE COMPUTATION APPARATUS, AND PROGRAM
4y 0m to grant Granted Aug 04, 2026
Patent 12699890
WORD LINE DRIVER FOR VECTOR-BY-MATRIX MULTIPLICATION ARRAY
2y 8m to grant Granted Aug 04, 2026
Patent 12693875
PROCESSING CORE WITH OPERATION SUPPRESSION BASED ON CONTRIBUTION ESTIMATE
4y 4m to grant Granted Jul 28, 2026
Patent 12694072
SOLVER EXECUTION SERVICE MANAGEMENT
3y 10m to grant Granted Jul 28, 2026
Patent 12681694
MULTIPLIER, METHOD, INTEGRATED CIRCUIT CHIP, AND COMPUTING DEVICE FOR FLOATING POINT OPERATION
3y 9m to grant Granted Jul 14, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
95%
With Interview (+8.1%)
3y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1013 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month