DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 7 and 9-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Narasimhan et al. (US 2023/0038670).
In regards to claim 1, Narasimhan discloses of a memory die (for example see Paragraphs 0036, 0146-0149, 0156-0183) comprising: one or more substrates; and a logic coupled to the one or more substrates, where the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic to: determine a completion of a burst cycle operation; and alternate between a first park status applied to even node devices and a second park status applied to odd node devices in response to the determined completion of the burst cycle operation (for example see Figs 1A-E, 3A-B, 18 and Paragraphs 0006, 0038-0045, 0056-0061, 0187-0193).
In regards to claim 2, Narasimhan discloses of the memory die of claim 1, wherein the logic is further to: select between an activated age protection mode and a disabled age protection mode (for example see selections in Figs 1A-E, 3A-B, 18 and Paragraphs 0006, 0038-0045, 0056-0061, 0187-0193).
In regards to claim 3, Narasimhan discloses of the memory die of claim 2, wherein the activated age protection mode is a default mode (for example see Paragraphs 0006, 0038, 0045, 0187-0193).
In regards to claim 7, Narasimhan discloses of the memory die of claim 1, wherein the even and odd node devices are PMOS devices (for example see Figs 1A-B, D).
In regards to claim 9, Narasimhan discloses of a system comprising: a processor (see Paragraph 0146, 0160, 165-0166); and a memory architecture (for example see Paragraphs 0036, 0146-0149, 0156-0183) communicatively coupled to the processor (for example see Paragraphs 0036, 0146-0149, 0156-0183), the memory architecture including logic coupled to one more substrates, wherein the logic is to: monitor an internal reference clock (for example see Paragraphs 0036-0045, 0051-0059); and alternate between a first park status applied to even node devices and a second park status applied to odd node devices in response to the monitored internal reference clock (for example see Figs 1A-E, 3A-B, 18 and Paragraphs 0006, 0038-0045, 0056-0061, 0187-0193).
In regards to claim 10, Narasimhan discloses of the system of claim 9, wherein the logic is further to: select between an activated age protection mode and a disabled age protection mode (for example see selections in Figs 1A-E, 3A-B and Paragraphs 0039-0045, 0056-0061).
In regards to claim 11, Narasimhan discloses of the system of claim 10, wherein the activated age protection mode is a default mode (for example see Paragraphs 0006, 0038, 0045, 0187-0193).
In regards to claim 12, Narasimhan discloses of the system of claim 9, wherein the logic is further to: detect when entering an active idle state, wherein the detected entering of the active idle state is based on detection of a burst signal end, and wherein the alternation between the first park status applied to even node devices and the second park status applied to odd node devices is done in response to the detected entering of the active idle state (for example see Paragraphs 0038-0045, 0056-0061, 0187-0193).
In regards to claim 13, Narasimhan discloses of the system of claim 12, wherein the logic is further to: detect when leaving the active idle state, wherein the detected leaving of the active idle state is based on detection of a burst signal start; and end the alternation between the first park status and the park status in response to the detected leaving of the active idle state (for example see Paragraphs 0038-0045, 0056-0061, 0187-0193).
In regards to claim 14, Narasimhan discloses of the system of claim 9, wherein the monitored internal reference clock is to supply an oscillating signal (for example see Paragraphs 0036-0045, 0051-0059).
In regards to claim 15, Narasimhan discloses of a method comprising: determining a completion of a burst cycle operation; and alternating between a first park status applied to even node devices and a second park status applied to odd node devices in response to the determined completion of the burst cycle operation (for example see Figs 1A-E, 3A-B, 18 and Paragraphs 0006, 0038-0045, 0056-0061, 0187-0193).
In regards to claim 16, Narasimhan discloses of the method of claim 15, further comprising: selecting between an activated age protection mode and a disabled age protection mode (for example see selections in Figs 1A-E, 3A-B and Paragraphs 0039-0045, 0056-0061).
In regards to claim 17, Narasimhan discloses of the method of claim 16, wherein the activated age protection mode is a default mode (for example see Paragraphs 0006, 0038, 0045, 0187-0193).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Narasimhan et al. (US 2023/0038670) in view of Rayaprolu et al. (US 2022/0155956).
In regards to claim 8, Narasimhan discloses of the memory die of claim 1 as found within the explanation above.
However, Narasimhan does not explicitly disclose of wherein the memory die comprises 3D NAND.
Rayaprolu discloses of a memory die (130) comprising:: determining cycles of operation; and alternate between statuses in response to the cycles of operation (for example see Figs 9-10, 11A-D, 12A-D, 13, 14A-B); wherein the memory die comprises a 3D NAND (see Paragraphs 0055, 0057).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have the memory die comprising a 3D NAND as taught by Rayaprolu as a widely utilized and recognized non-volatile memory technology within the art to achieve the desired operational outcome.
Allowable Subject Matter
Claims 4-6 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 4, the prior art does not explicitly disclose of the memory die of claim 1, wherein the logic is further to: receive a burst signal; determine whether the burst signal indicates a clock tree path request or a data path request in response to the burst signal; determine whether the data path request indicates an input write path request or an output read path request in response to the determination that the burst signal indicates the data path request; and perform a burst cycle operation in response to the burst signal and based on the determination of whether the clock tree path request, the input write path request, or the output read path request is indicated by the burst signal, nor would it have been obvious to one of ordinary skill in the art to do so. Claim 5 is also objected to as being dependent on claim 4.
In regards to claim 6, the prior art does not explicitly disclose of the memory die of claim 1, wherein the operations to determine the completion of the burst cycle operation and to alternate between the first and second park status are performed by a clock divider, nor would it have been obvious to one of ordinary skill in the art to do so.
In regards to claim 18, the prior art does not explicitly disclose of the method of claim 15, further comprising: receiving a burst signal; determining whether the burst signal indicates a clock tree path request or a data path request in response to the burst signal; determining whether the data path request indicates an input write path request or an output read path request in response to the determination that the burst signal indicates the data path request; and performing a burst cycle operation in response to the burst signal and based on the determination of whether the clock tree path request, the input write path request, or the output read path request is indicated by the burst signal, nor would it have been obvious to one of ordinary skill in the art to do so. Claim 19 is also objected to as being dependent on claim 18.
In regards to claim 20, the prior art does not explicitly disclose of the method of claim 15, wherein the operations to determine the completion of the burst cycle operation and to alternate between the first and second park status are performed by a clock divider, nor would it have been obvious to one of ordinary skill in the art to do so.
Conclusion
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/JASON M CRAWFORD/Primary Examiner, Art Unit 2844
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