DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 19 is objected to due to confusing wording related to the “operations” (not the “manufacturing operations”). Claim 19 includes a first, second, and third operation, and corresponding structures for carrying out the operations are disclosed. However, it is not clear how each operation is used to accomplish and/or instantiate the main method. The main method of the invention, which is generating predictive images and comparing the predicted images to actual images for defect detection caused by a second manufacturing operation, is performed by processing circuitry. In claim 19, the processor circuitry performs “at least one of the first operations, the second operations, or the third operations to instantiate” this main method.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are: machine in claim 25.
“Machine” is interpreted as the wafer inspection system 102 as shown within Fig. 1, including at least a processor, memory, and data storage for the WMA model. See 0031 of the Specification.
Because this claim limitation is being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it is being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this limitation interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation to avoid it being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recites sufficient structure to perform the claimed function so as to avoid it being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6, 10-12, 15-20, 25-26, and 28 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pisarenco et al. (US 2022/0375063 A1), hereafter Pisarenco.
Regarding claim 1, Pisarenco teaches an apparatus comprising:
memory; machine readable instructions; and processor circuitry to at least one of instantiate operations corresponding to the machine-readable instructions or execute the machine readable instructions (See the wafer manufacturing and analysis system of Fig 1 and 0039-0043. [0008] “The non-transitory computer readable medium stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform a method for inspecting a wafer,”) to:
predict a structure of a semiconductor wafer that is to result from a second wafer manufacturing operation based on a first image of the semiconductor wafer obtained after a first wafer manufacturing operation, the second wafer manufacturing operation to be performed subsequent to the first wafer manufacturing operation (See the SEM image 204A in Fig. 2A. Here, the first manufacturing process is development of the wafer, and the second manufacturing process is etching of the developed wafer. [0045] “Additionally, the SEM image acquired at step 204A may be desired to generate predictive images of the wafer after etching to allow the wafer to be reworked based on the inspection metrology results.”); and
determine whether an actual defect developed in the semiconductor wafer between completion of the first wafer manufacturing operation and completion of the second wafer manufacturing operation based on the predicted structure of the semiconductor wafer and a second image representative of the semiconductor wafer after completion of the second wafer manufacturing operation ([0045] “Additionally, the SEM image acquired at step 204A may be desired to generate predictive images of the wafer after etching to allow the wafer to be reworked based on the inspection metrology results.” The first image is provided to a neural network to generate an ideal image of the wafer after etching. [0046] “At step 206A, the system may acquire the wafer after it has been etched. At step 208A, the system may then acquire a SEM image of the etched wafer. Inspection of the wafer using the SEM image acquired at step 208A may be desired to observe etching effects on the wafer.” Then SEM image(s) captured after etching are compared to the generated image(s) to determine defects from the etching process. Also see Figs 5A-5B and 0055-0059 where Pisarenco discusses imaging a developed wafer and generating predictive images of the through-hole locations after etching.).
Regarding claim 2, Pisarenco teaches the apparatus of claim 1, wherein the actual defect includes at least one of a bridge that connects a first word line and a second word line in the semiconductor wafer, a metal tip-to-tip short, a metal side-to-side short, an epitaxy short, or a contact-to-gate short ([0045] “For example, the SEM image acquired at step 204A may be used for defect detection (e.g., necking, bridging, etc.), roughness/ randomness characterization (e.g., line edge/width roughness, local critical dimension uniformity, edge placement error), process window optimization, calibration of the computational lithography model, and process performance monitoring and control.").
Regarding claim 3, Pisarenco teaches the apparatus of claim 1, wherein, to predict the structure of the semiconductor wafer, the processor circuitry is to simulate a change in the first image that is to occur during at least the second wafer manufacturing operation using a generative adversarial network (Fig. 8B and 0063-0083 explain different embodiments for the learning model, including learning feature maps for images and determining changes in features through the etching process (thus simulating changes occurring in the second manufacturing process of etching). Also see the process outlined in Fig. 9B, where the learning model receives SEM images of a developed wafer as input and outputs generated predictive images of the wafer after etching. Additionally, Pisarenco teaches using a GAN when discussing training of the learning model in 0068.).
Regarding claim 4, Pisarenco teaches the apparatus of claim 1, wherein, to predict the structure of the semiconductor wafer, the processor circuitry is to transform the first image into a third image representative of the predicted structure based on the second wafer manufacturing operation (Fig. 8B and 0063-0083 explain different embodiments for the learning model, including learning feature maps for images and determining changes in features through the etching process (thus predicting the changes in structure through the second manufacturing process). Also see the process outlined in Fig. 9B, where the learning model receives SEM images of a developed wafer as input and outputs generated predictive images of the wafer after etching. Additionally, Pisarenco teaches using a GAN when discussing training of the learning model in 0068.).
Regarding claim 6, Pisarenco teaches the apparatus of claim 1, wherein the processor circuitry is to obtain the first and second images via an electron-beam microscope ([0033] “An SEM can be used to image these extremely small structures, in effect, taking a “picture” of the structures.” Figs. 5A-5B show images captured by an SEM. Pisarenco also teaches that using SEM images for wafer inspection is well known in the art. [0004] “A charged particle (e.g., electron) beam microscope, such as a scanning electron microscope (SEM) or a transmission electron microscope (TEM), capable of resolution down to less than a nanometer, serves as a practicable tool for inspecting IC components having a feature size that is sub-100 nanometers. With a SEM, electrons of a single primary electron beam, or electrons of a plurality of primary electron beams, can be focused at locations of interest of a wafer under inspection.”).
Regarding claim 10, Pisarenco teaches the apparatus of claim 1, wherein the processor circuitry is to predict the structure of the semiconductor wafer before completion of the second wafer manufacturing operation and after completion of the first wafer manufacturing operation ([0045] “Additionally, the SEM image acquired at step 204A may be desired to generate predictive images of the wafer after etching to allow the wafer to be reworked based on the inspection metrology results. Since the wafer can no longer be returned to a previous process state after etch, the wafer can be re-processed to improve inspection results after development. It is thus important to obtain SEM images of the printed pattern of the wafer after development and before etching.”).
Regarding claim 11, Pisarenco teaches the apparatus of claim 1, wherein the processor circuitry is to compare the predicted structure to a corresponding structure in the second image, the corresponding structure in a location on the semiconductor wafer where the predicted structure is expected (Fig. 8B shows the model which receives an image before the etching process and generates an image predicting the wafer structure after etching. An actual image of the wafer after etching can be compared to the generated image for determining defects and damage. [0082] “In some embodiments, a statistical analysis (see, e.g., FIG. 3) may be performed based on the after-etch images, the after-development images, and predictive images to generate a statistical characterization of SEM damage to the wafer.” Additionally, 0083 teaches comparing structural features such as contact hole locations between images.).
Regarding claim 12, Pisarenco teaches a non-transitory machine readable storage medium comprising instructions that, when executed, cause processor circuitry (See the wafer manufacturing and analysis system of Fig 1 and 0039-0043. [0008] “The non-transitory computer readable medium stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform a method for inspecting a wafer,”) to at least:
simulate advancement in a manufacturing process of a semiconductor wafer to obtain a wafer appearance prediction that is expected to result from a second wafer manufacturing operation based on a first image obtained after a first wafer manufacturing operation, the second wafer manufacturing operation to be performed subsequent to the first wafer manufacturing operation (See the SEM image 204A in Fig. 2A. Here, the first manufacturing process is development of the wafer, and the second manufacturing process is etching of the developed wafer. [0045] “Additionally, the SEM image acquired at step 204A may be desired to generate predictive images of the wafer after etching to allow the wafer to be reworked based on the inspection metrology results.”); and
compute defect information based on differences between the wafer appearance prediction and a second image of the semiconductor wafer obtained after the second wafer manufacturing operation ([0045] “Additionally, the SEM image acquired at step 204A may be desired to generate predictive images of the wafer after etching to allow the wafer to be reworked based on the inspection metrology results.” The first image is provided to a neural network to generate an ideal image of the wafer after etching. [0046] “At step 206A, the system may acquire the wafer after it has been etched. At step 208A, the system may then acquire a SEM image of the etched wafer. Inspection of the wafer using the SEM image acquired at step 208A may be desired to observe etching effects on the wafer.” Then SEM image(s) captured after etching are compared to the generated image(s) to determine defects from the etching process. Also see Figs 5A-5B and 0055-0059 where Pisarenco discusses imaging a developed wafer and generating predictive images of the through-hole locations after etching.).
Regarding claim 15, Pisarenco teaches the non-transitory machine readable storage medium of claim 12, wherein the instructions, when executed, cause the processor circuitry to utilize a neural network to simulate the advancement in the manufacturing process and obtain the wafer appearance prediction (Fig. 8B and 0063-0083 explain different embodiments for the learning model, including learning feature maps for images and determining changes in features through the etching process (thus simulating changes occurring in the second manufacturing process of etching). Also see the process outlined in Fig. 9B, where the learning model receives SEM images of a developed wafer as input and outputs generated predictive images of the wafer after etching. Additionally, Pisarenco teaches using a GAN when discussing training of the learning model in 0068.).
Regarding claim 16, Pisarenco teaches the non-transitory machine readable storage medium of claim 15, wherein the instructions, when executed, cause the processor circuitry to train the neural network using first sample wafer images captured after performance of the first wafer manufacturing operation on semiconductor wafers associated with the first sample wafer images, and second sample wafer images captured after performance of the second wafer manufacturing operation on the semiconductor wafers (See Figs. 7A-7B, 8A-8B, and 0063-0083 showing the neural networks and training processes.).
Regarding claim 17, Pisarenco teaches the non-transitory machine readable storage medium of claim 12, wherein advancement in the manufacturing process is simulated before completion of the second wafer manufacturing operation on the semiconductor wafer ([0045] “Additionally, the SEM image acquired at step 204A may be desired to generate predictive images of the wafer after etching to allow the wafer to be reworked based on the inspection metrology results. Since the wafer can no longer be returned to a previous process state after etch, the wafer can be re-processed to improve inspection results after development. It is thus important to obtain SEM images of the printed pattern of the wafer after development and before etching.”).
Regarding claim 18, Pisarenco teaches the non-transitory machine readable storage medium of claim 12, where, to compute the defect information, the instructions, when executed, cause the processor circuitry to compare the wafer appearance prediction to a corresponding structure in the second image in a same location on the semiconductor wafer as the wafer appearance prediction (Fig. 8B shows the model which receives an image before the etching process and generates an image predicting the wafer structure after etching. An actual image of the wafer after etching can be compared to the generated image for determining defects and damage. [0082] “In some embodiments, a statistical analysis (see, e.g., FIG. 3) may be performed based on the after-etch images, the after-development images, and predictive images to generate a statistical characterization of SEM damage to the wafer.” Additionally, 0083 teaches comparing structural features such as contact hole locations between images.).
Regarding claim 19, Pisarenco teaches an apparatus comprising:
at least one electron-beam tool to: capture first information representative of a structure of a semiconductor wafer after a first wafer manufacturing operation; and capture second information representative of the structure of the semiconductor wafer after a second wafer manufacturing operation subsequent to the first wafer manufacturing operation ([0033] “An SEM can be used to image these extremely small structures, in effect, taking a “picture” of the structures.” Fig. 2B shows that SEM images are captured before and after the second manufacturing step. Figs. 5A-5B show examples of images captured by an SEM. Pisarenco also teaches that using SEM images for wafer inspection is well known in the art. [0004] “A charged particle (e.g., electron) beam microscope, such as a scanning electron microscope (SEM) or a transmission electron microscope (TEM), capable of resolution down to less than a nanometer, serves as a practicable tool for inspecting IC components having a feature size that is sub-100 nanometers. With a SEM, electrons of a single primary electron beam, or electrons of a plurality of primary electron beams, can be focused at locations of interest of a wafer under inspection.”);
interface circuitry to access the first information and the second information; and processor circuitry including one or more of: at least one of a central processor unit, a graphics processor unit, or a digital signal processor, the at least one of the central processor unit, the graphics processor unit, or the digital signal processor having control circuitry to control data movement within the processor circuitry, arithmetic and logic circuitry to perform one or more first operations corresponding to instructions, and one or more registers to store a result of the one or more first operations, the instructions in the apparatus; a Field Programmable Gate Array (FPGA), the FPGA including logic gate circuitry, a plurality of configurable interconnections, and storage circuitry, the logic gate circuitry and the plurality of the configurable interconnections to perform one or more second operations, the storage circuitry to store a result of the one or more second operations; or Application Specific Integrated Circuitry (ASIC) including logic gate circuitry to perform one or more third operations (See Fig. 1 showing the construction of the electron beam tool, and Fig. 6 shows the construction of the processing circuitry for receiving images, creating predictions of images after a manufacturing process, and data storage for the images and machine learning model. Also see 0060-0062 for a discussion of the elements in claim 6.);
the processor circuitry to perform at least one of the first operations, the second operations, or the third operations to instantiate: wafer structure prediction circuitry to determine projected wafer information that is to result from the second wafer manufacturing operation based on the first information (See the Image Prediction Server 630 in Fig. 6, which utilizes machine learning to generate images of a wafer after a second manufacturing operation (etching).); and
defect detection circuitry to detect whether an actual defect developed between completion of the first wafer manufacturing operation and completion of the second wafer manufacturing operation based on the second information and the projected wafer information (Figs. 7A-7B and 8A-8B show implementations of the machine learning model and its training. The model can generate images of a wafer after development (first manufacturing process) and/or after etching (second manufacturing process). In 0082-0083, Pisarenco teaches observing the structure and detecting the extent of damage to wafers.).
Regarding claim 20, Pisarenco teaches the apparatus of claim 19, wherein the wafer structure prediction circuitry is to determine the projected wafer information using a generative adversarial network (Fig. 8B and 0063-0083 explain different embodiments for the learning model, including learning feature maps for images and determining changes in features through the etching process (thus simulating changes occurring in the second manufacturing process of etching). Also see the process outlined in Fig. 9B, where the learning model receives SEM images of a developed wafer as input and outputs generated predictive images of the wafer after etching. Additionally, Pisarenco teaches using a GAN when discussing training of the learning model in 0068.).
Regarding claim 25, Pisarenco teaches a non-transitory machine readable medium ([0008] “The non-transitory computer readable medium stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform a method for inspecting a wafer,”) comprising:
wafer structure prediction instructions to cause at least one machine to predict a structure of a semiconductor wafer that is to result from a second wafer manufacturing operation based on a first image of the semiconductor wafer obtained after a first wafer manufacturing operation, the second wafer manufacturing operation to be performed subsequent to the first wafer manufacturing operation, the predicted structure corresponding to an associated state of the semiconductor wafer (See the SEM image 204A in Fig. 2A. Here, the first manufacturing process is development of the wafer, and the second manufacturing process is etching of the developed wafer. [0045] “Additionally, the SEM image acquired at step 204A may be desired to generate predictive images of the wafer after etching to allow the wafer to be reworked based on the inspection metrology results.”); and
defect detection instructions to cause the at least one machine to compare the predicted structure of the semiconductor wafer to a second image of the semiconductor wafer obtained after the second wafer manufacturing operation to identify whether an actual defect developed in the semiconductor wafer between completion of the first wafer manufacturing operation and completion of the second wafer manufacturing operation ([0045] “Additionally, the SEM image acquired at step 204A may be desired to generate predictive images of the wafer after etching to allow the wafer to be reworked based on the inspection metrology results.” The first image is provided to a neural network to generate an ideal image of the wafer after etching. [0046] “At step 206A, the system may acquire the wafer after it has been etched. At step 208A, the system may then acquire a SEM image of the etched wafer. Inspection of the wafer using the SEM image acquired at step 208A may be desired to observe etching effects on the wafer.” Then SEM image(s) captured after etching are compared to the generated image(s) to determine defects from the etching process. Also see Figs 5A-5B and 0055-0059 where Pisarenco discusses imaging a developed wafer and generating predictive images of the through-hole locations after etching.).
Regarding claim 26, Pisarenco teaches the non-transitory machine readable medium of claim 25, wherein the wafer structure prediction instructions cause the at least one machine to input the first image in a generative adversarial network to predict the structure of the semiconductor wafer (Fig. 8B and 0063-0083 explain different embodiments for the learning model, including learning feature maps for images and determining changes in features through the etching process (thus simulating changes occurring in the second manufacturing process of etching). Also see the process outlined in Fig. 9B, where the learning model receives SEM images of a developed wafer as input and outputs generated predictive images of the wafer after etching. Additionally, Pisarenco teaches using a GAN when discussing training of the learning model in 0068.).
Regarding claim 28, Pisarenco teaches the non-transitory machine readable medium of claim 25, wherein the wafer structure prediction instructions cause the at least one machine to transform the first image into a third image representative of the predicted structure based on the second wafer manufacturing operation (Fig. 8B shows the use of the neural network for predicting a third image (after etching) from a first image (captured before etching).).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 7, 13, 21, 22, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Pisarenco (US 2022/0375063 A1) in view of Sali et al. (US 2008/0101686 A1), hereafter Sali.
Regarding claim 5, Pisarenco teaches the apparatus of claim 1. Pisarenco teaches generating a post-etching image from a post-development image (where development is the first manufacturing process and etching is the second manufacturing process), but Pisarenco does not teach applying this method to other steps in the manufacturing process. Thus, Pisarenco fails to teach cause a first adjustment to the first image to generate a third image based on a third wafer manufacturing operation performed between the first wafer manufacturing operation and the second wafer manufacturing operation; and cause a second adjustment to the third image to generate the predicted structure based on the second wafer manufacturing operation.
However, Sali teaches wherein, to predict the structure of the semiconductor wafer, the processor circuitry is to: cause a first adjustment to the first image to generate a third image based on a third wafer manufacturing operation performed between the first wafer manufacturing operation and the second wafer manufacturing operation; and cause a second adjustment to the third image to generate the predicted structure based on the second wafer manufacturing operation (As discussed in claim 1, Pisarenco teaches the method of adjusting an image to simulate the ideal result of a subsequent manufacturing process, but Pisarenco only teaches using the method for a first and second manufacturing process. However, Sali teaches a more general method which can be applied at multiple different stages in the manufacturing process. The method simply involves comparing an inspection image to a reference image generated for the current stage of manufacturing. [0007] “The method may further include obtaining a reference image representing the same part of the object shown in the inspection image as said part would appear in a substantially-defectless state. For instance, the reference image may comprise an image of another part of the object or an aggregate of inspection images, for example. The method may further comprise comparing at least a portion of the inspection image to a corresponding portion of the reference image.” Reference images can be generated by learning from many images of wafers at the same manufacturing level. [0011] “Reference images may be obtained in any suitable manner. For example, a plurality of images depicting the same structural elements as shown in the inspection image may be accumulated or otherwise combined to generate a reference image.” Therefore, this method can be repeated at different manufacturing processes.).
Pisarenco and Sali are analogous in the art to the claimed invention, because both teach methods of comparing inspection images to generated and/or reference images for defect detection. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Pisarenco’s invention so that it could be applied at multiple manufacturing stages. This modification would allow one to apply Pisarenco’s methods to earlier stages in the manufacturing process, which as pointed out by Sali, would allow for defects to be found before wasteful subsequent manufacturing steps are performed on an already defective wafer ([0002] “Even the slightest structural defect can ruin a semiconductor device, and so to avoid losses of time and effort, detection of defects is critical before a defective device is mass-produced or further processes are performed on a defective wafer.”).
Regarding claim 7, Pisarenco teaches the apparatus of claim 1, and Pisarenco teaches process performance monitoring and defect detection (“For example, the SEM image acquired at step 204A may be used for defect detection (e.g., necking, bridging, etc.), roughness/randomness characterization (e.g., line edge/width roughness, local critical dimension uniformity, edge placement error), process window optimization, calibration of the computational lithography model, and process performance monitoring and control.”). This would typically include alerts when a defect is detected, but Pisarenco is not specific about generating alerts or flagging defects automatically.
However, Sali teaches the apparatus of claim 1, wherein the processor circuitry is to generate an alert in response to detection of the actual defect ([0081-0083] “The defect candidate identification unit may perform a number of different operations before determining the existence of a possible defect… One or more defect candidates may then be identified to a relative value based comparison unit 940… Unit 940 may then provide defect data for further use in the inspection process. The defect data can include, for example, the relative value comparison results and the location of the defect candidate. For example, the defect data may be compared to a threshold, and if such threshold is met or exceeded, the defect may be flagged or otherwise noted for further analysis and processing.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Pisarenco’s invention by automatically flagging defects when the defect data surpasses a threshold. This modification would allow for defects to be automatically flagged, which as pointed out by Sali, would allow for defects to be found before wasteful subsequent manufacturing steps are performed on an already defective wafer ([0002] “Even the slightest structural defect can ruin a semiconductor device, and so to avoid losses of time and effort, detection of defects is critical before a defective device is mass-produced or further processes are performed on a defective wafer.”).
Regarding claim 13, Pisarenco teaches the non-transitory machine readable storage medium of claim 12. Pisarenco teaches generating a post-etching image from a post-development image (where development is the first manufacturing process and etching is the second manufacturing process), but Pisarenco does not teach applying this method to other steps in the manufacturing process. Thus, Pisarenco fails to teach cause a first adjustment to data associated with the first image based on a third wafer manufacturing operation performed between the first wafer manufacturing operation and the second wafer manufacturing operation, the first adjustment to result in a second wafer appearance prediction; and cause a second adjustment to the second wafer appearance prediction based on the second wafer manufacturing operation, the second adjustment to result in the first wafer appearance prediction.
However, Sali teaches wherein the wafer appearance prediction is a first wafer appearance prediction, wherein, to simulate advancement in the manufacturing process, the instructions, when executed, cause the processor circuitry to: cause a first adjustment to data associated with the first image based on a third wafer manufacturing operation performed between the first wafer manufacturing operation and the second wafer manufacturing operation, the first adjustment to result in a second wafer appearance prediction; and cause a second adjustment to the second wafer appearance prediction based on the second wafer manufacturing operation, the second adjustment to result in the first wafer appearance prediction (As discussed in claim 12, Pisarenco teaches the method of adjusting an image to simulate the ideal result of a subsequent manufacturing process, but Pisarenco only teaches using the method for a first and second manufacturing process. However, Sali teaches a more general method which can be applied at multiple different stages in the manufacturing process. The method simply involves comparing an inspection image to a reference image generated for the current stage of manufacturing. [0007] “The method may further include obtaining a reference image representing the same part of the object shown in the inspection image as said part would appear in a substantially-defectless state. For instance, the reference image may comprise an image of another part of the object or an aggregate of inspection images, for example. The method may further comprise comparing at least a portion of the inspection image to a corresponding portion of the reference image.” Reference images can be generated by learning from many images of wafers at the same manufacturing level. [0011] “Reference images may be obtained in any suitable manner. For example, a plurality of images depicting the same structural elements as shown in the inspection image may be accumulated or otherwise combined to generate a reference image.” Therefore, this method can be repeated at different manufacturing processes.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Pisarenco’s invention so that it could be applied at multiple manufacturing stages. This modification would allow one to apply Pisarenco’s methods to earlier stages in the manufacturing process, which as pointed out by Sali, would allow for defects to be found before wasteful subsequent manufacturing steps are performed on an already defective wafer ([0002] “Even the slightest structural defect can ruin a semiconductor device, and so to avoid losses of time and effort, detection of defects is critical before a defective device is mass-produced or further processes are performed on a defective wafer.”).
Regarding claim 21, Pisarenco teaches the apparatus of claim 19. Pisarenco teaches generating a post-etching image from a post-development image (where development is the first manufacturing process and etching is the second manufacturing process), but Pisarenco does not teach applying this method to other steps in the manufacturing process. Thus, Pisarenco fails to teach determine a first change to the structure of the semiconductor wafer based on the first information and a third wafer manufacturing operation performed between the first wafer manufacturing operation and the second wafer manufacturing operation; and determine a second change to the structure of the semiconductor wafer based on the first information, the first change, and the second wafer manufacturing operation.
However, Sali teaches wherein the wafer structure prediction circuitry is to: determine a first change to the structure of the semiconductor wafer based on the first information and a third wafer manufacturing operation performed between the first wafer manufacturing operation and the second wafer manufacturing operation; and determine a second change to the structure of the semiconductor wafer based on the first information, the first change, and the second wafer manufacturing operation. (As discussed in claim 19, Pisarenco teaches the method of adjusting an image to simulate the ideal result of a subsequent manufacturing process, but Pisarenco only teaches using the method for a first and second manufacturing process. However, Sali teaches a more general method which can be applied at multiple different stages in the manufacturing process. The method simply involves comparing an inspection image to a reference image generated for the current stage of manufacturing. [0007] “The method may further include obtaining a reference image representing the same part of the object shown in the inspection image as said part would appear in a substantially-defectless state. For instance, the reference image may comprise an image of another part of the object or an aggregate of inspection images, for example. The method may further comprise comparing at least a portion of the inspection image to a corresponding portion of the reference image.” Reference images can be generated by learning from many images of wafers at the same manufacturing level. [0011] “Reference images may be obtained in any suitable manner. For example, a plurality of images depicting the same structural elements as shown in the inspection image may be accumulated or otherwise combined to generate a reference image.” Therefore, this method can be repeated at different manufacturing processes.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Pisarenco’s invention so that it could be applied at multiple manufacturing stages. This modification would allow one to apply Pisarenco’s methods to earlier stages in the manufacturing process, which as pointed out by Sali, would allow for defects to be found before wasteful subsequent manufacturing steps are performed on an already defective wafer ([0002] “Even the slightest structural defect can ruin a semiconductor device, and so to avoid losses of time and effort, detection of defects is critical before a defective device is mass-produced or further processes are performed on a defective wafer.”).
Regarding claim 22, Pisarenco and Sali teach the apparatus of claim 21. Sali further teaches wherein the first change is associated with dimensions of a pattern on the semiconductor wafer ([0082] “One or more defect candidates may then be identified to a relative value based comparison unit 940. The identification may include data, for example, pixel coordinates, identifying where in the image the defect candidate occurs. The relative value based comparison unit 940 may then evaluate differences between the inspection and reference images based on ordinal values, directional vectors, and/or other relative measurements for an area of pixels surrounding the defect candidate(s).”), and
wherein the second change is associated with a contrast of the pattern on the semiconductor wafer ([0081] “A defect candidate identifier 930 is operative to compare an image to be inspected to a corresponding reference image… In some embodiments, comparisons may be based on identifying the maximal differences in pixel intensities between the images.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Pisarenco’s invention by automatically detecting defects based on pattern dimensions and/or contrast. This modification would consider using both dimensions/shapes of patterns and contrast, which according to Sali, would assist in reducing false alarms ([0006] “Comparing shapes rather than gray levels alone advantageously reduces the false alarm rate. For example, false alarms due to gray level differences in non-defective areas caused by process variation or change in the image conditions can be reduced since the shape of the area is considered.”).
Regarding claim 27, Pisarenco teaches the non-transitory machine readable medium of claim 25, but Pisarenco fails to teach further including defect evaluation instructions to cause the at least one machine to generate an alert when a quantity of the actual defect satisfies a threshold.
However, Sali teaches further including defect evaluation instructions to cause the at least one machine to generate an alert when a quantity of the actual defect satisfies a threshold ([0081-0083] “The defect candidate identification unit may perform a number of different operations before determining the existence of a possible defect… One or more defect candidates may then be identified to a relative value based comparison unit 940… Unit 940 may then provide defect data for further use in the inspection process. The defect data can include, for example, the relative value comparison results and the location of the defect candidate. For example, the defect data may be compared to a threshold, and if such threshold is met or exceeded, the defect may be flagged or otherwise noted for further analysis and processing.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Pisarenco’s invention by automatically flagging defects when the defect data surpasses a threshold. This modification would allow for defects to be automatically flagged, which as pointed out by Sali, would allow for defects to be found before wasteful subsequent manufacturing steps are performed on an already defective wafer ([0002] “Even the slightest structural defect can ruin a semiconductor device, and so to avoid losses of time and effort, detection of defects is critical before a defective device is mass-produced or further processes are performed on a defective wafer.”).
Allowable Subject Matter
Claims 8-9, 14, 23, and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 8-9 and 14, the closest prior art of record, Pisarenco (US 2022/0375063 A1), teaches receiving inspection images after a first manufacturing process, generating predictive images of an ideal wafer after a second manufacturing process, and comparing inspection images captured after the second manufacturing process to the generated images for defect detection. Additionally, as discussed in the rejection to claim 5, the art of Pisarenco in combination with Sali et al. (US 2008/0101686 A1) renders obvious the use of Pisarenco’s method of using generative AI at different stages of manufacturing. However, neither Pisarenco or Sali dicuss making comparisons between manufacturing operations.
Generally, the prior art in the field of defect detection teaches methods for detecting and classifying defects in wafers and relating the root cause of defects to a manufacturing process or piece of manufacturing equipment. For example, Pisarenco teaches relating bridging, necking, etc. to the development or etching stages of manufacturing, and Gadre (US 2023/0061513 A1) (from the conclusion of the office action), teaches methods for identifying manufacturing equipment responsible for wafer defects. Additionally, Zika (US 6,040,912 A) (from the conclusion of the office action) teaches comparing two manufacturing process based on the amount of defects detected from each process. However, this method directly compares images from the first manufacturing process and second manufacturing process to detect defects using a difference between the images. Thus, Zika differs from claims 8-9, which quantify defects from each process using comparisons to generated images for each process.
However, claims 8-9 and 14 require a comparison between manufacturing processes themselves. A third manufacturing process is used to replace a second manufacturing process, and a comparison of resulting defects from the third manufacturing process and the second manufacturing process is made. The cited art before the priory date of the claimed invention does not teach this concept or utilize generative AI for this exact purpose.
Therefore, claims 8-9 and 14 obtain potentially allowable subject matter. The Examiner recommends incorporating the subject matter of claims 8-9 into claim 1 and incorporating claim 14 into claim 12.
Regarding claims 23 and 24, the closest prior art of record, Pisarenco, teaches receiving inspection images after a first manufacturing process, generating predictive images of an ideal wafer after a second manufacturing process, and comparing inspection images captured after the second manufacturing process to the generated images for defect detection. Additionally, as discussed in the rejection to claim 14, the art of Pisarenco in combination with Sali renders obvious the use of Pisarenco’s method of using generative AI at different stages of manufacturing. However, neither Pisarenco or Sali discuss making comparisons between different two wafers made of different materials.
Generally, the prior art teaches comparisons between a control wafer and a test wafer. For example, Zika teaches applying different one manufacturing processes to a first wafer and a different manufacturing process to a second wafer. Then comparisons between the defects of the wafers can be used to determine a best manufacturing process. Similarly, other prior art teaches comparisons based on wafer material and/or density, but the prior art fails to provide motivation for combining the entire machine-learning-driven process of claim 19 with the material rankings of claims 23-24.
Therefore, claims 23 and 24 obtain potentially allowable subject matter. The Examiner recommends incorporating the subject matter of claims 23 and 24 into claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mariyappan et al (US 2022/0301133 A1) teaches methods and systems for detecting defects on a wafer by capturing an inspection image of the wafer after undergoing a manufacturing process, generating a reference image of an ideal wafer after undergoing the same manufacturing process, and comparing the difference between the captured image and the reference image to identify defects.
Gao et al. (US 2017/0191948 A1) teaches methods and systems for detecting defects on a wafer by collecting images of the wafer after a manufacturing process and comparing the images to images generated by a generative deep learning model. The model generates images of ideal wafers after the manufacturing process by receiving a wafer design pattern as input.
Chuo et al. (US 2020/0105500 A1) teaches methods and systems for detecting defects on a wafer. The method involves acquiring an SEM image of a region of a wafer, generating an image of an ideal wafer based on the design pattern of the wafer and/or the SEM image, and comparing the SEM image with the generated image to determine defect locations, types, and causes.
Gadre et al. (US 2023/0061513 A1) teaches methods and systems for receiving sensor values from semiconductor manufacturing equipment and determining causes of failure during manufacturing steps.
Zika et al. (US 6,040,912 A) teaches methods and systems for determining systematic pattern defects by comparing two manufacturing processes. A first wafer undergoes a first manufacturing process, and a second wafer undergoes a second manufacturing process. The difference between the resulting patterns is analyzed to determine defects and determine the best manufacturing process.
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/Eric Shoemaker/
Patent Examiner
/JENNIFER MEHMOOD/Supervisory Patent Examiner, Art Unit 2664