Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note: The Examiner notes that for all claims, a person of ordinary skill in the art is aware that the broadest reasonable interpretation of the term “electrically connected” used in the rejection includes either parallel or series connections. As evidence , see Ong et al. (US 20170263836 A1) hereafter referred to as Ong paragraph 0137 “Removing the connection webs 150 has the consequence that the short-circuit connections of the leadframe sections 120 serving as cathodes and anodes are interrupted as a result of which the semiconductor chips 170 or semiconductor chip groups now electrically connect in series. To put it another way, an electrical series connection of the semiconductor chips 170 or semiconductor chip groups arranged in the mounting regions 140 is provided as a result of the removal of the connection webs 150. In this case, the leadframe sections 120 arranged next to one another form a part of the electrical series connection”. The Examiner recommends that the Applicant clarify the claims to specify parallel or series connection using phrases such as “in physical contact with the electrode” or “connected by a contiguous metal electrode” etc. As an example the Examiner notes that decorative lighting used during festivals are series connected light emitting diodes, thus the same electrical current flows through all the light emitting diodes in the series connection, and in each of those light emitting diodes the current flows from the anode to the cathode because the anode is electrically connected to the positive of the power supply and the cathode is electrically connected to the negative of the power supply , and this is standard electrical engineering known to a person of ordinary skill in the art.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 6, 8, 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 20080203424 A1) hereafter referred to as Chen
In regard to claim 1 Chen teaches a semiconductor device [see Fig. 6] having a first terminal [see two terminals connected to Vhigh and Vlow] and a second terminal, the semiconductor device comprising:
a semiconductor die [see Fig. 6];
a plurality of diode unit cells [see between the STI see P+/PW/N+] integrated on the semiconductor die and being electrically connected between [see Fig. 6 the current flow through the interconnections] the first and second terminal, each unit cell comprising a first region of a first charge type [see either of P and N] in the semiconductor die and a second region [see the other of P and N] of a second charge type in the semiconductor die;
an isolation structure [see STI] arranged in the semiconductor die, the isolation structure being configured to electrically isolate [see Fig. 6 the current flow through the interconnections] the plurality of unit cells from one another in the semiconductor die;
a plurality of contacts [see Fig. 6 the current flow through the interconnections] comprising first contacts [see the plurality of contacts on the P+ and N+, see the electrical connectivity flows from Vhigh to Vlow through contacts on P+ and N+, through each cell and the interconnections between the cells shown in Fig. 6] that are electrically connected to the first terminal and second contacts that are electrically connected to the second terminal; and
wherein each contact among the first and second contacts is electrically connected to the first region [see the interconnections between cells is connecting N+ to P+ thus series connected] of a unit cell among the plurality of unit cells and to the second region of another unit cell among the plurality of unit cells.
In regard to claim 2 Chen teaches wherein the plurality of unit cells are arranged in a plurality [“plurality” means at least two groups, and in fact, the Fig. 6 can be divided into two groups i.e. the left 2 cells can be the first “group” and the right two cells can be the second “group”, and thus the limitation is satisfied] of groups, each group having two or more unit cells [see Fig. 6 see a total of 4 cells are shown as example i.e. each group has two cells in this example] that are connected in series via one or more intermediate contacts [see the interconnections between cells is connecting N+ to P+ thus series connected], each intermediate contact being electrically connected to the first region of a respective unit cell among unit cells in the group and to the second region of another unit cell among unit cells in the group.
In regard to claim 4 Chen teaches wherein the plurality of contacts and the first and second interconnecting portions are arranged in a metal layer, or in one or more metal layers of a metal layer stack, arranged on top of the semiconductor die; and/or wherein the first charge type corresponds to [see Fig. 6 the interconnections between cells is connecting N+ to P+ charge types] a p-type doping and wherein the second charge type corresponds to an n-type doping, or vice versa.
In regard to claim 6 Chen teaches wherein unit cells that are electrically connected to a same first contact, a same second contact and/or, if applicable, a same intermediate contact are [see Fig. 6 the interconnections between adjacently arranged cells is connecting N+ to P+ charge types] adjacently arranged; and/or wherein the plurality of groups has a first portion that is arranged in parallel to one another between the first and second terminal, and wherein the plurality of groups has a second portion that is arranged in anti-parallel to the first portion between the first and second terminal; and/or wherein the first contacts are electrically connected to one another via a first interconnecting portion, the first interconnecting portion forming or being electrically connected to the first terminal, and/or wherein the second contacts are electrically connected to one another via a second interconnecting portion, the second interconnecting portion forming or being electrically connected to the second terminal; and/or wherein the first contacts, the second contacts and/or, the intermediate contacts are finger-shaped.
In regard to claim 8 Chen teaches wherein the plurality of contacts and the first and second interconnecting portions are arranged in a metal layer, or in one or more metal layers of a metal layer stack, arranged on top of the semiconductor die; and/or wherein the first charge type corresponds to [see Fig. 6 the interconnections between cells is connecting N+ to P+ charge types] a p-type doping and wherein the second charge type corresponds to an n-type doping, or vice versa.
In regard to claim 9 Chen teaches wherein the first contacts and the second contacts are alternatingly [see Fig. 6 the interconnections between cells is connecting N+ to P+ charge types, see from the left the sequence is P-N-P-N- P-N-P-N] arranged, wherein the intermediate contacts are arranged in between the first contacts and second contacts.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3, 4, 7, 8, 10, 12, 15, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen
In regard to claim 3 Chen teaches wherein the semiconductor die comprises a semiconductor [see Fig. 6, see P-sub see paragraph 0003 “P-type (P) substrate”] substrate but does not state “and an epitaxial layer, and wherein the plurality of unit cells are formed in the epitaxial layer”.
See Fig. 7 see paragraph 0035 “N+ buried layer 12 is disposed on the P substrate 14. PW 16 and N+ sinker 18 are disposed on N+ buried layer 12 and generally formed in an epitaxy silicon layer of a BiCMOS process”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Chen to include “and an epitaxial layer, and wherein the plurality of unit cells are formed in the epitaxial layer”.
Thus it would be obvious to combine the embodiments to arrive at the claimed invention.
The motivation is that epitaxial layers are known to be good quality and useful to get good performance in semiconductor devices.
In regard to claim 4 Chen teaches wherein the plurality of contacts and the first and second interconnecting portions are arranged [see the plurality of contacts on the P+ and N+, see the electrical connectivity flows from Vhigh to Vlow through contacts on P+ and N+, through each cell and the interconnections between the cells shown in Fig. 6] on top of the semiconductor die; and/or wherein the first charge type corresponds to a p-type doping and wherein the second charge type corresponds to an n-type doping, or vice versa.
but does not state in Fig. 6 “arranged in a metal layer, or in one or more metal layers of a metal layer stack”.
See Fig. 7 see paragraph 0036 “Wire connections 30 generally consist of contacts, metal lines, vias and the like”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Chen to include “arranged in a metal layer, or in one or more metal layers of a metal layer stack”.
Thus it would be obvious to combine the embodiments to arrive at the claimed invention.
The motivation is that metal lines are standard and are known to give good conductivity and performance in semiconductor circuits.
In regard to claim 7 Chen teaches wherein the semiconductor die comprises a semiconductor substrate [see Fig. 6, see P-sub see paragraph 0003 “P-type (P) substrate”] but does not state “and an epitaxial layer, and wherein the plurality of unit cells are formed in the epitaxial layer”.
See Fig. 7 see paragraph 0035 “N+ buried layer 12 is disposed on the P substrate 14. PW 16 and N+ sinker 18 are disposed on N+ buried layer 12 and generally formed in an epitaxy silicon layer of a BiCMOS process”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Chen to include “and an epitaxial layer, and wherein the plurality of unit cells are formed in the epitaxial layer”.
Thus it would be obvious to combine the embodiments to arrive at the claimed invention.
The motivation is that epitaxial layers are known to be good quality and useful to get good performance in semiconductor devices.
In regard to claim 8 Chen teaches wherein the plurality of contacts and the first and second interconnecting portions are [see the plurality of contacts on the P+ and N+, see the electrical connectivity flows from Vhigh to Vlow through contacts on P+ and N+, through each cell and the interconnections between the cells shown in Fig. 6] arranged on top of the semiconductor die; and/or wherein the first charge type corresponds to a p-type doping and wherein the second charge type corresponds to an n-type doping, or vice versa.
but does not state in Fig. 6 “arranged in a metal layer, or in one or more metal layers of a metal layer stack”.
See Fig. 7 see paragraph 0036 “Wire connections 30 generally consist of contacts, metal lines, vias and the like”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Chen to include “arranged in a metal layer, or in one or more metal layers of a metal layer stack”.
Thus it would be obvious to combine the embodiments to arrive at the claimed invention.
The motivation is that metal lines are standard and are known to give good conductivity and performance in semiconductor circuits.
In regard to claim 10 Chen teaches wherein the isolation structure comprises a plurality of vertical isolation structures [see Fig. 6 has STI with vertical extensions down] and a plurality of lateral [see “In FIG. 6, each diode has a heavy-doped N-type (N+) buried layer 94”] isolation structures, wherein the vertical isolation structures are each arranged in between [see Fig. 6] adjacent unit cells among the plurality of unit cells, and wherein the plurality of lateral isolation structures are each arranged below [see Fig. 6] a respective unit cell among the plurality of unit cells with respect to a top surface of the semiconductor die, wherein the vertical isolation structures extend from the top surface at least to the [see Fig. 6] lateral isolation structures, wherein the vertical isolation structures each extend from the top surface in a first direction [see Fig. 6 down] that is substantially perpendicular to the top surface, and wherein the lateral isolation structures each extend in a second direction [see Fig. 6 horizontal] that is substantially parallel to the top surface.
In regard to claim 12 Chen teaches wherein the plurality of lateral isolation structures is formed by respective PN junctions [see “In FIG. 6, each diode has a heavy-doped N-type (N+) buried layer 94”] extending between the vertical isolation structures arranged adjacent to a corresponding unit cell.
In regard to claim 15 Chen teaches wherein the epitaxial layer is of a different charge type with respect to the semiconductor substrate, and wherein the PN junctions are formed by junctions between the epitaxial layer and the semiconductor substrate; or wherein the epitaxial layer has a well region [see under broadest reasonable interpretation, a “well” is just a doped region, see “In FIG. 6, each diode has a heavy-doped N-type (N+) buried layer 94”] in which the plurality of unit cells are arranged of a different charge type with respect to a remainder of the epitaxial layer and/or the semiconductor substrate, and wherein the PN junctions are formed by respective junctions between the epitaxial layer and the semiconductor substrate, and/or by respective junctions between the well region [see junction between PW and 94] and the epitaxial layer.
In regard to claim 16 Chen teaches wherein the PN junctions are each formed by a respective first buried region [i.e. “N-type (N+) buried layer 94”] of the first or second charge type in the semiconductor die and a respective second buried region [upper part of P-sub] of the second or first charge type respectively in the semiconductor die, and wherein each of the second buried regions are spaced apart [see P-sub is below 94] from the epitaxial layer by a corresponding first buried region.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Voldman (see IDS filed by Applicant on 12/29/2022)
In regard to claim 5 Chen does not specifically teach further comprising a first portion of intermediate contacts arranged in an interleaved manner with first contacts, and a second portion of intermediate contacts are arranged in an interleaved manner with second contacts, and wherein the intermediate contacts among the first portion of intermediate contacts are each electrically connected to at least one intermediate contact among the second portion of intermediate contacts.
However this layout of contact metallization is a standard design choice, see Voldman Fig. 4.13 see the left 3 contacts, see that the second contact from the left is interleaved with the first and thitd contacts.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Chen to include further comprising a first portion of intermediate contacts arranged in an interleaved manner with first contacts, and a second portion of intermediate contacts are arranged in an interleaved manner with second contacts, and wherein the intermediate contacts among the first portion of intermediate contacts are each electrically connected to at least one intermediate contact among the second portion of intermediate contacts.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to obtain good performance in ESD circuit layout design rules.
Claim(s) 11, 13, 14, 17, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Zhan et al. (US 20160013177 A1) hereafter referred to as Zhan
In regard to claim 11 Chen does not teach wherein the lateral isolation structures are formed by respective buried insulating layers, wherein the buried insulating layers are buried oxide layers, and wherein the buried insulating layers together form respective portions of a contiguous buried insulating layer.
See Chen paragraph 0038 “In FIG. 7, an isolation region exemplarily comprises a shallow trench 22a and a deep trench 20, both of isolation material, such as silicon dioxide”.
See Zhan teaches SOI see paragraph 0021 “In exemplary embodiments, the substrate 110 of the packaged electronic device 1000 including stacked protection circuitry 108 is realized as a SOI substrate that provides vertical isolation” see alternative to Chen see “In this regard, the vertical isolation provided by the SOI substrate combined with lateral isolation (e.g., deep trench isolation) between instances of the protection circuitry 108 prevents the substrate voltage underlying one instance of the protection circuitry 108 from influencing the breakdown of an adjacent instance of the protection circuitry 108. In alternative embodiments, instances of the protection circuitry 108 may be stacked when fabricated on a bulk substrate by providing an appropriate doping profile that isolates the protection circuitry 108 from the surrounding bulk substrate (e.g., by using N-type well regions and buried regions to provide isolation from a P-type bulk substrate)” “In accordance with one embodiment, the insulating layer 304 is realized as an oxide layer formed in a subsurface region of the semiconductor substrate 301, also known as a buried oxide (BOX) layer”, see Fig. 7 see paragraph 0036 “deep trench isolation (DTI) to provide deep isolation regions 324, 326 of dielectric material” “expose the peripheral portions of the epitaxial layer 312 and seed layer 306, which are then etched until the buried layer 304 is exposed, and thereafter, a dielectric material, such as an oxide material, may be deposited in the trenches or grown on exposed surfaces of the trenches to fill the trenches, resulting in deep isolation regions 324, 326”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Chen to include wherein the lateral isolation structures are formed by respective buried insulating layers, wherein the buried insulating layers are buried oxide layers, and wherein the buried insulating layers together form respective portions of a contiguous buried insulating layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that the excellent isolation benefit of SOI is known to give high performamance circuits.
In regard to claim 13 Chen and Zhan as combined teaches wherein the vertical isolation structures each comprise a trench [see STI of Chen see paragraph 0038 “In FIG. 7, an isolation region exemplarily comprises a shallow trench 22a and a deep trench 20, both of isolation material, such as silicon dioxide”, see combination Zhan above], and wherein the trench has an insulating material arranged therein, wherein the insulating material is an oxide material.
In regard to claim 14 Chen and Zhan as combined teaches wherein one of the first and second region of each unit cell among the plurality of unit cells extends [see Chen Fig. 6 see PW reaches 94, see combination Zhan] from a top surface of the semiconductor die to the buried insulating layer, but does not state wherein the epitaxial layer or a well region in the epitaxial layer in which the plurality of unit cells are arranged is of the second charge type, and wherein the vertical isolation structures are each formed by a respective PN junction between the one of the first and second region of a respective unit cell and the epitaxial layer or the well region; and/or wherein the first region and the second region of each unit cell among the plurality of unit cells extends from a top surface of the semiconductor die to the buried insulating layer, and wherein the vertical isolation structures are formed by respective PN junctions between one of the first or second region of a respective unit cell and the epitaxial layer or, if applicable, a well region in the epitaxial layer in which the plurality of unit cells are arranged, or between the first region of a respective unit cell and the second region of a unit cell arranged directly adjacent to the first region.
However see Chen Fig. 2, see Fig. 4 see NW in a P-sub, see P-sub extends between the NW, thus the lateral isolation can just be PN junction.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Chen to include “wherein the epitaxial layer or a well region in the epitaxial layer in which the plurality of unit cells are arranged is of the second charge type, and wherein the vertical isolation structures are each formed by a respective PN junction between the one of the first and second region of a respective unit cell and the epitaxial layer or the well region”.
Thus it would be obvious to combine the embodiments to arrive at the claimed invention.
The motivation is ease of manufacture by using PN junction for isolation rather than STI and/or deep trench isolation.
In regard to claim 17 Chen teaches an electrostatic discharge, ESD, protection device [under broadest reasonable interpretation the ESD circuit is “device”, see paragraph 0001, 0050 “The present invention relates in general to a diode providing electrostatic discharge (ESD) protection” “Among ESD protection devices, a diode has one of the simplest structures”, see application see Figs. 14, 15, 16 “FIG. 14 illustrates an ESD protection circuit for an input/output port according to embodiments of the present invention” “thereby protecting internal circuits from ESD damage”] configured to be electrically connected to an electronic circuit and to protect the electronic circuit from ESD events, wherein the ESD protection device comprises one or more semiconductor devices as defined in claim 1,
but does not state and wherein the ESD protection device is a packaged device [see that the claim does not state that the ESD device is in a separate package than the electronic circuit].
However packages are standard in the art, see Zhan paragraph 0014 “Turning now to FIG. 1, an exemplary electronic device package 100 includes one or more package interfaces 102, 104, functional circuitry 106 coupled to the package interfaces 102, 104, and protection circuitry 108 coupled to the interfaces 102, 104”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Chen to include and wherein the ESD protection device is a packaged device.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that packages are useful to protect circuitry and provide good physical and electrical connectivity to external circuits.
In regard to claim 18 Chen teaches a device comprising an electronic circuit [under broadest reasonable interpretation the ESD circuit is “device”, see paragraph 0001, 0050 “The present invention relates in general to a diode providing electrostatic discharge (ESD) protection, and in particular to a diode manufactured by bipolar complementary metal oxide semiconductor (BiCMOS) processes” “Among ESD protection devices, a diode has one of the simplest structures”, see application see Figs. 14, 15, 16 “FIG. 14 illustrates an ESD protection circuit for an input/output port according to embodiments of the present invention” “thereby protecting internal circuits from ESD damage” “This ESD protection circuit is especially suitable for radio frequency (RF) integrated circuits (ICs)”] integrated on a semiconductor die, and one or more semiconductor devices as defined in claim 1, wherein the one or more semiconductor devices are integrated on the semiconductor die and [see above] are electrically connected to the electronic circuit to protect the electronic circuit from ESD events,
but does not state and wherein the device is a packaged device.
However packages are standard in the art, see Zhan paragraph 0014 “Turning now to FIG. 1, an exemplary electronic device package 100 includes one or more package interfaces 102, 104, functional circuitry 106 coupled to the package interfaces 102, 104, and protection circuitry 108 coupled to the interfaces 102, 104”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Chen to include and wherein the device is a packaged device.
Thus it would be obvious to combine the references to arrive at the claimed invention.
Response to Arguments
Applicant's arguments filed 11/6/2025 have been fully considered but they are not persuasive.
On page 9 the Applicant argues “The Office Action alleges that "the plurality of contacts on the P+ and N+,see the electrical connectivity flows from VHigh to VHow through contacts onP+ and N+, through each cell and the interconnections between the cellsshown in Fig. 6" show the above recited "a plurality of contacts comprisingfirst contacts that are electrically connected to the first terminal" and that"second contacts that are electrically connected to the second terminal." Assuch the Office Action makes no distinction between contacts connected tothe Vhigh and VIow lines. That is to say, with this interpretation any contact onthe line is both a first and second contact. This is an unreasonably broadinterpretation of the features of claim 1”.
The Examiner responds that, see Fig. 6 of Chen, see that each P+ region has its own contact and each N+ region has its own contact and the N+ contact is electrically connected to the P+ contact and this is a series connection and is standard electrical engineering known to a person of ordinary skill in the art. The Examiner responds that in each diode current can only flow when the P+ is biased higher than the N+, thus it is untrue for the Applicant to say that “the Office Action makes no distinction between contacts connected tothe Vhigh and VIow lines” because the current flow is based on the polarity in each diode and the current only flows because the contacts are electrically connected to the power supply and forward biased.
The Examiner responds that for all claims, a person of ordinary skill in the art is aware that the broadest reasonable interpretation of the term “electrically connected” used in the rejection includes either parallel or series connections. As evidence , see Ong et al. (US 20170263836 A1) hereafter referred to as Ong paragraph 0137 “Removing the connection webs 150 has the consequence that the short-circuit connections of the leadframe sections 120 serving as cathodes and anodes are interrupted as a result of which the semiconductor chips 170 or semiconductor chip groups now electrically connect in series. To put it another way, an electrical series connection of the semiconductor chips 170 or semiconductor chip groups arranged in the mounting regions 140 is provided as a result of the removal of the connection webs 150. In this case, the leadframe sections 120 arranged next to one another form a part of the electrical series connection”. The Examiner recommends that the Applicant clarify the claims to specify parallel or series connection using phrases such as “in physical contact with the electrode” or “connected by a contiguous metal electrode” etc. As an example the Examiner notes that decorative lighting used during festivals are series connected light emitting diodes, thus the same electrical current flows through all the light emitting diodes in the series connection, and in each of those light emitting diodes the current flows from the anode to the cathode because the anode is electrically connected to the positive of the power supply and the cathode is electrically connected to the negative of the power supply , and this is standard electrical engineering known to a person of ordinary skill in the art.
On page 10, 11 the Applicant argues “Even without resort to the specification, the Examiner's claiminterpretation does not accord with the broadest reasonable interpretation,as it makes no distinction between "a plurality of contacts comprising firstcontacts that are electrically connected to the first terminal" and "secondcontacts that are electrically connected to the second terminal" as plainlyrecited in claim 1.Figure 6 of Chen, annotated below, shows only one contact connectedto Vhigh and one contact connected to Vlow (see blue circles).1 The PTO's construction here, though certainly broad, is unreasonably broad. Thebroadest-construction rubric coupled with the term "comprising" does not give the PTO anunfettered license to interpret claims to embrace anything remotely related to the claimedinvention. Rather, claims should always be read in light of the specification and teachings inthe underlying patent. See Schriber-Schroth Co. V. Cleveland Trust Co., 311 U.S. 211, 217(1940) ("The claims of a patent are always to be read or interpreted in light of itsspecifications."). In that vein, the express language of the claim and the specificationrequire the finishing material to be the top and final layer on the surface being finished.See, e.g., '514 patent, col.1 II.15-20 ("The present invention is directed generally to amaterial and method for quickly and easily producing a transparent wear resistant finish ona smooth flat surface subject to wear and more particularly to a material and method forfinishing a floor"). The PTO's proffered construction therefore fails The remaining interconnections (in red box) are though a diode string,which are each connected to one another by wires on the contacts. SeeChen, paragraph [0007]: "However, with regard to a diode string with ESDprotection for SiGe BiCMOS processes, the diode string in FIG. 6 is generallyutilized." Applicant also refers to the similar structures shown in FIG. 13Band FIG. 14: As shown above, the diode string 62 only has two contacts thatelectrically connect to VSS and VDD. The "interconnections" of the diodestring connect the series connected diodes in between. They do not show"first contacts that are electrically connected to the first terminal" and aseparate set of "second contacts that are electrically connected to thesecond terminal" as recited in claim 1.Next, at page 3 the Office Action alleges "the interconnections betweencells is connecting N+ to P+ thus series connected" shows "wherein eachcontact among the first and second contacts is electrically connected to thefirst region of a unit cell among the plurality of unit cells and to the secondregion of another unit cell among the plurality of unit cells". As outlinedabove, the series connected diodes and interconnected contacts annotated inthe red box are not "each contact among the first and second contacts" asrecited in claim 1. For the reasons given above Chen fails to disclose (or suggest)independent claim 1. Thus, Applicant respectfully requests reconsiderationand withdrawal of the rejection ”.
See above, the Examiner responds that , see Fig. 6 of Chen, see that each P+ region has its own contact and each N+ region has its own contact and the N+ contact is electrically connected to the P+ contact and this is a series connection and is standard electrical engineering known to a person of ordinary skill in the art. The Examiner responds that in each diode current can only flow when the P+ is biased higher than the N+, thus it is untrue for the Applicant to say “As shown above, the diode string 62 only has two contacts thatelectrically connect to VSS and VDD” because the current flow is based on the polarity in each diode and the current only flows because the contacts are electrically connected to the power supply and forward biased.
The Examiner responds that for all claims, a person of ordinary skill in the art is aware that the broadest reasonable interpretation of the term “electrically connected” used in the rejection includes either parallel or series connections. As evidence , see Ong et al. (US 20170263836 A1) hereafter referred to as Ong paragraph 0137 “Removing the connection webs 150 has the consequence that the short-circuit connections of the leadframe sections 120 serving as cathodes and anodes are interrupted as a result of which the semiconductor chips 170 or semiconductor chip groups now electrically connect in series. To put it another way, an electrical series connection of the semiconductor chips 170 or semiconductor chip groups arranged in the mounting regions 140 is provided as a result of the removal of the connection webs 150. In this case, the leadframe sections 120 arranged next to one another form a part of the electrical series connection”. The Examiner recommends that the Applicant clarify the claims to specify parallel or series connection using phrases such as “in physical contact with the electrode” or “connected by a contiguous metal electrode” etc. As an example the Examiner notes that decorative lighting used during festivals are series connected light emitting diodes, thus the same electrical current flows through all the light emitting diodes in the series connection, and in each of those light emitting diodes the current flows from the anode to the cathode because the anode is electrically connected to the positive of the power supply and the cathode is electrically connected to the negative of the power supply , and this is standard electrical engineering known to a person of ordinary skill in the art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ozard (US 7071514 B1) teaches epitaxial layers, “structure shown in FIG. 8 is fabricated from a layered semiconductor structure having a substrate (not shown), subcollector 805, collector 710, base 720, and emitter layers. Each layer may be epitaxially grown and doped using the methods described in Sze to produce semiconductor layers with the desired properties” , see Ozard teaches use of metal “Electrical connection to the diode emitter finger 730 may include a metal layer 830 and a metal interconnect layer 835. The metal interconnect layer 835 may be connected to the collector 710 through a metal air bridge 760 such as the one described in U.S. Pat. No. 6,724,067, for example. The air bridge 760 is deposited on a collector contact, which may include a metal contact 806 and a metal interconnect contact 807”.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt D Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893