Prosecution Insights
Last updated: April 19, 2026
Application No. 18/147,751

TRAFFIC MANAGEMENT IN EDGE CACHING

Non-Final OA §102§103
Filed
Dec 29, 2022
Examiner
HLAING, SOE MIN
Art Unit
2451
Tech Center
2400 — Computer Networks
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
288 granted / 353 resolved
+23.6% vs TC avg
Strong +18% interview lift
Without
With
+17.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
18 currently pending
Career history
371
Total Applications
across all art units

Statute-Specific Performance

§101
7.2%
-32.8% vs TC avg
§103
60.2%
+20.2% vs TC avg
§102
15.2%
-24.8% vs TC avg
§112
5.6%
-34.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 353 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claims 6, 13 and 20 are objected to because of the following informalities: Claims 6, 13 and 20 recites "the content previously stored in the target system." without having antecedent basis. Appropriate correction(s) is/are required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 5, 8, 12, 15 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Saito et al. (US PG PUB 20130132673), hereinafter "Saito". Regarding Claim1, 8 and 15, Saito discloses: (Claim 1) A computer-implemented method comprising: (Claim 8) A system (Fig. 1 and ¶ 0032 - 0033) comprising: a memory having computer readable instructions (i.e. memory 12, 42, 34 storing program instructions) (Fig. 1 and ¶ 0034 – 0036); and a computer for executing the computer readable instructions (computer CPUs 22 & 32 for executing program instructions) (22 & 32 – Fig. 1 and ¶ 0033 – 0034), the computer readable instructions controlling the computer to perform operations comprising: (Claim 15) A computer program product comprising a computer readable storage medium having program instructions embodied therewith (i.e. memory 12, 42, 34 storing program instructions) (Fig. 1 and ¶ 0034 – 0036), the program instructions executable by a computer to cause the computer to perform operations (computer CPUs 22 & 32 for executing program instructions) (¶ 0033 – 0034) comprising: responsive to an emergency trigger, receiving, by an edge device / the computer, a map from a target system (i.e. responsive to forced destage request [i.e. an emergency trigger], edge storage apparatus 20 [i.e. an edge device / the computer] may receive logical unit identification information 333 [i.e. a map] registered in the forced destage request from core storage apparatus 30 [i.e. a target system]; Note that forced destage requests are issued in order to prevent overflow [i.e. therefore, it is an emergency trigger]) (20 & 30 - Fig. 1, ¶ 0182 and ¶ 0189 – 0190), the edge device / the computer comprising a cache having a plurality of blocks (i.e. the edge storage apparatus 20 [i.e. the edge device / the computer] includes cache memory 25 storing various data blocks [i.e. a plurality of blocks] each of which corresponding to data identification information 233) (Fig. 5, ¶ 0061 and ¶ 0064), wherein the map is representative of content in a data volume of the target system (i.e. the logical unit identification information 333 [i.e. the map] indicate address, e.g. logical unit number LUN [i.e. representative], of the data [i.e. content] stored in logical unit 101 [i.e. a data volume] of the core storage apparatus 30 [i.e. the target system]) (101 – Fig. 2, ¶ 0122 and ¶ 0189); determining, by the edge device / the computer, at least one block of the plurality of blocks in the cache different from the content in the data volume based on the map (i.e. the edge storage apparatus 20 [i.e. the edge device / the computer] may determine a dirty data [i.e. at least one block of the plurality of blocks] in the virtual logical unit 102 of the cache memory 25 [i.e. the cache] based on the logical unit identification information 333 [i.e. the map]; Note that the dirty data is a modified version [i.e. different] of the data [i.e. the content] stored in the logical unit 101 [i.e. the data volume]) (¶ 0065, ¶ 0073 and ¶ 0189 - 0190); and sending, by the edge device / the computer, the at least one block in the cache to the target system, responsive to the emergency trigger (i.e. upon receipt of the forced destage request [i.e. responsive to the emergency trigger], the edge storage apparatus 20 [i.e. the edge device / the computer] destage [i.e. sending] the dirty data [i.e. the at least one block] in the virtual logical unit 102 of the cache memory 25 [i.e. the cache] to the core storage apparatus 30 [i.e. the target system]) (¶ 0054 and ¶ 0190). Regarding Claims 5, 12 and 19 Saito discloses: wherein the determining the at least one block of the plurality of blocks in the cache is utilized to avoid sending other blocks of the plurality of blocks to the target system, responsive to the emergency trigger (i.e. in response to the forced destage request [i.e. responsive to the emergency trigger], the edge storage apparatus 20 [i.e. the edge device] determines a particular dirty data [i.e. at least one block of the plurality of blocks in the cache] as a modified version of the data stored in corresponding address of the logical unit 101 [i.e. the target system]; such determination is made in order to send only the relevant dirty data [i.e. avoid sending other blocks of the plurality of blocks] that corresponds to the one already stored in the logical unit 101 [i.e. the target system]) (¶ 0189 – 0190 and ¶ 0200). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2, 9 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saito as applied to claims 1, 8 and 15 above, and further in view of Agombar et al. (US PG PUB 20170351615), hereinafter "Agombar". Regarding Claims 2, 9 and 16 Saito discloses all the features with respect to Claims 1, 8 and 15 as described above. However, Saito does not explicitly disclose: wherein the edge device / the computer receives an algorithm associated with the map. On the other hand, in the same field of endeavor, Agombar teaches: wherein the edge device / the computer receives an algorithm associated with the map (i.e. cache appliance 310 [i.e. the edge device / the computer] may receive input utilization model [i.e. algorithm] associated with destaging of the data occupying a data volume represented with Logical Unit Number LUN [i.e. the map]) (310 – Fig. 3, ¶ 0033, ¶ 0041 and ¶ 0063). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method/system/computer readable medium of Saito to include wherein the edge device / the computer receives an algorithm associated with the map as taught by Agombar in order to track resource utilization associated with cache operations (310 – Fig. 3, ¶ 0033, ¶ 0041 and ¶ 0063). Claim(s) 3, 4, 10, 11, 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saito as applied to claims 1, 8 and 15 above, and further in view of Wu et al. (US PG PUB 20220012218), hereinafter "Wu". Regarding Claims 3, 10 and 17 Saito discloses all the features with respect to Claims 1, 8 and 15 as described above. However, Saito does not explicitly disclose: wherein the edge device / the computer is configured to utilize an algorithm to compare the cache to the content in the data volume based on the map. On the other hand, in the same field of endeavor, Wu teaches: wherein the edge device is configured to utilize an algorithm to compare the cache to the content in the data volume based on the map (i.e. based on target logical address, e.g. LBA or LUN [i.e. based on the map], cache [i.e. the edge device / the computer] may utilize one or more processes [i.e. an algorithm] to determine whether the fingerprint of the data block being destaged from the cache match [i.e. compare the cash to] a fingerprint of the fingerprint of a data block [i.e. the content] stored in backend physical storage [i.e. the data volume]) (¶ 0067, ¶ 0085 and ¶ 0088). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method/system/computer readable medium of Saito to include wherein the edge device / the computer is configured to utilize an algorithm to compare the cache to the content in the data volume based on the map as taught by Wu in order to identify whether the data block being destaged from the cache matches to the data block already stored on backend physical storage (¶ 0067, ¶ 0085 and ¶ 0088). Regarding Claims 4, 11 and 18 Saito and Wu disclose, in particular Wu teaches: wherein the edge device / the computer is configured to utilize the algorithm to determine a fingerprint of the at least one block that is different from predetermined fingerprints of the map (i.e. the cache [i.e. the edge device / the computer] may utilize one or more processes [i.e. the algorithm] to determine whether the fingerprint of the data block being destaged from the cache match a fingerprint of the fingerprint of a data block [i.e. the content] stored in backend physical storage; If there is not already an existing matching entry in the fingerprint hash table [i.e. determine a fingerprint of the at least one block that is different from predetermined fingerprints of the map] for the fingerprint, then the data block is a new unique data block) (¶ 0067, ¶ 0085 and ¶ 0088). The prior art used in the rejection of the current claim is combined using the same motivations as was applied in claims 3, 8 and 15. Claim(s) 6, 13 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saito as applied to claims 1, 8 and 15 above, and further in view of Lee et al. (US PG PUB 20030229767), hereinafter "Lee". Regarding Claims 6, 13 and 20, Saito discloses all the features with respect to Claims 1, 8 and 15 as described above. However, Saito does not explicitly disclose: wherein at least one updated pointer corresponding to one block of the plurality of blocks is sent to the target system, the at least one updated pointer identifying the content previously stored in the target system for the one block. On the other hand, in the same field of endeavor, Lee teaches: wherein at least one updated pointer corresponding to one block of the plurality of blocks is sent to the target system (i.e. metadata controller 20 issues/sends a destage request including the pointer [i.e. at least one updated pointer] corresponding to the data block_215 [i.e. one block of the plurality blocks] to data mover 30 [i.e. the target system], wherein the metadata controller updates the metadata comprised of the pointer to reflect the location of the destaged data blocks [i.e. in other words, pointer is updated]) (Fig. 4, ¶ 0038, ¶ 0046 and ¶ 0057), the at least one updated pointer identifying the content previously stored in the target system for the one block (i.e. multiple versions of the data block [i.e. the content previously stored in the target system] may be identified by the pointer [i.e. the at least one updated pointer]) (¶ 0039 and ¶ 0057). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method/system/computer readable medium of Saito to include wherein at least one updated pointer corresponding to one block of the plurality of blocks is sent to the target system, the at least one updated pointer identifying the content previously stored in the target system for the one block as taught by Lee so that data blocks may be moved from cache to storage location based on the metadata that points locations of the data blocks (¶ 0039 and ¶ 0057). Claim(s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saito as applied to claims 1 and 8 above, and further in view of Yuasa et al. (US PG PUB 20140317436), hereinafter "Yuasa". Regarding Claims 7 and 14, Saito discloses all the features with respect to Claims 1 and 8 as described above. In addition, Saito further teaches: wherein: the sending the at least one block in the cache to the target system causes the target system to store the at least one block without validating a fingerprint for the at least one block (i.e. the edge storage apparatus 20 [i.e. cache] destages/sends the dirty data [i.e. the at least one block in the cache] corresponding to the cache management entry 231 selected in step SP830 to the core storage apparatus 30 [i.e. the target system]; Then, the dirty data is written into logical unit 101 of the core storage apparatus 30 [i.e. the target system stores the at least one block]; Note that the core storage apparatus 30 stores the data without going through any validation procedure [i.e. without validating a fingerprint for the at least one block]) (Fig. 13, ¶ 0138 - 0139). However, Saito does not explicitly disclose: the emergency trigger occurs responsive to a power failure at the edge device / the computer such that the edge device / the computer requires backup power. On the other hand, in the same field of endeavor, Yuasa teaches: the emergency trigger occurs responsive to a power failure at the edge device / the computer such that the edge device / the computer requires backup power (i.e. in response to the power failure determination register 16d indicating activation associated with transition from the memory backup mode to the cache destage mode [i.e. responsive to a power failure at the edge device] such that the cache [i.e. the edge device] is being operated on battery/backup power [i.e. the edge device requires backup power], the CPU 11 executes the cache destage processing [i.e. the emergency trigger occurs], and writes the cache data from the cache memory 12 into the non-volatile memory 13) (¶ 0007 and ¶ 0112 - 0113). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method/system/computer readable medium of Saito to include wherein the emergency trigger occurs responsive to a power failure at the edge device / the computer such that the edge device / the computer requires backup power as taught by Yuasa in order to avoid loss of data during a power failure (¶ 0007 and ¶ 0112 - 0113). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOE MIN HLAING whose telephone number is (303)297-4282. The examiner can normally be reached Monday-Friday 9AM - 5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christopher Parry can be reached at 571-272-8328. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Soe Hlaing/ Primary Examiner, Art Unit 2451
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Prosecution Timeline

Dec 29, 2022
Application Filed
Nov 06, 2023
Response after Non-Final Action
Mar 06, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
99%
With Interview (+17.5%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 353 resolved cases by this examiner. Grant probability derived from career allow rate.

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